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514 lines
13 KiB
514 lines
13 KiB
// SPDX-License-Identifier: GPL-2.0 |
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/* |
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* Renesas RIIC driver |
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* |
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* Copyright (C) 2013 Wolfram Sang <[email protected]> |
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* Copyright (C) 2013 Renesas Solutions Corp. |
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*/ |
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|
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/* |
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* This i2c core has a lot of interrupts, namely 8. We use their chaining as |
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* some kind of state machine. |
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* |
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* 1) The main xfer routine kicks off a transmission by putting the start bit |
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* (or repeated start) on the bus and enabling the transmit interrupt (TIE) |
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* since we need to send the slave address + RW bit in every case. |
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* |
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* 2) TIE sends slave address + RW bit and selects how to continue. |
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* |
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* 3a) Write case: We keep utilizing TIE as long as we have data to send. If we |
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* are done, we switch over to the transmission done interrupt (TEIE) and mark |
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* the message as completed (includes sending STOP) there. |
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* |
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* 3b) Read case: We switch over to receive interrupt (RIE). One dummy read is |
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* needed to start clocking, then we keep receiving until we are done. Note |
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* that we use the RDRFS mode all the time, i.e. we ACK/NACK every byte by |
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* writing to the ACKBT bit. I tried using the RDRFS mode only at the end of a |
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* message to create the final NACK as sketched in the datasheet. This caused |
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* some subtle races (when byte n was processed and byte n+1 was already |
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* waiting), though, and I started with the safe approach. |
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* |
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* 4) If we got a NACK somewhere, we flag the error and stop the transmission |
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* via NAKIE. |
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* |
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* Also check the comments in the interrupt routines for some gory details. |
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*/ |
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#include <linux/clk.h> |
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#include <linux/completion.h> |
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#include <linux/err.h> |
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#include <linux/i2c.h> |
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#include <linux/interrupt.h> |
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#include <linux/io.h> |
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#include <linux/module.h> |
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#include <linux/of.h> |
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#include <linux/of_device.h> |
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#include <linux/platform_device.h> |
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#include <linux/pm_runtime.h> |
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#include <linux/reset.h> |
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#define RIIC_ICCR1 0x00 |
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#define RIIC_ICCR2 0x04 |
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#define RIIC_ICMR1 0x08 |
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#define RIIC_ICMR3 0x10 |
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#define RIIC_ICSER 0x18 |
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#define RIIC_ICIER 0x1c |
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#define RIIC_ICSR2 0x24 |
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#define RIIC_ICBRL 0x34 |
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#define RIIC_ICBRH 0x38 |
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#define RIIC_ICDRT 0x3c |
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#define RIIC_ICDRR 0x40 |
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#define ICCR1_ICE 0x80 |
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#define ICCR1_IICRST 0x40 |
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#define ICCR1_SOWP 0x10 |
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#define ICCR2_BBSY 0x80 |
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#define ICCR2_SP 0x08 |
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#define ICCR2_RS 0x04 |
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#define ICCR2_ST 0x02 |
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#define ICMR1_CKS_MASK 0x70 |
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#define ICMR1_BCWP 0x08 |
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#define ICMR1_CKS(_x) ((((_x) << 4) & ICMR1_CKS_MASK) | ICMR1_BCWP) |
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#define ICMR3_RDRFS 0x20 |
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#define ICMR3_ACKWP 0x10 |
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#define ICMR3_ACKBT 0x08 |
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#define ICIER_TIE 0x80 |
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#define ICIER_TEIE 0x40 |
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#define ICIER_RIE 0x20 |
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#define ICIER_NAKIE 0x10 |
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#define ICIER_SPIE 0x08 |
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#define ICSR2_NACKF 0x10 |
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#define ICBR_RESERVED 0xe0 /* Should be 1 on writes */ |
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#define RIIC_INIT_MSG -1 |
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enum riic_type { |
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RIIC_RZ_A, |
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RIIC_RZ_G2L, |
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}; |
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struct riic_dev { |
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void __iomem *base; |
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u8 *buf; |
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struct i2c_msg *msg; |
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int bytes_left; |
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int err; |
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int is_last; |
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struct completion msg_done; |
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struct i2c_adapter adapter; |
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struct clk *clk; |
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}; |
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struct riic_irq_desc { |
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int res_num; |
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irq_handler_t isr; |
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char *name; |
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}; |
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static inline void riic_clear_set_bit(struct riic_dev *riic, u8 clear, u8 set, u8 reg) |
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{ |
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writeb((readb(riic->base + reg) & ~clear) | set, riic->base + reg); |
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} |
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static int riic_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num) |
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{ |
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struct riic_dev *riic = i2c_get_adapdata(adap); |
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unsigned long time_left; |
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int i; |
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u8 start_bit; |
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pm_runtime_get_sync(adap->dev.parent); |
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if (readb(riic->base + RIIC_ICCR2) & ICCR2_BBSY) { |
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riic->err = -EBUSY; |
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goto out; |
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} |
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reinit_completion(&riic->msg_done); |
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riic->err = 0; |
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writeb(0, riic->base + RIIC_ICSR2); |
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for (i = 0, start_bit = ICCR2_ST; i < num; i++) { |
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riic->bytes_left = RIIC_INIT_MSG; |
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riic->buf = msgs[i].buf; |
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riic->msg = &msgs[i]; |
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riic->is_last = (i == num - 1); |
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writeb(ICIER_NAKIE | ICIER_TIE, riic->base + RIIC_ICIER); |
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writeb(start_bit, riic->base + RIIC_ICCR2); |
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time_left = wait_for_completion_timeout(&riic->msg_done, riic->adapter.timeout); |
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if (time_left == 0) |
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riic->err = -ETIMEDOUT; |
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if (riic->err) |
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break; |
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start_bit = ICCR2_RS; |
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} |
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out: |
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pm_runtime_put(adap->dev.parent); |
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return riic->err ?: num; |
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} |
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static irqreturn_t riic_tdre_isr(int irq, void *data) |
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{ |
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struct riic_dev *riic = data; |
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u8 val; |
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if (!riic->bytes_left) |
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return IRQ_NONE; |
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if (riic->bytes_left == RIIC_INIT_MSG) { |
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if (riic->msg->flags & I2C_M_RD) |
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/* On read, switch over to receive interrupt */ |
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riic_clear_set_bit(riic, ICIER_TIE, ICIER_RIE, RIIC_ICIER); |
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else |
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/* On write, initialize length */ |
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riic->bytes_left = riic->msg->len; |
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val = i2c_8bit_addr_from_msg(riic->msg); |
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} else { |
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val = *riic->buf; |
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riic->buf++; |
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riic->bytes_left--; |
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} |
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/* |
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* Switch to transmission ended interrupt when done. Do check here |
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* after bytes_left was initialized to support SMBUS_QUICK (new msg has |
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* 0 length then) |
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*/ |
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if (riic->bytes_left == 0) |
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riic_clear_set_bit(riic, ICIER_TIE, ICIER_TEIE, RIIC_ICIER); |
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/* |
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* This acks the TIE interrupt. We get another TIE immediately if our |
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* value could be moved to the shadow shift register right away. So |
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* this must be after updates to ICIER (where we want to disable TIE)! |
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*/ |
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writeb(val, riic->base + RIIC_ICDRT); |
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return IRQ_HANDLED; |
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} |
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static irqreturn_t riic_tend_isr(int irq, void *data) |
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{ |
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struct riic_dev *riic = data; |
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if (readb(riic->base + RIIC_ICSR2) & ICSR2_NACKF) { |
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/* We got a NACKIE */ |
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readb(riic->base + RIIC_ICDRR); /* dummy read */ |
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riic_clear_set_bit(riic, ICSR2_NACKF, 0, RIIC_ICSR2); |
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riic->err = -ENXIO; |
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} else if (riic->bytes_left) { |
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return IRQ_NONE; |
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} |
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if (riic->is_last || riic->err) { |
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riic_clear_set_bit(riic, ICIER_TEIE, ICIER_SPIE, RIIC_ICIER); |
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writeb(ICCR2_SP, riic->base + RIIC_ICCR2); |
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} else { |
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/* Transfer is complete, but do not send STOP */ |
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riic_clear_set_bit(riic, ICIER_TEIE, 0, RIIC_ICIER); |
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complete(&riic->msg_done); |
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} |
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return IRQ_HANDLED; |
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} |
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static irqreturn_t riic_rdrf_isr(int irq, void *data) |
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{ |
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struct riic_dev *riic = data; |
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if (!riic->bytes_left) |
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return IRQ_NONE; |
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if (riic->bytes_left == RIIC_INIT_MSG) { |
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riic->bytes_left = riic->msg->len; |
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readb(riic->base + RIIC_ICDRR); /* dummy read */ |
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return IRQ_HANDLED; |
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} |
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if (riic->bytes_left == 1) { |
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/* STOP must come before we set ACKBT! */ |
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if (riic->is_last) { |
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riic_clear_set_bit(riic, 0, ICIER_SPIE, RIIC_ICIER); |
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writeb(ICCR2_SP, riic->base + RIIC_ICCR2); |
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} |
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riic_clear_set_bit(riic, 0, ICMR3_ACKBT, RIIC_ICMR3); |
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} else { |
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riic_clear_set_bit(riic, ICMR3_ACKBT, 0, RIIC_ICMR3); |
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} |
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/* Reading acks the RIE interrupt */ |
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*riic->buf = readb(riic->base + RIIC_ICDRR); |
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riic->buf++; |
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riic->bytes_left--; |
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return IRQ_HANDLED; |
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} |
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static irqreturn_t riic_stop_isr(int irq, void *data) |
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{ |
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struct riic_dev *riic = data; |
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/* read back registers to confirm writes have fully propagated */ |
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writeb(0, riic->base + RIIC_ICSR2); |
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readb(riic->base + RIIC_ICSR2); |
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writeb(0, riic->base + RIIC_ICIER); |
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readb(riic->base + RIIC_ICIER); |
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complete(&riic->msg_done); |
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return IRQ_HANDLED; |
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} |
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static u32 riic_func(struct i2c_adapter *adap) |
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{ |
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return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; |
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} |
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static const struct i2c_algorithm riic_algo = { |
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.master_xfer = riic_xfer, |
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.functionality = riic_func, |
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}; |
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static int riic_init_hw(struct riic_dev *riic, struct i2c_timings *t) |
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{ |
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int ret = 0; |
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unsigned long rate; |
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int total_ticks, cks, brl, brh; |
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pm_runtime_get_sync(riic->adapter.dev.parent); |
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if (t->bus_freq_hz > I2C_MAX_FAST_MODE_FREQ) { |
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dev_err(&riic->adapter.dev, |
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"unsupported bus speed (%dHz). %d max\n", |
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t->bus_freq_hz, I2C_MAX_FAST_MODE_FREQ); |
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ret = -EINVAL; |
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goto out; |
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} |
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rate = clk_get_rate(riic->clk); |
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/* |
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* Assume the default register settings: |
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* FER.SCLE = 1 (SCL sync circuit enabled, adds 2 or 3 cycles) |
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* FER.NFE = 1 (noise circuit enabled) |
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* MR3.NF = 0 (1 cycle of noise filtered out) |
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* |
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* Freq (CKS=000) = (I2CCLK + tr + tf)/ (BRH + 3 + 1) + (BRL + 3 + 1) |
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* Freq (CKS!=000) = (I2CCLK + tr + tf)/ (BRH + 2 + 1) + (BRL + 2 + 1) |
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*/ |
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/* |
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* Determine reference clock rate. We must be able to get the desired |
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* frequency with only 62 clock ticks max (31 high, 31 low). |
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* Aim for a duty of 60% LOW, 40% HIGH. |
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*/ |
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total_ticks = DIV_ROUND_UP(rate, t->bus_freq_hz); |
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for (cks = 0; cks < 7; cks++) { |
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/* |
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* 60% low time must be less than BRL + 2 + 1 |
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* BRL max register value is 0x1F. |
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*/ |
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brl = ((total_ticks * 6) / 10); |
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if (brl <= (0x1F + 3)) |
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break; |
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total_ticks /= 2; |
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rate /= 2; |
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} |
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if (brl > (0x1F + 3)) { |
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dev_err(&riic->adapter.dev, "invalid speed (%lu). Too slow.\n", |
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(unsigned long)t->bus_freq_hz); |
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ret = -EINVAL; |
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goto out; |
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} |
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brh = total_ticks - brl; |
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/* Remove automatic clock ticks for sync circuit and NF */ |
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if (cks == 0) { |
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brl -= 4; |
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brh -= 4; |
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} else { |
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brl -= 3; |
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brh -= 3; |
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} |
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/* |
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* Remove clock ticks for rise and fall times. Convert ns to clock |
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* ticks. |
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*/ |
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brl -= t->scl_fall_ns / (1000000000 / rate); |
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brh -= t->scl_rise_ns / (1000000000 / rate); |
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/* Adjust for min register values for when SCLE=1 and NFE=1 */ |
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if (brl < 1) |
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brl = 1; |
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if (brh < 1) |
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brh = 1; |
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pr_debug("i2c-riic: freq=%lu, duty=%d, fall=%lu, rise=%lu, cks=%d, brl=%d, brh=%d\n", |
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rate / total_ticks, ((brl + 3) * 100) / (brl + brh + 6), |
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t->scl_fall_ns / (1000000000 / rate), |
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t->scl_rise_ns / (1000000000 / rate), cks, brl, brh); |
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/* Changing the order of accessing IICRST and ICE may break things! */ |
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writeb(ICCR1_IICRST | ICCR1_SOWP, riic->base + RIIC_ICCR1); |
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riic_clear_set_bit(riic, 0, ICCR1_ICE, RIIC_ICCR1); |
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writeb(ICMR1_CKS(cks), riic->base + RIIC_ICMR1); |
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writeb(brh | ICBR_RESERVED, riic->base + RIIC_ICBRH); |
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writeb(brl | ICBR_RESERVED, riic->base + RIIC_ICBRL); |
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writeb(0, riic->base + RIIC_ICSER); |
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writeb(ICMR3_ACKWP | ICMR3_RDRFS, riic->base + RIIC_ICMR3); |
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riic_clear_set_bit(riic, ICCR1_IICRST, 0, RIIC_ICCR1); |
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out: |
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pm_runtime_put(riic->adapter.dev.parent); |
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return ret; |
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} |
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static struct riic_irq_desc riic_irqs[] = { |
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{ .res_num = 0, .isr = riic_tend_isr, .name = "riic-tend" }, |
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{ .res_num = 1, .isr = riic_rdrf_isr, .name = "riic-rdrf" }, |
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{ .res_num = 2, .isr = riic_tdre_isr, .name = "riic-tdre" }, |
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{ .res_num = 3, .isr = riic_stop_isr, .name = "riic-stop" }, |
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{ .res_num = 5, .isr = riic_tend_isr, .name = "riic-nack" }, |
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}; |
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static int riic_i2c_probe(struct platform_device *pdev) |
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{ |
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struct riic_dev *riic; |
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struct i2c_adapter *adap; |
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struct resource *res; |
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struct i2c_timings i2c_t; |
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struct reset_control *rstc; |
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int i, ret; |
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enum riic_type type; |
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riic = devm_kzalloc(&pdev->dev, sizeof(*riic), GFP_KERNEL); |
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if (!riic) |
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return -ENOMEM; |
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
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riic->base = devm_ioremap_resource(&pdev->dev, res); |
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if (IS_ERR(riic->base)) |
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return PTR_ERR(riic->base); |
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riic->clk = devm_clk_get(&pdev->dev, NULL); |
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if (IS_ERR(riic->clk)) { |
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dev_err(&pdev->dev, "missing controller clock"); |
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return PTR_ERR(riic->clk); |
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} |
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type = (enum riic_type)of_device_get_match_data(&pdev->dev); |
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if (type == RIIC_RZ_G2L) { |
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rstc = devm_reset_control_get_exclusive(&pdev->dev, NULL); |
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if (IS_ERR(rstc)) { |
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dev_err(&pdev->dev, "Error: missing reset ctrl\n"); |
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return PTR_ERR(rstc); |
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} |
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reset_control_deassert(rstc); |
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} |
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for (i = 0; i < ARRAY_SIZE(riic_irqs); i++) { |
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res = platform_get_resource(pdev, IORESOURCE_IRQ, riic_irqs[i].res_num); |
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if (!res) |
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return -ENODEV; |
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ret = devm_request_irq(&pdev->dev, res->start, riic_irqs[i].isr, |
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0, riic_irqs[i].name, riic); |
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if (ret) { |
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dev_err(&pdev->dev, "failed to request irq %s\n", riic_irqs[i].name); |
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return ret; |
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} |
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} |
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adap = &riic->adapter; |
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i2c_set_adapdata(adap, riic); |
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strlcpy(adap->name, "Renesas RIIC adapter", sizeof(adap->name)); |
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adap->owner = THIS_MODULE; |
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adap->algo = &riic_algo; |
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adap->dev.parent = &pdev->dev; |
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adap->dev.of_node = pdev->dev.of_node; |
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init_completion(&riic->msg_done); |
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i2c_parse_fw_timings(&pdev->dev, &i2c_t, true); |
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pm_runtime_enable(&pdev->dev); |
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ret = riic_init_hw(riic, &i2c_t); |
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if (ret) |
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goto out; |
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ret = i2c_add_adapter(adap); |
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if (ret) |
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goto out; |
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platform_set_drvdata(pdev, riic); |
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dev_info(&pdev->dev, "registered with %dHz bus speed\n", |
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i2c_t.bus_freq_hz); |
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return 0; |
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out: |
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pm_runtime_disable(&pdev->dev); |
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return ret; |
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} |
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static int riic_i2c_remove(struct platform_device *pdev) |
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{ |
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struct riic_dev *riic = platform_get_drvdata(pdev); |
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pm_runtime_get_sync(&pdev->dev); |
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writeb(0, riic->base + RIIC_ICIER); |
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pm_runtime_put(&pdev->dev); |
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i2c_del_adapter(&riic->adapter); |
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pm_runtime_disable(&pdev->dev); |
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return 0; |
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} |
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static const struct of_device_id riic_i2c_dt_ids[] = { |
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{ .compatible = "renesas,riic-r9a07g044", .data = (void *)RIIC_RZ_G2L }, |
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{ .compatible = "renesas,riic-rz", .data = (void *)RIIC_RZ_A }, |
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{ /* Sentinel */ }, |
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}; |
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static struct platform_driver riic_i2c_driver = { |
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.probe = riic_i2c_probe, |
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.remove = riic_i2c_remove, |
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.driver = { |
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.name = "i2c-riic", |
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.of_match_table = riic_i2c_dt_ids, |
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}, |
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}; |
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module_platform_driver(riic_i2c_driver); |
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MODULE_DESCRIPTION("Renesas RIIC adapter"); |
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MODULE_AUTHOR("Wolfram Sang <[email protected]>"); |
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MODULE_LICENSE("GPL v2"); |
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MODULE_DEVICE_TABLE(of, riic_i2c_dt_ids);
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