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792 lines
21 KiB
792 lines
21 KiB
/* |
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* Provides I2C support for Philips PNX010x/PNX4008 boards. |
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* |
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* Authors: Dennis Kovalev <[email protected]> |
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* Vitaly Wool <[email protected]> |
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* |
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* 2004-2006 (c) MontaVista Software, Inc. This file is licensed under |
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* the terms of the GNU General Public License version 2. This program |
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* is licensed "as is" without any warranty of any kind, whether express |
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* or implied. |
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*/ |
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#include <linux/module.h> |
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#include <linux/interrupt.h> |
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#include <linux/ioport.h> |
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#include <linux/delay.h> |
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#include <linux/i2c.h> |
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#include <linux/timer.h> |
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#include <linux/completion.h> |
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#include <linux/platform_device.h> |
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#include <linux/io.h> |
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#include <linux/err.h> |
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#include <linux/clk.h> |
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#include <linux/slab.h> |
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#include <linux/of.h> |
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#define I2C_PNX_TIMEOUT_DEFAULT 10 /* msec */ |
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#define I2C_PNX_SPEED_KHZ_DEFAULT 100 |
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#define I2C_PNX_REGION_SIZE 0x100 |
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struct i2c_pnx_mif { |
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int ret; /* Return value */ |
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int mode; /* Interface mode */ |
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struct completion complete; /* I/O completion */ |
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struct timer_list timer; /* Timeout */ |
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u8 * buf; /* Data buffer */ |
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int len; /* Length of data buffer */ |
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int order; /* RX Bytes to order via TX */ |
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}; |
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struct i2c_pnx_algo_data { |
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void __iomem *ioaddr; |
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struct i2c_pnx_mif mif; |
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int last; |
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struct clk *clk; |
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struct i2c_adapter adapter; |
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int irq; |
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u32 timeout; |
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}; |
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enum { |
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mstatus_tdi = 0x00000001, |
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mstatus_afi = 0x00000002, |
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mstatus_nai = 0x00000004, |
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mstatus_drmi = 0x00000008, |
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mstatus_active = 0x00000020, |
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mstatus_scl = 0x00000040, |
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mstatus_sda = 0x00000080, |
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mstatus_rff = 0x00000100, |
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mstatus_rfe = 0x00000200, |
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mstatus_tff = 0x00000400, |
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mstatus_tfe = 0x00000800, |
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}; |
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enum { |
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mcntrl_tdie = 0x00000001, |
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mcntrl_afie = 0x00000002, |
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mcntrl_naie = 0x00000004, |
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mcntrl_drmie = 0x00000008, |
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mcntrl_drsie = 0x00000010, |
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mcntrl_rffie = 0x00000020, |
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mcntrl_daie = 0x00000040, |
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mcntrl_tffie = 0x00000080, |
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mcntrl_reset = 0x00000100, |
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mcntrl_cdbmode = 0x00000400, |
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}; |
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enum { |
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rw_bit = 1 << 0, |
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start_bit = 1 << 8, |
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stop_bit = 1 << 9, |
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}; |
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#define I2C_REG_RX(a) ((a)->ioaddr) /* Rx FIFO reg (RO) */ |
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#define I2C_REG_TX(a) ((a)->ioaddr) /* Tx FIFO reg (WO) */ |
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#define I2C_REG_STS(a) ((a)->ioaddr + 0x04) /* Status reg (RO) */ |
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#define I2C_REG_CTL(a) ((a)->ioaddr + 0x08) /* Ctl reg */ |
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#define I2C_REG_CKL(a) ((a)->ioaddr + 0x0c) /* Clock divider low */ |
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#define I2C_REG_CKH(a) ((a)->ioaddr + 0x10) /* Clock divider high */ |
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#define I2C_REG_ADR(a) ((a)->ioaddr + 0x14) /* I2C address */ |
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#define I2C_REG_RFL(a) ((a)->ioaddr + 0x18) /* Rx FIFO level (RO) */ |
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#define I2C_REG_TFL(a) ((a)->ioaddr + 0x1c) /* Tx FIFO level (RO) */ |
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#define I2C_REG_RXB(a) ((a)->ioaddr + 0x20) /* Num of bytes Rx-ed (RO) */ |
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#define I2C_REG_TXB(a) ((a)->ioaddr + 0x24) /* Num of bytes Tx-ed (RO) */ |
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#define I2C_REG_TXS(a) ((a)->ioaddr + 0x28) /* Tx slave FIFO (RO) */ |
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#define I2C_REG_STFL(a) ((a)->ioaddr + 0x2c) /* Tx slave FIFO level (RO) */ |
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static inline int wait_timeout(struct i2c_pnx_algo_data *data) |
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{ |
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long timeout = data->timeout; |
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while (timeout > 0 && |
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(ioread32(I2C_REG_STS(data)) & mstatus_active)) { |
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mdelay(1); |
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timeout--; |
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} |
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return (timeout <= 0); |
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} |
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static inline int wait_reset(struct i2c_pnx_algo_data *data) |
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{ |
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long timeout = data->timeout; |
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while (timeout > 0 && |
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(ioread32(I2C_REG_CTL(data)) & mcntrl_reset)) { |
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mdelay(1); |
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timeout--; |
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} |
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return (timeout <= 0); |
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} |
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static inline void i2c_pnx_arm_timer(struct i2c_pnx_algo_data *alg_data) |
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{ |
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struct timer_list *timer = &alg_data->mif.timer; |
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unsigned long expires = msecs_to_jiffies(alg_data->timeout); |
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if (expires <= 1) |
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expires = 2; |
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del_timer_sync(timer); |
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dev_dbg(&alg_data->adapter.dev, "Timer armed at %lu plus %lu jiffies.\n", |
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jiffies, expires); |
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timer->expires = jiffies + expires; |
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add_timer(timer); |
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} |
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/** |
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* i2c_pnx_start - start a device |
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* @slave_addr: slave address |
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* @alg_data: pointer to local driver data structure |
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* |
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* Generate a START signal in the desired mode. |
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*/ |
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static int i2c_pnx_start(unsigned char slave_addr, |
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struct i2c_pnx_algo_data *alg_data) |
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{ |
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dev_dbg(&alg_data->adapter.dev, "%s(): addr 0x%x mode %d\n", __func__, |
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slave_addr, alg_data->mif.mode); |
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|
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/* Check for 7 bit slave addresses only */ |
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if (slave_addr & ~0x7f) { |
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dev_err(&alg_data->adapter.dev, |
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"%s: Invalid slave address %x. Only 7-bit addresses are supported\n", |
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alg_data->adapter.name, slave_addr); |
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return -EINVAL; |
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} |
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/* First, make sure bus is idle */ |
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if (wait_timeout(alg_data)) { |
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/* Somebody else is monopolizing the bus */ |
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dev_err(&alg_data->adapter.dev, |
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"%s: Bus busy. Slave addr = %02x, cntrl = %x, stat = %x\n", |
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alg_data->adapter.name, slave_addr, |
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ioread32(I2C_REG_CTL(alg_data)), |
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ioread32(I2C_REG_STS(alg_data))); |
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return -EBUSY; |
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} else if (ioread32(I2C_REG_STS(alg_data)) & mstatus_afi) { |
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/* Sorry, we lost the bus */ |
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dev_err(&alg_data->adapter.dev, |
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"%s: Arbitration failure. Slave addr = %02x\n", |
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alg_data->adapter.name, slave_addr); |
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return -EIO; |
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} |
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/* |
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* OK, I2C is enabled and we have the bus. |
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* Clear the current TDI and AFI status flags. |
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*/ |
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iowrite32(ioread32(I2C_REG_STS(alg_data)) | mstatus_tdi | mstatus_afi, |
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I2C_REG_STS(alg_data)); |
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dev_dbg(&alg_data->adapter.dev, "%s(): sending %#x\n", __func__, |
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(slave_addr << 1) | start_bit | alg_data->mif.mode); |
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/* Write the slave address, START bit and R/W bit */ |
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iowrite32((slave_addr << 1) | start_bit | alg_data->mif.mode, |
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I2C_REG_TX(alg_data)); |
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dev_dbg(&alg_data->adapter.dev, "%s(): exit\n", __func__); |
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return 0; |
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} |
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/** |
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* i2c_pnx_stop - stop a device |
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* @alg_data: pointer to local driver data structure |
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* |
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* Generate a STOP signal to terminate the master transaction. |
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*/ |
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static void i2c_pnx_stop(struct i2c_pnx_algo_data *alg_data) |
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{ |
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/* Only 1 msec max timeout due to interrupt context */ |
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long timeout = 1000; |
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dev_dbg(&alg_data->adapter.dev, "%s(): entering: stat = %04x.\n", |
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__func__, ioread32(I2C_REG_STS(alg_data))); |
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/* Write a STOP bit to TX FIFO */ |
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iowrite32(0xff | stop_bit, I2C_REG_TX(alg_data)); |
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/* Wait until the STOP is seen. */ |
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while (timeout > 0 && |
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(ioread32(I2C_REG_STS(alg_data)) & mstatus_active)) { |
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/* may be called from interrupt context */ |
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udelay(1); |
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timeout--; |
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} |
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dev_dbg(&alg_data->adapter.dev, "%s(): exiting: stat = %04x.\n", |
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__func__, ioread32(I2C_REG_STS(alg_data))); |
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} |
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/** |
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* i2c_pnx_master_xmit - transmit data to slave |
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* @alg_data: pointer to local driver data structure |
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* |
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* Sends one byte of data to the slave |
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*/ |
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static int i2c_pnx_master_xmit(struct i2c_pnx_algo_data *alg_data) |
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{ |
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u32 val; |
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dev_dbg(&alg_data->adapter.dev, "%s(): entering: stat = %04x.\n", |
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__func__, ioread32(I2C_REG_STS(alg_data))); |
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if (alg_data->mif.len > 0) { |
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/* We still have something to talk about... */ |
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val = *alg_data->mif.buf++; |
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if (alg_data->mif.len == 1) |
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val |= stop_bit; |
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alg_data->mif.len--; |
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iowrite32(val, I2C_REG_TX(alg_data)); |
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dev_dbg(&alg_data->adapter.dev, "%s(): xmit %#x [%d]\n", |
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__func__, val, alg_data->mif.len + 1); |
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if (alg_data->mif.len == 0) { |
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if (alg_data->last) { |
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/* Wait until the STOP is seen. */ |
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if (wait_timeout(alg_data)) |
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dev_err(&alg_data->adapter.dev, |
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"The bus is still active after timeout\n"); |
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} |
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/* Disable master interrupts */ |
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iowrite32(ioread32(I2C_REG_CTL(alg_data)) & |
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~(mcntrl_afie | mcntrl_naie | mcntrl_drmie), |
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I2C_REG_CTL(alg_data)); |
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del_timer_sync(&alg_data->mif.timer); |
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dev_dbg(&alg_data->adapter.dev, |
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"%s(): Waking up xfer routine.\n", |
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__func__); |
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complete(&alg_data->mif.complete); |
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} |
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} else if (alg_data->mif.len == 0) { |
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/* zero-sized transfer */ |
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i2c_pnx_stop(alg_data); |
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/* Disable master interrupts. */ |
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iowrite32(ioread32(I2C_REG_CTL(alg_data)) & |
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~(mcntrl_afie | mcntrl_naie | mcntrl_drmie), |
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I2C_REG_CTL(alg_data)); |
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/* Stop timer. */ |
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del_timer_sync(&alg_data->mif.timer); |
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dev_dbg(&alg_data->adapter.dev, |
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"%s(): Waking up xfer routine after zero-xfer.\n", |
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__func__); |
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complete(&alg_data->mif.complete); |
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} |
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dev_dbg(&alg_data->adapter.dev, "%s(): exiting: stat = %04x.\n", |
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__func__, ioread32(I2C_REG_STS(alg_data))); |
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return 0; |
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} |
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/** |
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* i2c_pnx_master_rcv - receive data from slave |
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* @alg_data: pointer to local driver data structure |
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* |
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* Reads one byte data from the slave |
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*/ |
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static int i2c_pnx_master_rcv(struct i2c_pnx_algo_data *alg_data) |
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{ |
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unsigned int val = 0; |
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u32 ctl = 0; |
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dev_dbg(&alg_data->adapter.dev, "%s(): entering: stat = %04x.\n", |
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__func__, ioread32(I2C_REG_STS(alg_data))); |
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/* Check, whether there is already data, |
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* or we didn't 'ask' for it yet. |
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*/ |
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if (ioread32(I2C_REG_STS(alg_data)) & mstatus_rfe) { |
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/* 'Asking' is done asynchronously, e.g. dummy TX of several |
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* bytes is done before the first actual RX arrives in FIFO. |
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* Therefore, ordered bytes (via TX) are counted separately. |
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*/ |
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if (alg_data->mif.order) { |
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dev_dbg(&alg_data->adapter.dev, |
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"%s(): Write dummy data to fill Rx-fifo...\n", |
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__func__); |
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if (alg_data->mif.order == 1) { |
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/* Last byte, do not acknowledge next rcv. */ |
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val |= stop_bit; |
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/* |
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* Enable interrupt RFDAIE (data in Rx fifo), |
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* and disable DRMIE (need data for Tx) |
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*/ |
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ctl = ioread32(I2C_REG_CTL(alg_data)); |
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ctl |= mcntrl_rffie | mcntrl_daie; |
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ctl &= ~mcntrl_drmie; |
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iowrite32(ctl, I2C_REG_CTL(alg_data)); |
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} |
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/* |
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* Now we'll 'ask' for data: |
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* For each byte we want to receive, we must |
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* write a (dummy) byte to the Tx-FIFO. |
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*/ |
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iowrite32(val, I2C_REG_TX(alg_data)); |
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alg_data->mif.order--; |
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} |
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return 0; |
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} |
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/* Handle data. */ |
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if (alg_data->mif.len > 0) { |
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val = ioread32(I2C_REG_RX(alg_data)); |
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*alg_data->mif.buf++ = (u8) (val & 0xff); |
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dev_dbg(&alg_data->adapter.dev, "%s(): rcv 0x%x [%d]\n", |
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__func__, val, alg_data->mif.len); |
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alg_data->mif.len--; |
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if (alg_data->mif.len == 0) { |
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if (alg_data->last) |
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/* Wait until the STOP is seen. */ |
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if (wait_timeout(alg_data)) |
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dev_err(&alg_data->adapter.dev, |
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"The bus is still active after timeout\n"); |
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/* Disable master interrupts */ |
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ctl = ioread32(I2C_REG_CTL(alg_data)); |
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ctl &= ~(mcntrl_afie | mcntrl_naie | mcntrl_rffie | |
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mcntrl_drmie | mcntrl_daie); |
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iowrite32(ctl, I2C_REG_CTL(alg_data)); |
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/* Kill timer. */ |
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del_timer_sync(&alg_data->mif.timer); |
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complete(&alg_data->mif.complete); |
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} |
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} |
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dev_dbg(&alg_data->adapter.dev, "%s(): exiting: stat = %04x.\n", |
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__func__, ioread32(I2C_REG_STS(alg_data))); |
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return 0; |
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} |
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static irqreturn_t i2c_pnx_interrupt(int irq, void *dev_id) |
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{ |
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struct i2c_pnx_algo_data *alg_data = dev_id; |
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u32 stat, ctl; |
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dev_dbg(&alg_data->adapter.dev, |
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"%s(): mstat = %x mctrl = %x, mode = %d\n", |
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__func__, |
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ioread32(I2C_REG_STS(alg_data)), |
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ioread32(I2C_REG_CTL(alg_data)), |
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alg_data->mif.mode); |
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stat = ioread32(I2C_REG_STS(alg_data)); |
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/* let's see what kind of event this is */ |
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if (stat & mstatus_afi) { |
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/* We lost arbitration in the midst of a transfer */ |
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alg_data->mif.ret = -EIO; |
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/* Disable master interrupts. */ |
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ctl = ioread32(I2C_REG_CTL(alg_data)); |
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ctl &= ~(mcntrl_afie | mcntrl_naie | mcntrl_rffie | |
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mcntrl_drmie); |
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iowrite32(ctl, I2C_REG_CTL(alg_data)); |
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/* Stop timer, to prevent timeout. */ |
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del_timer_sync(&alg_data->mif.timer); |
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complete(&alg_data->mif.complete); |
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} else if (stat & mstatus_nai) { |
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/* Slave did not acknowledge, generate a STOP */ |
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dev_dbg(&alg_data->adapter.dev, |
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"%s(): Slave did not acknowledge, generating a STOP.\n", |
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__func__); |
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i2c_pnx_stop(alg_data); |
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/* Disable master interrupts. */ |
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ctl = ioread32(I2C_REG_CTL(alg_data)); |
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ctl &= ~(mcntrl_afie | mcntrl_naie | mcntrl_rffie | |
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mcntrl_drmie); |
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iowrite32(ctl, I2C_REG_CTL(alg_data)); |
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|
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/* Our return value. */ |
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alg_data->mif.ret = -EIO; |
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/* Stop timer, to prevent timeout. */ |
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del_timer_sync(&alg_data->mif.timer); |
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complete(&alg_data->mif.complete); |
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} else { |
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/* |
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* Two options: |
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* - Master Tx needs data. |
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* - There is data in the Rx-fifo |
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* The latter is only the case if we have requested for data, |
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* via a dummy write. (See 'i2c_pnx_master_rcv'.) |
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* We therefore check, as a sanity check, whether that interrupt |
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* has been enabled. |
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*/ |
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if ((stat & mstatus_drmi) || !(stat & mstatus_rfe)) { |
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if (alg_data->mif.mode == I2C_SMBUS_WRITE) { |
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i2c_pnx_master_xmit(alg_data); |
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} else if (alg_data->mif.mode == I2C_SMBUS_READ) { |
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i2c_pnx_master_rcv(alg_data); |
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} |
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} |
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} |
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/* Clear TDI and AFI bits */ |
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stat = ioread32(I2C_REG_STS(alg_data)); |
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iowrite32(stat | mstatus_tdi | mstatus_afi, I2C_REG_STS(alg_data)); |
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dev_dbg(&alg_data->adapter.dev, |
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"%s(): exiting, stat = %x ctrl = %x.\n", |
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__func__, ioread32(I2C_REG_STS(alg_data)), |
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ioread32(I2C_REG_CTL(alg_data))); |
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return IRQ_HANDLED; |
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} |
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static void i2c_pnx_timeout(struct timer_list *t) |
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{ |
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struct i2c_pnx_algo_data *alg_data = from_timer(alg_data, t, mif.timer); |
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u32 ctl; |
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dev_err(&alg_data->adapter.dev, |
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"Master timed out. stat = %04x, cntrl = %04x. Resetting master...\n", |
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ioread32(I2C_REG_STS(alg_data)), |
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ioread32(I2C_REG_CTL(alg_data))); |
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|
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/* Reset master and disable interrupts */ |
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ctl = ioread32(I2C_REG_CTL(alg_data)); |
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ctl &= ~(mcntrl_afie | mcntrl_naie | mcntrl_rffie | mcntrl_drmie); |
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iowrite32(ctl, I2C_REG_CTL(alg_data)); |
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ctl |= mcntrl_reset; |
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iowrite32(ctl, I2C_REG_CTL(alg_data)); |
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wait_reset(alg_data); |
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alg_data->mif.ret = -EIO; |
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complete(&alg_data->mif.complete); |
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} |
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static inline void bus_reset_if_active(struct i2c_pnx_algo_data *alg_data) |
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{ |
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u32 stat; |
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|
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if ((stat = ioread32(I2C_REG_STS(alg_data))) & mstatus_active) { |
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dev_err(&alg_data->adapter.dev, |
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"%s: Bus is still active after xfer. Reset it...\n", |
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alg_data->adapter.name); |
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iowrite32(ioread32(I2C_REG_CTL(alg_data)) | mcntrl_reset, |
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I2C_REG_CTL(alg_data)); |
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wait_reset(alg_data); |
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} else if (!(stat & mstatus_rfe) || !(stat & mstatus_tfe)) { |
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/* If there is data in the fifo's after transfer, |
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* flush fifo's by reset. |
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*/ |
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iowrite32(ioread32(I2C_REG_CTL(alg_data)) | mcntrl_reset, |
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I2C_REG_CTL(alg_data)); |
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wait_reset(alg_data); |
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} else if (stat & mstatus_nai) { |
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iowrite32(ioread32(I2C_REG_CTL(alg_data)) | mcntrl_reset, |
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I2C_REG_CTL(alg_data)); |
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wait_reset(alg_data); |
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} |
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} |
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/** |
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* i2c_pnx_xfer - generic transfer entry point |
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* @adap: pointer to I2C adapter structure |
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* @msgs: array of messages |
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* @num: number of messages |
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* |
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* Initiates the transfer |
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*/ |
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static int |
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i2c_pnx_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num) |
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{ |
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struct i2c_msg *pmsg; |
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int rc = 0, completed = 0, i; |
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struct i2c_pnx_algo_data *alg_data = adap->algo_data; |
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u32 stat; |
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dev_dbg(&alg_data->adapter.dev, |
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"%s(): entering: %d messages, stat = %04x.\n", |
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__func__, num, ioread32(I2C_REG_STS(alg_data))); |
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bus_reset_if_active(alg_data); |
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/* Process transactions in a loop. */ |
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for (i = 0; rc >= 0 && i < num; i++) { |
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u8 addr; |
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pmsg = &msgs[i]; |
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addr = pmsg->addr; |
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if (pmsg->flags & I2C_M_TEN) { |
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dev_err(&alg_data->adapter.dev, |
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"%s: 10 bits addr not supported!\n", |
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alg_data->adapter.name); |
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rc = -EINVAL; |
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break; |
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} |
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alg_data->mif.buf = pmsg->buf; |
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alg_data->mif.len = pmsg->len; |
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alg_data->mif.order = pmsg->len; |
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alg_data->mif.mode = (pmsg->flags & I2C_M_RD) ? |
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I2C_SMBUS_READ : I2C_SMBUS_WRITE; |
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alg_data->mif.ret = 0; |
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alg_data->last = (i == num - 1); |
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dev_dbg(&alg_data->adapter.dev, "%s(): mode %d, %d bytes\n", |
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__func__, alg_data->mif.mode, alg_data->mif.len); |
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i2c_pnx_arm_timer(alg_data); |
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/* initialize the completion var */ |
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init_completion(&alg_data->mif.complete); |
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/* Enable master interrupt */ |
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iowrite32(ioread32(I2C_REG_CTL(alg_data)) | mcntrl_afie | |
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mcntrl_naie | mcntrl_drmie, |
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I2C_REG_CTL(alg_data)); |
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/* Put start-code and slave-address on the bus. */ |
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rc = i2c_pnx_start(addr, alg_data); |
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if (rc < 0) |
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break; |
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/* Wait for completion */ |
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wait_for_completion(&alg_data->mif.complete); |
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if (!(rc = alg_data->mif.ret)) |
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completed++; |
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dev_dbg(&alg_data->adapter.dev, |
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"%s(): Complete, return code = %d.\n", |
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__func__, rc); |
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/* Clear TDI and AFI bits in case they are set. */ |
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if ((stat = ioread32(I2C_REG_STS(alg_data))) & mstatus_tdi) { |
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dev_dbg(&alg_data->adapter.dev, |
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"%s: TDI still set... clearing now.\n", |
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alg_data->adapter.name); |
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iowrite32(stat, I2C_REG_STS(alg_data)); |
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} |
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if ((stat = ioread32(I2C_REG_STS(alg_data))) & mstatus_afi) { |
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dev_dbg(&alg_data->adapter.dev, |
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"%s: AFI still set... clearing now.\n", |
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alg_data->adapter.name); |
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iowrite32(stat, I2C_REG_STS(alg_data)); |
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} |
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} |
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bus_reset_if_active(alg_data); |
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/* Cleanup to be sure... */ |
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alg_data->mif.buf = NULL; |
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alg_data->mif.len = 0; |
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alg_data->mif.order = 0; |
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dev_dbg(&alg_data->adapter.dev, "%s(): exiting, stat = %x\n", |
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__func__, ioread32(I2C_REG_STS(alg_data))); |
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if (completed != num) |
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return ((rc < 0) ? rc : -EREMOTEIO); |
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return num; |
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} |
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static u32 i2c_pnx_func(struct i2c_adapter *adapter) |
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{ |
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return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; |
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} |
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static const struct i2c_algorithm pnx_algorithm = { |
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.master_xfer = i2c_pnx_xfer, |
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.functionality = i2c_pnx_func, |
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}; |
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#ifdef CONFIG_PM_SLEEP |
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static int i2c_pnx_controller_suspend(struct device *dev) |
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{ |
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struct i2c_pnx_algo_data *alg_data = dev_get_drvdata(dev); |
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clk_disable_unprepare(alg_data->clk); |
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return 0; |
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} |
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static int i2c_pnx_controller_resume(struct device *dev) |
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{ |
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struct i2c_pnx_algo_data *alg_data = dev_get_drvdata(dev); |
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return clk_prepare_enable(alg_data->clk); |
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} |
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static SIMPLE_DEV_PM_OPS(i2c_pnx_pm, |
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i2c_pnx_controller_suspend, i2c_pnx_controller_resume); |
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#define PNX_I2C_PM (&i2c_pnx_pm) |
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#else |
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#define PNX_I2C_PM NULL |
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#endif |
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static int i2c_pnx_probe(struct platform_device *pdev) |
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{ |
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unsigned long tmp; |
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int ret = 0; |
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struct i2c_pnx_algo_data *alg_data; |
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unsigned long freq; |
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struct resource *res; |
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u32 speed = I2C_PNX_SPEED_KHZ_DEFAULT * 1000; |
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alg_data = devm_kzalloc(&pdev->dev, sizeof(*alg_data), GFP_KERNEL); |
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if (!alg_data) |
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return -ENOMEM; |
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platform_set_drvdata(pdev, alg_data); |
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alg_data->adapter.dev.parent = &pdev->dev; |
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alg_data->adapter.algo = &pnx_algorithm; |
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alg_data->adapter.algo_data = alg_data; |
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alg_data->adapter.nr = pdev->id; |
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alg_data->timeout = I2C_PNX_TIMEOUT_DEFAULT; |
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#ifdef CONFIG_OF |
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alg_data->adapter.dev.of_node = of_node_get(pdev->dev.of_node); |
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if (pdev->dev.of_node) { |
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of_property_read_u32(pdev->dev.of_node, "clock-frequency", |
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&speed); |
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/* |
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* At this point, it is planned to add an OF timeout property. |
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* As soon as there is a consensus about how to call and handle |
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* this, sth. like the following can be put here: |
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* |
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* of_property_read_u32(pdev->dev.of_node, "timeout", |
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* &alg_data->timeout); |
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*/ |
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} |
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#endif |
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alg_data->clk = devm_clk_get(&pdev->dev, NULL); |
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if (IS_ERR(alg_data->clk)) |
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return PTR_ERR(alg_data->clk); |
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timer_setup(&alg_data->mif.timer, i2c_pnx_timeout, 0); |
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snprintf(alg_data->adapter.name, sizeof(alg_data->adapter.name), |
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"%s", pdev->name); |
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/* Register I/O resource */ |
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
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alg_data->ioaddr = devm_ioremap_resource(&pdev->dev, res); |
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if (IS_ERR(alg_data->ioaddr)) |
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return PTR_ERR(alg_data->ioaddr); |
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ret = clk_prepare_enable(alg_data->clk); |
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if (ret) |
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return ret; |
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freq = clk_get_rate(alg_data->clk); |
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/* |
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* Clock Divisor High This value is the number of system clocks |
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* the serial clock (SCL) will be high. |
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* For example, if the system clock period is 50 ns and the maximum |
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* desired serial period is 10000 ns (100 kHz), then CLKHI would be |
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* set to 0.5*(f_sys/f_i2c)-2=0.5*(20e6/100e3)-2=98. The actual value |
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* programmed into CLKHI will vary from this slightly due to |
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* variations in the output pad's rise and fall times as well as |
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* the deglitching filter length. |
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*/ |
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tmp = (freq / speed) / 2 - 2; |
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if (tmp > 0x3FF) |
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tmp = 0x3FF; |
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iowrite32(tmp, I2C_REG_CKH(alg_data)); |
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iowrite32(tmp, I2C_REG_CKL(alg_data)); |
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iowrite32(mcntrl_reset, I2C_REG_CTL(alg_data)); |
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if (wait_reset(alg_data)) { |
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ret = -ENODEV; |
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goto out_clock; |
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} |
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init_completion(&alg_data->mif.complete); |
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alg_data->irq = platform_get_irq(pdev, 0); |
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if (alg_data->irq < 0) { |
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ret = alg_data->irq; |
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goto out_clock; |
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} |
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ret = devm_request_irq(&pdev->dev, alg_data->irq, i2c_pnx_interrupt, |
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0, pdev->name, alg_data); |
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if (ret) |
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goto out_clock; |
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/* Register this adapter with the I2C subsystem */ |
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ret = i2c_add_numbered_adapter(&alg_data->adapter); |
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if (ret < 0) |
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goto out_clock; |
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dev_dbg(&pdev->dev, "%s: Master at %pap, irq %d.\n", |
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alg_data->adapter.name, &res->start, alg_data->irq); |
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return 0; |
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out_clock: |
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clk_disable_unprepare(alg_data->clk); |
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return ret; |
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} |
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static int i2c_pnx_remove(struct platform_device *pdev) |
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{ |
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struct i2c_pnx_algo_data *alg_data = platform_get_drvdata(pdev); |
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i2c_del_adapter(&alg_data->adapter); |
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clk_disable_unprepare(alg_data->clk); |
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return 0; |
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} |
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#ifdef CONFIG_OF |
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static const struct of_device_id i2c_pnx_of_match[] = { |
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{ .compatible = "nxp,pnx-i2c" }, |
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{ }, |
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}; |
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MODULE_DEVICE_TABLE(of, i2c_pnx_of_match); |
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#endif |
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static struct platform_driver i2c_pnx_driver = { |
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.driver = { |
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.name = "pnx-i2c", |
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.of_match_table = of_match_ptr(i2c_pnx_of_match), |
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.pm = PNX_I2C_PM, |
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}, |
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.probe = i2c_pnx_probe, |
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.remove = i2c_pnx_remove, |
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}; |
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static int __init i2c_adap_pnx_init(void) |
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{ |
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return platform_driver_register(&i2c_pnx_driver); |
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} |
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static void __exit i2c_adap_pnx_exit(void) |
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{ |
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platform_driver_unregister(&i2c_pnx_driver); |
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} |
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MODULE_AUTHOR("Vitaly Wool"); |
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MODULE_AUTHOR("Dennis Kovalev <[email protected]>"); |
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MODULE_DESCRIPTION("I2C driver for Philips IP3204-based I2C busses"); |
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MODULE_LICENSE("GPL"); |
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MODULE_ALIAS("platform:pnx-i2c"); |
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/* We need to make sure I2C is initialized before USB */ |
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subsys_initcall(i2c_adap_pnx_init); |
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module_exit(i2c_adap_pnx_exit);
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