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817 lines
19 KiB
817 lines
19 KiB
// SPDX-License-Identifier: GPL-2.0 |
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/* |
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* i2c-ocores.c: I2C bus driver for OpenCores I2C controller |
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* (https://opencores.org/project/i2c/overview) |
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* |
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* Peter Korsgaard <[email protected]> |
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* |
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* Support for the GRLIB port of the controller by |
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* Andreas Larsson <[email protected]> |
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*/ |
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|
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#include <linux/clk.h> |
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#include <linux/delay.h> |
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#include <linux/err.h> |
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#include <linux/kernel.h> |
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#include <linux/module.h> |
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#include <linux/errno.h> |
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#include <linux/platform_device.h> |
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#include <linux/i2c.h> |
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#include <linux/interrupt.h> |
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#include <linux/wait.h> |
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#include <linux/platform_data/i2c-ocores.h> |
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#include <linux/slab.h> |
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#include <linux/io.h> |
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#include <linux/log2.h> |
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#include <linux/spinlock.h> |
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#include <linux/jiffies.h> |
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/* |
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* 'process_lock' exists because ocores_process() and ocores_process_timeout() |
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* can't run in parallel. |
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*/ |
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struct ocores_i2c { |
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void __iomem *base; |
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int iobase; |
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u32 reg_shift; |
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u32 reg_io_width; |
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unsigned long flags; |
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wait_queue_head_t wait; |
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struct i2c_adapter adap; |
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struct i2c_msg *msg; |
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int pos; |
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int nmsgs; |
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int state; /* see STATE_ */ |
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spinlock_t process_lock; |
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struct clk *clk; |
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int ip_clock_khz; |
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int bus_clock_khz; |
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void (*setreg)(struct ocores_i2c *i2c, int reg, u8 value); |
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u8 (*getreg)(struct ocores_i2c *i2c, int reg); |
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}; |
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|
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/* registers */ |
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#define OCI2C_PRELOW 0 |
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#define OCI2C_PREHIGH 1 |
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#define OCI2C_CONTROL 2 |
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#define OCI2C_DATA 3 |
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#define OCI2C_CMD 4 /* write only */ |
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#define OCI2C_STATUS 4 /* read only, same address as OCI2C_CMD */ |
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#define OCI2C_CTRL_IEN 0x40 |
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#define OCI2C_CTRL_EN 0x80 |
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#define OCI2C_CMD_START 0x91 |
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#define OCI2C_CMD_STOP 0x41 |
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#define OCI2C_CMD_READ 0x21 |
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#define OCI2C_CMD_WRITE 0x11 |
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#define OCI2C_CMD_READ_ACK 0x21 |
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#define OCI2C_CMD_READ_NACK 0x29 |
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#define OCI2C_CMD_IACK 0x01 |
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#define OCI2C_STAT_IF 0x01 |
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#define OCI2C_STAT_TIP 0x02 |
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#define OCI2C_STAT_ARBLOST 0x20 |
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#define OCI2C_STAT_BUSY 0x40 |
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#define OCI2C_STAT_NACK 0x80 |
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#define STATE_DONE 0 |
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#define STATE_START 1 |
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#define STATE_WRITE 2 |
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#define STATE_READ 3 |
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#define STATE_ERROR 4 |
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#define TYPE_OCORES 0 |
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#define TYPE_GRLIB 1 |
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#define OCORES_FLAG_BROKEN_IRQ BIT(1) /* Broken IRQ for FU540-C000 SoC */ |
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static void oc_setreg_8(struct ocores_i2c *i2c, int reg, u8 value) |
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{ |
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iowrite8(value, i2c->base + (reg << i2c->reg_shift)); |
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} |
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static void oc_setreg_16(struct ocores_i2c *i2c, int reg, u8 value) |
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{ |
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iowrite16(value, i2c->base + (reg << i2c->reg_shift)); |
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} |
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static void oc_setreg_32(struct ocores_i2c *i2c, int reg, u8 value) |
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{ |
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iowrite32(value, i2c->base + (reg << i2c->reg_shift)); |
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} |
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static void oc_setreg_16be(struct ocores_i2c *i2c, int reg, u8 value) |
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{ |
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iowrite16be(value, i2c->base + (reg << i2c->reg_shift)); |
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} |
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static void oc_setreg_32be(struct ocores_i2c *i2c, int reg, u8 value) |
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{ |
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iowrite32be(value, i2c->base + (reg << i2c->reg_shift)); |
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} |
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static inline u8 oc_getreg_8(struct ocores_i2c *i2c, int reg) |
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{ |
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return ioread8(i2c->base + (reg << i2c->reg_shift)); |
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} |
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static inline u8 oc_getreg_16(struct ocores_i2c *i2c, int reg) |
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{ |
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return ioread16(i2c->base + (reg << i2c->reg_shift)); |
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} |
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static inline u8 oc_getreg_32(struct ocores_i2c *i2c, int reg) |
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{ |
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return ioread32(i2c->base + (reg << i2c->reg_shift)); |
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} |
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static inline u8 oc_getreg_16be(struct ocores_i2c *i2c, int reg) |
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{ |
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return ioread16be(i2c->base + (reg << i2c->reg_shift)); |
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} |
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static inline u8 oc_getreg_32be(struct ocores_i2c *i2c, int reg) |
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{ |
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return ioread32be(i2c->base + (reg << i2c->reg_shift)); |
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} |
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static void oc_setreg_io_8(struct ocores_i2c *i2c, int reg, u8 value) |
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{ |
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outb(value, i2c->iobase + reg); |
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} |
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static inline u8 oc_getreg_io_8(struct ocores_i2c *i2c, int reg) |
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{ |
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return inb(i2c->iobase + reg); |
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} |
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static inline void oc_setreg(struct ocores_i2c *i2c, int reg, u8 value) |
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{ |
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i2c->setreg(i2c, reg, value); |
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} |
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static inline u8 oc_getreg(struct ocores_i2c *i2c, int reg) |
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{ |
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return i2c->getreg(i2c, reg); |
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} |
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static void ocores_process(struct ocores_i2c *i2c, u8 stat) |
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{ |
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struct i2c_msg *msg = i2c->msg; |
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unsigned long flags; |
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/* |
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* If we spin here is because we are in timeout, so we are going |
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* to be in STATE_ERROR. See ocores_process_timeout() |
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*/ |
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spin_lock_irqsave(&i2c->process_lock, flags); |
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if ((i2c->state == STATE_DONE) || (i2c->state == STATE_ERROR)) { |
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/* stop has been sent */ |
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oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_IACK); |
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wake_up(&i2c->wait); |
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goto out; |
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} |
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/* error? */ |
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if (stat & OCI2C_STAT_ARBLOST) { |
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i2c->state = STATE_ERROR; |
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oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_STOP); |
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goto out; |
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} |
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if ((i2c->state == STATE_START) || (i2c->state == STATE_WRITE)) { |
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i2c->state = |
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(msg->flags & I2C_M_RD) ? STATE_READ : STATE_WRITE; |
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if (stat & OCI2C_STAT_NACK) { |
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i2c->state = STATE_ERROR; |
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oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_STOP); |
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goto out; |
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} |
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} else { |
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msg->buf[i2c->pos++] = oc_getreg(i2c, OCI2C_DATA); |
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} |
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/* end of msg? */ |
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if (i2c->pos == msg->len) { |
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i2c->nmsgs--; |
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i2c->msg++; |
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i2c->pos = 0; |
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msg = i2c->msg; |
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if (i2c->nmsgs) { /* end? */ |
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/* send start? */ |
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if (!(msg->flags & I2C_M_NOSTART)) { |
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u8 addr = i2c_8bit_addr_from_msg(msg); |
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i2c->state = STATE_START; |
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oc_setreg(i2c, OCI2C_DATA, addr); |
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oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_START); |
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goto out; |
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} |
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i2c->state = (msg->flags & I2C_M_RD) |
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? STATE_READ : STATE_WRITE; |
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} else { |
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i2c->state = STATE_DONE; |
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oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_STOP); |
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goto out; |
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} |
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} |
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if (i2c->state == STATE_READ) { |
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oc_setreg(i2c, OCI2C_CMD, i2c->pos == (msg->len-1) ? |
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OCI2C_CMD_READ_NACK : OCI2C_CMD_READ_ACK); |
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} else { |
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oc_setreg(i2c, OCI2C_DATA, msg->buf[i2c->pos++]); |
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oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_WRITE); |
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} |
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out: |
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spin_unlock_irqrestore(&i2c->process_lock, flags); |
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} |
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static irqreturn_t ocores_isr(int irq, void *dev_id) |
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{ |
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struct ocores_i2c *i2c = dev_id; |
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u8 stat = oc_getreg(i2c, OCI2C_STATUS); |
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if (i2c->flags & OCORES_FLAG_BROKEN_IRQ) { |
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if ((stat & OCI2C_STAT_IF) && !(stat & OCI2C_STAT_BUSY)) |
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return IRQ_NONE; |
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} else if (!(stat & OCI2C_STAT_IF)) { |
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return IRQ_NONE; |
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} |
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ocores_process(i2c, stat); |
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return IRQ_HANDLED; |
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} |
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/** |
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* ocores_process_timeout() - Process timeout event |
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* @i2c: ocores I2C device instance |
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*/ |
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static void ocores_process_timeout(struct ocores_i2c *i2c) |
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{ |
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unsigned long flags; |
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spin_lock_irqsave(&i2c->process_lock, flags); |
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i2c->state = STATE_ERROR; |
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oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_STOP); |
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spin_unlock_irqrestore(&i2c->process_lock, flags); |
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} |
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/** |
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* ocores_wait() - Wait until something change in a given register |
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* @i2c: ocores I2C device instance |
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* @reg: register to query |
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* @mask: bitmask to apply on register value |
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* @val: expected result |
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* @timeout: timeout in jiffies |
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* |
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* Timeout is necessary to avoid to stay here forever when the chip |
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* does not answer correctly. |
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* |
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* Return: 0 on success, -ETIMEDOUT on timeout |
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*/ |
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static int ocores_wait(struct ocores_i2c *i2c, |
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int reg, u8 mask, u8 val, |
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const unsigned long timeout) |
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{ |
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unsigned long j; |
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j = jiffies + timeout; |
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while (1) { |
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u8 status = oc_getreg(i2c, reg); |
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if ((status & mask) == val) |
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break; |
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if (time_after(jiffies, j)) |
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return -ETIMEDOUT; |
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} |
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return 0; |
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} |
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/** |
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* ocores_poll_wait() - Wait until is possible to process some data |
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* @i2c: ocores I2C device instance |
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* |
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* Used when the device is in polling mode (interrupts disabled). |
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* |
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* Return: 0 on success, -ETIMEDOUT on timeout |
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*/ |
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static int ocores_poll_wait(struct ocores_i2c *i2c) |
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{ |
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u8 mask; |
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int err; |
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if (i2c->state == STATE_DONE || i2c->state == STATE_ERROR) { |
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/* transfer is over */ |
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mask = OCI2C_STAT_BUSY; |
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} else { |
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/* on going transfer */ |
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mask = OCI2C_STAT_TIP; |
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/* |
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* We wait for the data to be transferred (8bit), |
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* then we start polling on the ACK/NACK bit |
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*/ |
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udelay((8 * 1000) / i2c->bus_clock_khz); |
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} |
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/* |
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* once we are here we expect to get the expected result immediately |
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* so if after 1ms we timeout then something is broken. |
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*/ |
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err = ocores_wait(i2c, OCI2C_STATUS, mask, 0, msecs_to_jiffies(1)); |
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if (err) |
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dev_warn(i2c->adap.dev.parent, |
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"%s: STATUS timeout, bit 0x%x did not clear in 1ms\n", |
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__func__, mask); |
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return err; |
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} |
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/** |
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* ocores_process_polling() - It handles an IRQ-less transfer |
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* @i2c: ocores I2C device instance |
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* |
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* Even if IRQ are disabled, the I2C OpenCore IP behavior is exactly the same |
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* (only that IRQ are not produced). This means that we can re-use entirely |
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* ocores_isr(), we just add our polling code around it. |
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* |
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* It can run in atomic context |
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*/ |
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static void ocores_process_polling(struct ocores_i2c *i2c) |
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{ |
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while (1) { |
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irqreturn_t ret; |
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int err; |
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err = ocores_poll_wait(i2c); |
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if (err) { |
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i2c->state = STATE_ERROR; |
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break; /* timeout */ |
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} |
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ret = ocores_isr(-1, i2c); |
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if (ret == IRQ_NONE) |
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break; /* all messages have been transferred */ |
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else { |
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if (i2c->flags & OCORES_FLAG_BROKEN_IRQ) |
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if (i2c->state == STATE_DONE) |
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break; |
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} |
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} |
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} |
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static int ocores_xfer_core(struct ocores_i2c *i2c, |
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struct i2c_msg *msgs, int num, |
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bool polling) |
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{ |
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int ret; |
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u8 ctrl; |
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ctrl = oc_getreg(i2c, OCI2C_CONTROL); |
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if (polling) |
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oc_setreg(i2c, OCI2C_CONTROL, ctrl & ~OCI2C_CTRL_IEN); |
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else |
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oc_setreg(i2c, OCI2C_CONTROL, ctrl | OCI2C_CTRL_IEN); |
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i2c->msg = msgs; |
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i2c->pos = 0; |
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i2c->nmsgs = num; |
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i2c->state = STATE_START; |
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oc_setreg(i2c, OCI2C_DATA, i2c_8bit_addr_from_msg(i2c->msg)); |
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oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_START); |
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if (polling) { |
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ocores_process_polling(i2c); |
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} else { |
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ret = wait_event_timeout(i2c->wait, |
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(i2c->state == STATE_ERROR) || |
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(i2c->state == STATE_DONE), HZ); |
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if (ret == 0) { |
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ocores_process_timeout(i2c); |
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return -ETIMEDOUT; |
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} |
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} |
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return (i2c->state == STATE_DONE) ? num : -EIO; |
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} |
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static int ocores_xfer_polling(struct i2c_adapter *adap, |
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struct i2c_msg *msgs, int num) |
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{ |
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return ocores_xfer_core(i2c_get_adapdata(adap), msgs, num, true); |
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} |
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static int ocores_xfer(struct i2c_adapter *adap, |
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struct i2c_msg *msgs, int num) |
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{ |
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return ocores_xfer_core(i2c_get_adapdata(adap), msgs, num, false); |
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} |
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static int ocores_init(struct device *dev, struct ocores_i2c *i2c) |
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{ |
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int prescale; |
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int diff; |
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u8 ctrl = oc_getreg(i2c, OCI2C_CONTROL); |
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/* make sure the device is disabled */ |
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ctrl &= ~(OCI2C_CTRL_EN | OCI2C_CTRL_IEN); |
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oc_setreg(i2c, OCI2C_CONTROL, ctrl); |
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prescale = (i2c->ip_clock_khz / (5 * i2c->bus_clock_khz)) - 1; |
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prescale = clamp(prescale, 0, 0xffff); |
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diff = i2c->ip_clock_khz / (5 * (prescale + 1)) - i2c->bus_clock_khz; |
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if (abs(diff) > i2c->bus_clock_khz / 10) { |
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dev_err(dev, |
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"Unsupported clock settings: core: %d KHz, bus: %d KHz\n", |
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i2c->ip_clock_khz, i2c->bus_clock_khz); |
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return -EINVAL; |
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} |
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oc_setreg(i2c, OCI2C_PRELOW, prescale & 0xff); |
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oc_setreg(i2c, OCI2C_PREHIGH, prescale >> 8); |
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/* Init the device */ |
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oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_IACK); |
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oc_setreg(i2c, OCI2C_CONTROL, ctrl | OCI2C_CTRL_EN); |
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return 0; |
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} |
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static u32 ocores_func(struct i2c_adapter *adap) |
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{ |
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return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; |
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} |
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static struct i2c_algorithm ocores_algorithm = { |
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.master_xfer = ocores_xfer, |
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.master_xfer_atomic = ocores_xfer_polling, |
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.functionality = ocores_func, |
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}; |
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static const struct i2c_adapter ocores_adapter = { |
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.owner = THIS_MODULE, |
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.name = "i2c-ocores", |
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.class = I2C_CLASS_DEPRECATED, |
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.algo = &ocores_algorithm, |
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}; |
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static const struct of_device_id ocores_i2c_match[] = { |
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{ |
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.compatible = "opencores,i2c-ocores", |
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.data = (void *)TYPE_OCORES, |
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}, |
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{ |
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.compatible = "aeroflexgaisler,i2cmst", |
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.data = (void *)TYPE_GRLIB, |
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}, |
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{ |
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.compatible = "sifive,fu540-c000-i2c", |
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}, |
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{ |
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.compatible = "sifive,i2c0", |
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}, |
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{}, |
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}; |
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MODULE_DEVICE_TABLE(of, ocores_i2c_match); |
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|
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#ifdef CONFIG_OF |
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/* |
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* Read and write functions for the GRLIB port of the controller. Registers are |
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* 32-bit big endian and the PRELOW and PREHIGH registers are merged into one |
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* register. The subsequent registers have their offsets decreased accordingly. |
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*/ |
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static u8 oc_getreg_grlib(struct ocores_i2c *i2c, int reg) |
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{ |
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u32 rd; |
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int rreg = reg; |
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if (reg != OCI2C_PRELOW) |
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rreg--; |
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rd = ioread32be(i2c->base + (rreg << i2c->reg_shift)); |
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if (reg == OCI2C_PREHIGH) |
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return (u8)(rd >> 8); |
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else |
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return (u8)rd; |
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} |
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static void oc_setreg_grlib(struct ocores_i2c *i2c, int reg, u8 value) |
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{ |
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u32 curr, wr; |
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int rreg = reg; |
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|
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if (reg != OCI2C_PRELOW) |
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rreg--; |
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if (reg == OCI2C_PRELOW || reg == OCI2C_PREHIGH) { |
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curr = ioread32be(i2c->base + (rreg << i2c->reg_shift)); |
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if (reg == OCI2C_PRELOW) |
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wr = (curr & 0xff00) | value; |
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else |
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wr = (((u32)value) << 8) | (curr & 0xff); |
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} else { |
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wr = value; |
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} |
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iowrite32be(wr, i2c->base + (rreg << i2c->reg_shift)); |
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} |
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static int ocores_i2c_of_probe(struct platform_device *pdev, |
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struct ocores_i2c *i2c) |
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{ |
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struct device_node *np = pdev->dev.of_node; |
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const struct of_device_id *match; |
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u32 val; |
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u32 clock_frequency; |
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bool clock_frequency_present; |
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|
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if (of_property_read_u32(np, "reg-shift", &i2c->reg_shift)) { |
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/* no 'reg-shift', check for deprecated 'regstep' */ |
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if (!of_property_read_u32(np, "regstep", &val)) { |
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if (!is_power_of_2(val)) { |
|
dev_err(&pdev->dev, "invalid regstep %d\n", |
|
val); |
|
return -EINVAL; |
|
} |
|
i2c->reg_shift = ilog2(val); |
|
dev_warn(&pdev->dev, |
|
"regstep property deprecated, use reg-shift\n"); |
|
} |
|
} |
|
|
|
clock_frequency_present = !of_property_read_u32(np, "clock-frequency", |
|
&clock_frequency); |
|
i2c->bus_clock_khz = 100; |
|
|
|
i2c->clk = devm_clk_get(&pdev->dev, NULL); |
|
|
|
if (!IS_ERR(i2c->clk)) { |
|
int ret = clk_prepare_enable(i2c->clk); |
|
|
|
if (ret) { |
|
dev_err(&pdev->dev, |
|
"clk_prepare_enable failed: %d\n", ret); |
|
return ret; |
|
} |
|
i2c->ip_clock_khz = clk_get_rate(i2c->clk) / 1000; |
|
if (clock_frequency_present) |
|
i2c->bus_clock_khz = clock_frequency / 1000; |
|
} |
|
|
|
if (i2c->ip_clock_khz == 0) { |
|
if (of_property_read_u32(np, "opencores,ip-clock-frequency", |
|
&val)) { |
|
if (!clock_frequency_present) { |
|
dev_err(&pdev->dev, |
|
"Missing required parameter 'opencores,ip-clock-frequency'\n"); |
|
clk_disable_unprepare(i2c->clk); |
|
return -ENODEV; |
|
} |
|
i2c->ip_clock_khz = clock_frequency / 1000; |
|
dev_warn(&pdev->dev, |
|
"Deprecated usage of the 'clock-frequency' property, please update to 'opencores,ip-clock-frequency'\n"); |
|
} else { |
|
i2c->ip_clock_khz = val / 1000; |
|
if (clock_frequency_present) |
|
i2c->bus_clock_khz = clock_frequency / 1000; |
|
} |
|
} |
|
|
|
of_property_read_u32(pdev->dev.of_node, "reg-io-width", |
|
&i2c->reg_io_width); |
|
|
|
match = of_match_node(ocores_i2c_match, pdev->dev.of_node); |
|
if (match && (long)match->data == TYPE_GRLIB) { |
|
dev_dbg(&pdev->dev, "GRLIB variant of i2c-ocores\n"); |
|
i2c->setreg = oc_setreg_grlib; |
|
i2c->getreg = oc_getreg_grlib; |
|
} |
|
|
|
return 0; |
|
} |
|
#else |
|
#define ocores_i2c_of_probe(pdev, i2c) -ENODEV |
|
#endif |
|
|
|
static int ocores_i2c_probe(struct platform_device *pdev) |
|
{ |
|
struct ocores_i2c *i2c; |
|
struct ocores_i2c_platform_data *pdata; |
|
struct resource *res; |
|
int irq; |
|
int ret; |
|
int i; |
|
|
|
i2c = devm_kzalloc(&pdev->dev, sizeof(*i2c), GFP_KERNEL); |
|
if (!i2c) |
|
return -ENOMEM; |
|
|
|
spin_lock_init(&i2c->process_lock); |
|
|
|
res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
|
if (res) { |
|
i2c->base = devm_ioremap_resource(&pdev->dev, res); |
|
if (IS_ERR(i2c->base)) |
|
return PTR_ERR(i2c->base); |
|
} else { |
|
res = platform_get_resource(pdev, IORESOURCE_IO, 0); |
|
if (!res) |
|
return -EINVAL; |
|
i2c->iobase = res->start; |
|
if (!devm_request_region(&pdev->dev, res->start, |
|
resource_size(res), |
|
pdev->name)) { |
|
dev_err(&pdev->dev, "Can't get I/O resource.\n"); |
|
return -EBUSY; |
|
} |
|
i2c->setreg = oc_setreg_io_8; |
|
i2c->getreg = oc_getreg_io_8; |
|
} |
|
|
|
pdata = dev_get_platdata(&pdev->dev); |
|
if (pdata) { |
|
i2c->reg_shift = pdata->reg_shift; |
|
i2c->reg_io_width = pdata->reg_io_width; |
|
i2c->ip_clock_khz = pdata->clock_khz; |
|
if (pdata->bus_khz) |
|
i2c->bus_clock_khz = pdata->bus_khz; |
|
else |
|
i2c->bus_clock_khz = 100; |
|
} else { |
|
ret = ocores_i2c_of_probe(pdev, i2c); |
|
if (ret) |
|
return ret; |
|
} |
|
|
|
if (i2c->reg_io_width == 0) |
|
i2c->reg_io_width = 1; /* Set to default value */ |
|
|
|
if (!i2c->setreg || !i2c->getreg) { |
|
bool be = pdata ? pdata->big_endian : |
|
of_device_is_big_endian(pdev->dev.of_node); |
|
|
|
switch (i2c->reg_io_width) { |
|
case 1: |
|
i2c->setreg = oc_setreg_8; |
|
i2c->getreg = oc_getreg_8; |
|
break; |
|
|
|
case 2: |
|
i2c->setreg = be ? oc_setreg_16be : oc_setreg_16; |
|
i2c->getreg = be ? oc_getreg_16be : oc_getreg_16; |
|
break; |
|
|
|
case 4: |
|
i2c->setreg = be ? oc_setreg_32be : oc_setreg_32; |
|
i2c->getreg = be ? oc_getreg_32be : oc_getreg_32; |
|
break; |
|
|
|
default: |
|
dev_err(&pdev->dev, "Unsupported I/O width (%d)\n", |
|
i2c->reg_io_width); |
|
ret = -EINVAL; |
|
goto err_clk; |
|
} |
|
} |
|
|
|
init_waitqueue_head(&i2c->wait); |
|
|
|
irq = platform_get_irq_optional(pdev, 0); |
|
/* |
|
* Since the SoC does have an interrupt, its DT has an interrupt |
|
* property - But this should be bypassed as the IRQ logic in this |
|
* SoC is broken. |
|
*/ |
|
if (of_device_is_compatible(pdev->dev.of_node, |
|
"sifive,fu540-c000-i2c")) { |
|
i2c->flags |= OCORES_FLAG_BROKEN_IRQ; |
|
irq = -ENXIO; |
|
} |
|
|
|
if (irq == -ENXIO) { |
|
ocores_algorithm.master_xfer = ocores_xfer_polling; |
|
} else { |
|
if (irq < 0) |
|
return irq; |
|
} |
|
|
|
if (ocores_algorithm.master_xfer != ocores_xfer_polling) { |
|
ret = devm_request_any_context_irq(&pdev->dev, irq, |
|
ocores_isr, 0, |
|
pdev->name, i2c); |
|
if (ret) { |
|
dev_err(&pdev->dev, "Cannot claim IRQ\n"); |
|
goto err_clk; |
|
} |
|
} |
|
|
|
ret = ocores_init(&pdev->dev, i2c); |
|
if (ret) |
|
goto err_clk; |
|
|
|
/* hook up driver to tree */ |
|
platform_set_drvdata(pdev, i2c); |
|
i2c->adap = ocores_adapter; |
|
i2c_set_adapdata(&i2c->adap, i2c); |
|
i2c->adap.dev.parent = &pdev->dev; |
|
i2c->adap.dev.of_node = pdev->dev.of_node; |
|
|
|
/* add i2c adapter to i2c tree */ |
|
ret = i2c_add_adapter(&i2c->adap); |
|
if (ret) |
|
goto err_clk; |
|
|
|
/* add in known devices to the bus */ |
|
if (pdata) { |
|
for (i = 0; i < pdata->num_devices; i++) |
|
i2c_new_client_device(&i2c->adap, pdata->devices + i); |
|
} |
|
|
|
return 0; |
|
|
|
err_clk: |
|
clk_disable_unprepare(i2c->clk); |
|
return ret; |
|
} |
|
|
|
static int ocores_i2c_remove(struct platform_device *pdev) |
|
{ |
|
struct ocores_i2c *i2c = platform_get_drvdata(pdev); |
|
u8 ctrl = oc_getreg(i2c, OCI2C_CONTROL); |
|
|
|
/* disable i2c logic */ |
|
ctrl &= ~(OCI2C_CTRL_EN | OCI2C_CTRL_IEN); |
|
oc_setreg(i2c, OCI2C_CONTROL, ctrl); |
|
|
|
/* remove adapter & data */ |
|
i2c_del_adapter(&i2c->adap); |
|
|
|
if (!IS_ERR(i2c->clk)) |
|
clk_disable_unprepare(i2c->clk); |
|
|
|
return 0; |
|
} |
|
|
|
#ifdef CONFIG_PM_SLEEP |
|
static int ocores_i2c_suspend(struct device *dev) |
|
{ |
|
struct ocores_i2c *i2c = dev_get_drvdata(dev); |
|
u8 ctrl = oc_getreg(i2c, OCI2C_CONTROL); |
|
|
|
/* make sure the device is disabled */ |
|
ctrl &= ~(OCI2C_CTRL_EN | OCI2C_CTRL_IEN); |
|
oc_setreg(i2c, OCI2C_CONTROL, ctrl); |
|
|
|
if (!IS_ERR(i2c->clk)) |
|
clk_disable_unprepare(i2c->clk); |
|
return 0; |
|
} |
|
|
|
static int ocores_i2c_resume(struct device *dev) |
|
{ |
|
struct ocores_i2c *i2c = dev_get_drvdata(dev); |
|
|
|
if (!IS_ERR(i2c->clk)) { |
|
unsigned long rate; |
|
int ret = clk_prepare_enable(i2c->clk); |
|
|
|
if (ret) { |
|
dev_err(dev, |
|
"clk_prepare_enable failed: %d\n", ret); |
|
return ret; |
|
} |
|
rate = clk_get_rate(i2c->clk) / 1000; |
|
if (rate) |
|
i2c->ip_clock_khz = rate; |
|
} |
|
return ocores_init(dev, i2c); |
|
} |
|
|
|
static SIMPLE_DEV_PM_OPS(ocores_i2c_pm, ocores_i2c_suspend, ocores_i2c_resume); |
|
#define OCORES_I2C_PM (&ocores_i2c_pm) |
|
#else |
|
#define OCORES_I2C_PM NULL |
|
#endif |
|
|
|
static struct platform_driver ocores_i2c_driver = { |
|
.probe = ocores_i2c_probe, |
|
.remove = ocores_i2c_remove, |
|
.driver = { |
|
.name = "ocores-i2c", |
|
.of_match_table = ocores_i2c_match, |
|
.pm = OCORES_I2C_PM, |
|
}, |
|
}; |
|
|
|
module_platform_driver(ocores_i2c_driver); |
|
|
|
MODULE_AUTHOR("Peter Korsgaard <[email protected]>"); |
|
MODULE_DESCRIPTION("OpenCores I2C bus driver"); |
|
MODULE_LICENSE("GPL"); |
|
MODULE_ALIAS("platform:ocores-i2c");
|
|
|