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838 lines
23 KiB
838 lines
23 KiB
// SPDX-License-Identifier: GPL-2.0-only |
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/* |
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* This driver implements I2C master functionality using the LSI API2C |
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* controller. |
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* |
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* NOTE: The controller has a limitation in that it can only do transfers of |
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* maximum 255 bytes at a time. If a larger transfer is attempted, error code |
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* (-EINVAL) is returned. |
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*/ |
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#include <linux/clk.h> |
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#include <linux/clkdev.h> |
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#include <linux/delay.h> |
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#include <linux/err.h> |
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#include <linux/i2c.h> |
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#include <linux/init.h> |
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#include <linux/interrupt.h> |
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#include <linux/module.h> |
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#include <linux/io.h> |
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#include <linux/kernel.h> |
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#include <linux/platform_device.h> |
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#define SCL_WAIT_TIMEOUT_NS 25000000 |
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#define I2C_XFER_TIMEOUT (msecs_to_jiffies(250)) |
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#define I2C_STOP_TIMEOUT (msecs_to_jiffies(100)) |
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#define FIFO_SIZE 8 |
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#define SEQ_LEN 2 |
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#define GLOBAL_CONTROL 0x00 |
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#define GLOBAL_MST_EN BIT(0) |
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#define GLOBAL_SLV_EN BIT(1) |
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#define GLOBAL_IBML_EN BIT(2) |
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#define INTERRUPT_STATUS 0x04 |
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#define INTERRUPT_ENABLE 0x08 |
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#define INT_SLV BIT(1) |
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#define INT_MST BIT(0) |
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#define WAIT_TIMER_CONTROL 0x0c |
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#define WT_EN BIT(15) |
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#define WT_VALUE(_x) ((_x) & 0x7fff) |
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#define IBML_TIMEOUT 0x10 |
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#define IBML_LOW_MEXT 0x14 |
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#define IBML_LOW_SEXT 0x18 |
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#define TIMER_CLOCK_DIV 0x1c |
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#define I2C_BUS_MONITOR 0x20 |
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#define BM_SDAC BIT(3) |
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#define BM_SCLC BIT(2) |
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#define BM_SDAS BIT(1) |
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#define BM_SCLS BIT(0) |
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#define SOFT_RESET 0x24 |
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#define MST_COMMAND 0x28 |
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#define CMD_BUSY (1<<3) |
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#define CMD_MANUAL (0x00 | CMD_BUSY) |
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#define CMD_AUTO (0x01 | CMD_BUSY) |
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#define CMD_SEQUENCE (0x02 | CMD_BUSY) |
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#define MST_RX_XFER 0x2c |
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#define MST_TX_XFER 0x30 |
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#define MST_ADDR_1 0x34 |
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#define MST_ADDR_2 0x38 |
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#define MST_DATA 0x3c |
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#define MST_TX_FIFO 0x40 |
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#define MST_RX_FIFO 0x44 |
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#define MST_INT_ENABLE 0x48 |
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#define MST_INT_STATUS 0x4c |
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#define MST_STATUS_RFL (1 << 13) /* RX FIFO serivce */ |
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#define MST_STATUS_TFL (1 << 12) /* TX FIFO service */ |
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#define MST_STATUS_SNS (1 << 11) /* Manual mode done */ |
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#define MST_STATUS_SS (1 << 10) /* Automatic mode done */ |
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#define MST_STATUS_SCC (1 << 9) /* Stop complete */ |
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#define MST_STATUS_IP (1 << 8) /* Invalid parameter */ |
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#define MST_STATUS_TSS (1 << 7) /* Timeout */ |
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#define MST_STATUS_AL (1 << 6) /* Arbitration lost */ |
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#define MST_STATUS_ND (1 << 5) /* NAK on data phase */ |
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#define MST_STATUS_NA (1 << 4) /* NAK on address phase */ |
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#define MST_STATUS_NAK (MST_STATUS_NA | \ |
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MST_STATUS_ND) |
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#define MST_STATUS_ERR (MST_STATUS_NAK | \ |
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MST_STATUS_AL | \ |
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MST_STATUS_IP) |
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#define MST_TX_BYTES_XFRD 0x50 |
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#define MST_RX_BYTES_XFRD 0x54 |
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#define SLV_ADDR_DEC_CTL 0x58 |
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#define SLV_ADDR_DEC_GCE BIT(0) /* ACK to General Call Address from own master (loopback) */ |
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#define SLV_ADDR_DEC_OGCE BIT(1) /* ACK to General Call Address from external masters */ |
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#define SLV_ADDR_DEC_SA1E BIT(2) /* ACK to addr_1 enabled */ |
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#define SLV_ADDR_DEC_SA1M BIT(3) /* 10-bit addressing for addr_1 enabled */ |
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#define SLV_ADDR_DEC_SA2E BIT(4) /* ACK to addr_2 enabled */ |
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#define SLV_ADDR_DEC_SA2M BIT(5) /* 10-bit addressing for addr_2 enabled */ |
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#define SLV_ADDR_1 0x5c |
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#define SLV_ADDR_2 0x60 |
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#define SLV_RX_CTL 0x64 |
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#define SLV_RX_ACSA1 BIT(0) /* Generate ACK for writes to addr_1 */ |
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#define SLV_RX_ACSA2 BIT(1) /* Generate ACK for writes to addr_2 */ |
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#define SLV_RX_ACGCA BIT(2) /* ACK data phase transfers to General Call Address */ |
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#define SLV_DATA 0x68 |
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#define SLV_RX_FIFO 0x6c |
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#define SLV_FIFO_DV1 BIT(0) /* Data Valid for addr_1 */ |
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#define SLV_FIFO_DV2 BIT(1) /* Data Valid for addr_2 */ |
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#define SLV_FIFO_AS BIT(2) /* (N)ACK Sent */ |
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#define SLV_FIFO_TNAK BIT(3) /* Timeout NACK */ |
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#define SLV_FIFO_STRC BIT(4) /* First byte after start condition received */ |
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#define SLV_FIFO_RSC BIT(5) /* Repeated Start Condition */ |
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#define SLV_FIFO_STPC BIT(6) /* Stop Condition */ |
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#define SLV_FIFO_DV (SLV_FIFO_DV1 | SLV_FIFO_DV2) |
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#define SLV_INT_ENABLE 0x70 |
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#define SLV_INT_STATUS 0x74 |
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#define SLV_STATUS_RFH BIT(0) /* FIFO service */ |
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#define SLV_STATUS_WTC BIT(1) /* Write transfer complete */ |
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#define SLV_STATUS_SRS1 BIT(2) /* Slave read from addr 1 */ |
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#define SLV_STATUS_SRRS1 BIT(3) /* Repeated start from addr 1 */ |
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#define SLV_STATUS_SRND1 BIT(4) /* Read request not following start condition */ |
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#define SLV_STATUS_SRC1 BIT(5) /* Read canceled */ |
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#define SLV_STATUS_SRAT1 BIT(6) /* Slave Read timed out */ |
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#define SLV_STATUS_SRDRE1 BIT(7) /* Data written after timed out */ |
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#define SLV_READ_DUMMY 0x78 |
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#define SCL_HIGH_PERIOD 0x80 |
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#define SCL_LOW_PERIOD 0x84 |
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#define SPIKE_FLTR_LEN 0x88 |
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#define SDA_SETUP_TIME 0x8c |
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#define SDA_HOLD_TIME 0x90 |
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/** |
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* axxia_i2c_dev - I2C device context |
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* @base: pointer to register struct |
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* @msg: pointer to current message |
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* @msg_r: pointer to current read message (sequence transfer) |
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* @msg_xfrd: number of bytes transferred in tx_fifo |
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* @msg_xfrd_r: number of bytes transferred in rx_fifo |
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* @msg_err: error code for completed message |
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* @msg_complete: xfer completion object |
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* @dev: device reference |
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* @adapter: core i2c abstraction |
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* @i2c_clk: clock reference for i2c input clock |
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* @bus_clk_rate: current i2c bus clock rate |
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* @last: a flag indicating is this is last message in transfer |
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*/ |
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struct axxia_i2c_dev { |
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void __iomem *base; |
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struct i2c_msg *msg; |
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struct i2c_msg *msg_r; |
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size_t msg_xfrd; |
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size_t msg_xfrd_r; |
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int msg_err; |
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struct completion msg_complete; |
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struct device *dev; |
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struct i2c_adapter adapter; |
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struct clk *i2c_clk; |
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u32 bus_clk_rate; |
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bool last; |
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struct i2c_client *slave; |
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int irq; |
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}; |
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static void i2c_int_disable(struct axxia_i2c_dev *idev, u32 mask) |
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{ |
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u32 int_en; |
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int_en = readl(idev->base + MST_INT_ENABLE); |
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writel(int_en & ~mask, idev->base + MST_INT_ENABLE); |
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} |
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static void i2c_int_enable(struct axxia_i2c_dev *idev, u32 mask) |
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{ |
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u32 int_en; |
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int_en = readl(idev->base + MST_INT_ENABLE); |
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writel(int_en | mask, idev->base + MST_INT_ENABLE); |
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} |
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/** |
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* ns_to_clk - Convert time (ns) to clock cycles for the given clock frequency. |
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*/ |
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static u32 ns_to_clk(u64 ns, u32 clk_mhz) |
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{ |
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return div_u64(ns * clk_mhz, 1000); |
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} |
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static int axxia_i2c_init(struct axxia_i2c_dev *idev) |
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{ |
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u32 divisor = clk_get_rate(idev->i2c_clk) / idev->bus_clk_rate; |
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u32 clk_mhz = clk_get_rate(idev->i2c_clk) / 1000000; |
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u32 t_setup; |
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u32 t_high, t_low; |
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u32 tmo_clk; |
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u32 prescale; |
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unsigned long timeout; |
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dev_dbg(idev->dev, "rate=%uHz per_clk=%uMHz -> ratio=1:%u\n", |
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idev->bus_clk_rate, clk_mhz, divisor); |
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/* Reset controller */ |
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writel(0x01, idev->base + SOFT_RESET); |
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timeout = jiffies + msecs_to_jiffies(100); |
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while (readl(idev->base + SOFT_RESET) & 1) { |
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if (time_after(jiffies, timeout)) { |
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dev_warn(idev->dev, "Soft reset failed\n"); |
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break; |
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} |
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} |
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/* Enable Master Mode */ |
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writel(0x1, idev->base + GLOBAL_CONTROL); |
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if (idev->bus_clk_rate <= I2C_MAX_STANDARD_MODE_FREQ) { |
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/* Standard mode SCL 50/50, tSU:DAT = 250 ns */ |
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t_high = divisor * 1 / 2; |
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t_low = divisor * 1 / 2; |
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t_setup = ns_to_clk(250, clk_mhz); |
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} else { |
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/* Fast mode SCL 33/66, tSU:DAT = 100 ns */ |
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t_high = divisor * 1 / 3; |
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t_low = divisor * 2 / 3; |
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t_setup = ns_to_clk(100, clk_mhz); |
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} |
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/* SCL High Time */ |
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writel(t_high, idev->base + SCL_HIGH_PERIOD); |
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/* SCL Low Time */ |
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writel(t_low, idev->base + SCL_LOW_PERIOD); |
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/* SDA Setup Time */ |
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writel(t_setup, idev->base + SDA_SETUP_TIME); |
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/* SDA Hold Time, 300ns */ |
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writel(ns_to_clk(300, clk_mhz), idev->base + SDA_HOLD_TIME); |
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/* Filter <50ns spikes */ |
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writel(ns_to_clk(50, clk_mhz), idev->base + SPIKE_FLTR_LEN); |
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/* Configure Time-Out Registers */ |
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tmo_clk = ns_to_clk(SCL_WAIT_TIMEOUT_NS, clk_mhz); |
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/* Find prescaler value that makes tmo_clk fit in 15-bits counter. */ |
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for (prescale = 0; prescale < 15; ++prescale) { |
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if (tmo_clk <= 0x7fff) |
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break; |
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tmo_clk >>= 1; |
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} |
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if (tmo_clk > 0x7fff) |
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tmo_clk = 0x7fff; |
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/* Prescale divider (log2) */ |
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writel(prescale, idev->base + TIMER_CLOCK_DIV); |
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/* Timeout in divided clocks */ |
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writel(WT_EN | WT_VALUE(tmo_clk), idev->base + WAIT_TIMER_CONTROL); |
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/* Mask all master interrupt bits */ |
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i2c_int_disable(idev, ~0); |
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/* Interrupt enable */ |
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writel(0x01, idev->base + INTERRUPT_ENABLE); |
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return 0; |
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} |
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static int i2c_m_rd(const struct i2c_msg *msg) |
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{ |
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return (msg->flags & I2C_M_RD) != 0; |
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} |
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static int i2c_m_ten(const struct i2c_msg *msg) |
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{ |
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return (msg->flags & I2C_M_TEN) != 0; |
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} |
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static int i2c_m_recv_len(const struct i2c_msg *msg) |
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{ |
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return (msg->flags & I2C_M_RECV_LEN) != 0; |
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} |
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/** |
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* axxia_i2c_empty_rx_fifo - Fetch data from RX FIFO and update SMBus block |
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* transfer length if this is the first byte of such a transfer. |
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*/ |
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static int axxia_i2c_empty_rx_fifo(struct axxia_i2c_dev *idev) |
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{ |
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struct i2c_msg *msg = idev->msg_r; |
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size_t rx_fifo_avail = readl(idev->base + MST_RX_FIFO); |
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int bytes_to_transfer = min(rx_fifo_avail, msg->len - idev->msg_xfrd_r); |
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while (bytes_to_transfer-- > 0) { |
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int c = readl(idev->base + MST_DATA); |
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if (idev->msg_xfrd_r == 0 && i2c_m_recv_len(msg)) { |
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/* |
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* Check length byte for SMBus block read |
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*/ |
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if (c <= 0 || c > I2C_SMBUS_BLOCK_MAX) { |
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idev->msg_err = -EPROTO; |
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i2c_int_disable(idev, ~MST_STATUS_TSS); |
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complete(&idev->msg_complete); |
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break; |
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} |
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msg->len = 1 + c; |
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writel(msg->len, idev->base + MST_RX_XFER); |
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} |
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msg->buf[idev->msg_xfrd_r++] = c; |
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} |
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return 0; |
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} |
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/** |
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* axxia_i2c_fill_tx_fifo - Fill TX FIFO from current message buffer. |
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* @return: Number of bytes left to transfer. |
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*/ |
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static int axxia_i2c_fill_tx_fifo(struct axxia_i2c_dev *idev) |
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{ |
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struct i2c_msg *msg = idev->msg; |
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size_t tx_fifo_avail = FIFO_SIZE - readl(idev->base + MST_TX_FIFO); |
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int bytes_to_transfer = min(tx_fifo_avail, msg->len - idev->msg_xfrd); |
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int ret = msg->len - idev->msg_xfrd - bytes_to_transfer; |
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while (bytes_to_transfer-- > 0) |
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writel(msg->buf[idev->msg_xfrd++], idev->base + MST_DATA); |
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return ret; |
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} |
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static void axxia_i2c_slv_fifo_event(struct axxia_i2c_dev *idev) |
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{ |
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u32 fifo_status = readl(idev->base + SLV_RX_FIFO); |
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u8 val; |
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dev_dbg(idev->dev, "slave irq fifo_status=0x%x\n", fifo_status); |
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if (fifo_status & SLV_FIFO_DV1) { |
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if (fifo_status & SLV_FIFO_STRC) |
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i2c_slave_event(idev->slave, |
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I2C_SLAVE_WRITE_REQUESTED, &val); |
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val = readl(idev->base + SLV_DATA); |
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i2c_slave_event(idev->slave, I2C_SLAVE_WRITE_RECEIVED, &val); |
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} |
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if (fifo_status & SLV_FIFO_STPC) { |
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readl(idev->base + SLV_DATA); /* dummy read */ |
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i2c_slave_event(idev->slave, I2C_SLAVE_STOP, &val); |
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} |
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if (fifo_status & SLV_FIFO_RSC) |
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readl(idev->base + SLV_DATA); /* dummy read */ |
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} |
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static irqreturn_t axxia_i2c_slv_isr(struct axxia_i2c_dev *idev) |
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{ |
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u32 status = readl(idev->base + SLV_INT_STATUS); |
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u8 val; |
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dev_dbg(idev->dev, "slave irq status=0x%x\n", status); |
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if (status & SLV_STATUS_RFH) |
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axxia_i2c_slv_fifo_event(idev); |
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if (status & SLV_STATUS_SRS1) { |
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i2c_slave_event(idev->slave, I2C_SLAVE_READ_REQUESTED, &val); |
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writel(val, idev->base + SLV_DATA); |
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} |
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if (status & SLV_STATUS_SRND1) { |
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i2c_slave_event(idev->slave, I2C_SLAVE_READ_PROCESSED, &val); |
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writel(val, idev->base + SLV_DATA); |
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} |
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if (status & SLV_STATUS_SRC1) |
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i2c_slave_event(idev->slave, I2C_SLAVE_STOP, &val); |
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writel(INT_SLV, idev->base + INTERRUPT_STATUS); |
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return IRQ_HANDLED; |
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} |
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static irqreturn_t axxia_i2c_isr(int irq, void *_dev) |
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{ |
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struct axxia_i2c_dev *idev = _dev; |
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irqreturn_t ret = IRQ_NONE; |
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u32 status; |
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status = readl(idev->base + INTERRUPT_STATUS); |
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if (status & INT_SLV) |
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ret = axxia_i2c_slv_isr(idev); |
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if (!(status & INT_MST)) |
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return ret; |
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/* Read interrupt status bits */ |
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status = readl(idev->base + MST_INT_STATUS); |
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if (!idev->msg) { |
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dev_warn(idev->dev, "unexpected interrupt\n"); |
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goto out; |
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} |
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/* RX FIFO needs service? */ |
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if (i2c_m_rd(idev->msg_r) && (status & MST_STATUS_RFL)) |
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axxia_i2c_empty_rx_fifo(idev); |
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/* TX FIFO needs service? */ |
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if (!i2c_m_rd(idev->msg) && (status & MST_STATUS_TFL)) { |
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if (axxia_i2c_fill_tx_fifo(idev) == 0) |
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i2c_int_disable(idev, MST_STATUS_TFL); |
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} |
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if (unlikely(status & MST_STATUS_ERR)) { |
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/* Transfer error */ |
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i2c_int_disable(idev, ~0); |
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if (status & MST_STATUS_AL) |
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idev->msg_err = -EAGAIN; |
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else if (status & MST_STATUS_NAK) |
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idev->msg_err = -ENXIO; |
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else |
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idev->msg_err = -EIO; |
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dev_dbg(idev->dev, "error %#x, addr=%#x rx=%u/%u tx=%u/%u\n", |
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status, |
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idev->msg->addr, |
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readl(idev->base + MST_RX_BYTES_XFRD), |
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readl(idev->base + MST_RX_XFER), |
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readl(idev->base + MST_TX_BYTES_XFRD), |
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readl(idev->base + MST_TX_XFER)); |
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complete(&idev->msg_complete); |
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} else if (status & MST_STATUS_SCC) { |
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/* Stop completed */ |
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i2c_int_disable(idev, ~MST_STATUS_TSS); |
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complete(&idev->msg_complete); |
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} else if (status & (MST_STATUS_SNS | MST_STATUS_SS)) { |
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/* Transfer done */ |
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int mask = idev->last ? ~0 : ~MST_STATUS_TSS; |
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i2c_int_disable(idev, mask); |
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if (i2c_m_rd(idev->msg_r) && idev->msg_xfrd_r < idev->msg_r->len) |
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axxia_i2c_empty_rx_fifo(idev); |
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complete(&idev->msg_complete); |
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} else if (status & MST_STATUS_TSS) { |
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/* Transfer timeout */ |
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idev->msg_err = -ETIMEDOUT; |
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i2c_int_disable(idev, ~MST_STATUS_TSS); |
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complete(&idev->msg_complete); |
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} |
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out: |
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/* Clear interrupt */ |
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writel(INT_MST, idev->base + INTERRUPT_STATUS); |
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return IRQ_HANDLED; |
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} |
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static void axxia_i2c_set_addr(struct axxia_i2c_dev *idev, struct i2c_msg *msg) |
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{ |
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u32 addr_1, addr_2; |
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if (i2c_m_ten(msg)) { |
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/* 10-bit address |
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* addr_1: 5'b11110 | addr[9:8] | (R/nW) |
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* addr_2: addr[7:0] |
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*/ |
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addr_1 = 0xF0 | ((msg->addr >> 7) & 0x06); |
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if (i2c_m_rd(msg)) |
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addr_1 |= 1; /* Set the R/nW bit of the address */ |
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addr_2 = msg->addr & 0xFF; |
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} else { |
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/* 7-bit address |
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* addr_1: addr[6:0] | (R/nW) |
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* addr_2: dont care |
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*/ |
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addr_1 = i2c_8bit_addr_from_msg(msg); |
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addr_2 = 0; |
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} |
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writel(addr_1, idev->base + MST_ADDR_1); |
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writel(addr_2, idev->base + MST_ADDR_2); |
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} |
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/* The NAK interrupt will be sent _before_ issuing STOP command |
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* so the controller might still be busy processing it. No |
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* interrupt will be sent at the end so we have to poll for it |
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*/ |
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static int axxia_i2c_handle_seq_nak(struct axxia_i2c_dev *idev) |
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{ |
|
unsigned long timeout = jiffies + I2C_XFER_TIMEOUT; |
|
|
|
do { |
|
if ((readl(idev->base + MST_COMMAND) & CMD_BUSY) == 0) |
|
return 0; |
|
usleep_range(1, 100); |
|
} while (time_before(jiffies, timeout)); |
|
|
|
return -ETIMEDOUT; |
|
} |
|
|
|
static int axxia_i2c_xfer_seq(struct axxia_i2c_dev *idev, struct i2c_msg msgs[]) |
|
{ |
|
u32 int_mask = MST_STATUS_ERR | MST_STATUS_SS | MST_STATUS_RFL; |
|
u32 rlen = i2c_m_recv_len(&msgs[1]) ? I2C_SMBUS_BLOCK_MAX : msgs[1].len; |
|
unsigned long time_left; |
|
|
|
axxia_i2c_set_addr(idev, &msgs[0]); |
|
|
|
writel(msgs[0].len, idev->base + MST_TX_XFER); |
|
writel(rlen, idev->base + MST_RX_XFER); |
|
|
|
idev->msg = &msgs[0]; |
|
idev->msg_r = &msgs[1]; |
|
idev->msg_xfrd = 0; |
|
idev->msg_xfrd_r = 0; |
|
idev->last = true; |
|
axxia_i2c_fill_tx_fifo(idev); |
|
|
|
writel(CMD_SEQUENCE, idev->base + MST_COMMAND); |
|
|
|
reinit_completion(&idev->msg_complete); |
|
i2c_int_enable(idev, int_mask); |
|
|
|
time_left = wait_for_completion_timeout(&idev->msg_complete, |
|
I2C_XFER_TIMEOUT); |
|
|
|
if (idev->msg_err == -ENXIO) { |
|
if (axxia_i2c_handle_seq_nak(idev)) |
|
axxia_i2c_init(idev); |
|
} else if (readl(idev->base + MST_COMMAND) & CMD_BUSY) { |
|
dev_warn(idev->dev, "busy after xfer\n"); |
|
} |
|
|
|
if (time_left == 0) { |
|
idev->msg_err = -ETIMEDOUT; |
|
i2c_recover_bus(&idev->adapter); |
|
axxia_i2c_init(idev); |
|
} |
|
|
|
if (unlikely(idev->msg_err) && idev->msg_err != -ENXIO) |
|
axxia_i2c_init(idev); |
|
|
|
return idev->msg_err; |
|
} |
|
|
|
static int axxia_i2c_xfer_msg(struct axxia_i2c_dev *idev, struct i2c_msg *msg, |
|
bool last) |
|
{ |
|
u32 int_mask = MST_STATUS_ERR; |
|
u32 rx_xfer, tx_xfer; |
|
unsigned long time_left; |
|
unsigned int wt_value; |
|
|
|
idev->msg = msg; |
|
idev->msg_r = msg; |
|
idev->msg_xfrd = 0; |
|
idev->msg_xfrd_r = 0; |
|
idev->last = last; |
|
reinit_completion(&idev->msg_complete); |
|
|
|
axxia_i2c_set_addr(idev, msg); |
|
|
|
if (i2c_m_rd(msg)) { |
|
/* I2C read transfer */ |
|
rx_xfer = i2c_m_recv_len(msg) ? I2C_SMBUS_BLOCK_MAX : msg->len; |
|
tx_xfer = 0; |
|
} else { |
|
/* I2C write transfer */ |
|
rx_xfer = 0; |
|
tx_xfer = msg->len; |
|
} |
|
|
|
writel(rx_xfer, idev->base + MST_RX_XFER); |
|
writel(tx_xfer, idev->base + MST_TX_XFER); |
|
|
|
if (i2c_m_rd(msg)) |
|
int_mask |= MST_STATUS_RFL; |
|
else if (axxia_i2c_fill_tx_fifo(idev) != 0) |
|
int_mask |= MST_STATUS_TFL; |
|
|
|
wt_value = WT_VALUE(readl(idev->base + WAIT_TIMER_CONTROL)); |
|
/* Disable wait timer temporarly */ |
|
writel(wt_value, idev->base + WAIT_TIMER_CONTROL); |
|
/* Check if timeout error happened */ |
|
if (idev->msg_err) |
|
goto out; |
|
|
|
if (!last) { |
|
writel(CMD_MANUAL, idev->base + MST_COMMAND); |
|
int_mask |= MST_STATUS_SNS; |
|
} else { |
|
writel(CMD_AUTO, idev->base + MST_COMMAND); |
|
int_mask |= MST_STATUS_SS; |
|
} |
|
|
|
writel(WT_EN | wt_value, idev->base + WAIT_TIMER_CONTROL); |
|
|
|
i2c_int_enable(idev, int_mask); |
|
|
|
time_left = wait_for_completion_timeout(&idev->msg_complete, |
|
I2C_XFER_TIMEOUT); |
|
|
|
i2c_int_disable(idev, int_mask); |
|
|
|
if (readl(idev->base + MST_COMMAND) & CMD_BUSY) |
|
dev_warn(idev->dev, "busy after xfer\n"); |
|
|
|
if (time_left == 0) { |
|
idev->msg_err = -ETIMEDOUT; |
|
i2c_recover_bus(&idev->adapter); |
|
axxia_i2c_init(idev); |
|
} |
|
|
|
out: |
|
if (unlikely(idev->msg_err) && idev->msg_err != -ENXIO && |
|
idev->msg_err != -ETIMEDOUT) |
|
axxia_i2c_init(idev); |
|
|
|
return idev->msg_err; |
|
} |
|
|
|
/* This function checks if the msgs[] array contains messages compatible with |
|
* Sequence mode of operation. This mode assumes there will be exactly one |
|
* write of non-zero length followed by exactly one read of non-zero length, |
|
* both targeted at the same client device. |
|
*/ |
|
static bool axxia_i2c_sequence_ok(struct i2c_msg msgs[], int num) |
|
{ |
|
return num == SEQ_LEN && !i2c_m_rd(&msgs[0]) && i2c_m_rd(&msgs[1]) && |
|
msgs[0].len > 0 && msgs[0].len <= FIFO_SIZE && |
|
msgs[1].len > 0 && msgs[0].addr == msgs[1].addr; |
|
} |
|
|
|
static int |
|
axxia_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num) |
|
{ |
|
struct axxia_i2c_dev *idev = i2c_get_adapdata(adap); |
|
int i; |
|
int ret = 0; |
|
|
|
idev->msg_err = 0; |
|
|
|
if (axxia_i2c_sequence_ok(msgs, num)) { |
|
ret = axxia_i2c_xfer_seq(idev, msgs); |
|
return ret ? : SEQ_LEN; |
|
} |
|
|
|
i2c_int_enable(idev, MST_STATUS_TSS); |
|
|
|
for (i = 0; ret == 0 && i < num; ++i) |
|
ret = axxia_i2c_xfer_msg(idev, &msgs[i], i == (num - 1)); |
|
|
|
return ret ? : i; |
|
} |
|
|
|
static int axxia_i2c_get_scl(struct i2c_adapter *adap) |
|
{ |
|
struct axxia_i2c_dev *idev = i2c_get_adapdata(adap); |
|
|
|
return !!(readl(idev->base + I2C_BUS_MONITOR) & BM_SCLS); |
|
} |
|
|
|
static void axxia_i2c_set_scl(struct i2c_adapter *adap, int val) |
|
{ |
|
struct axxia_i2c_dev *idev = i2c_get_adapdata(adap); |
|
u32 tmp; |
|
|
|
/* Preserve SDA Control */ |
|
tmp = readl(idev->base + I2C_BUS_MONITOR) & BM_SDAC; |
|
if (!val) |
|
tmp |= BM_SCLC; |
|
writel(tmp, idev->base + I2C_BUS_MONITOR); |
|
} |
|
|
|
static int axxia_i2c_get_sda(struct i2c_adapter *adap) |
|
{ |
|
struct axxia_i2c_dev *idev = i2c_get_adapdata(adap); |
|
|
|
return !!(readl(idev->base + I2C_BUS_MONITOR) & BM_SDAS); |
|
} |
|
|
|
static struct i2c_bus_recovery_info axxia_i2c_recovery_info = { |
|
.recover_bus = i2c_generic_scl_recovery, |
|
.get_scl = axxia_i2c_get_scl, |
|
.set_scl = axxia_i2c_set_scl, |
|
.get_sda = axxia_i2c_get_sda, |
|
}; |
|
|
|
static u32 axxia_i2c_func(struct i2c_adapter *adap) |
|
{ |
|
u32 caps = (I2C_FUNC_I2C | I2C_FUNC_10BIT_ADDR | |
|
I2C_FUNC_SMBUS_EMUL | I2C_FUNC_SMBUS_BLOCK_DATA); |
|
return caps; |
|
} |
|
|
|
static int axxia_i2c_reg_slave(struct i2c_client *slave) |
|
{ |
|
struct axxia_i2c_dev *idev = i2c_get_adapdata(slave->adapter); |
|
u32 slv_int_mask = SLV_STATUS_RFH; |
|
u32 dec_ctl; |
|
|
|
if (idev->slave) |
|
return -EBUSY; |
|
|
|
idev->slave = slave; |
|
|
|
/* Enable slave mode as well */ |
|
writel(GLOBAL_MST_EN | GLOBAL_SLV_EN, idev->base + GLOBAL_CONTROL); |
|
writel(INT_MST | INT_SLV, idev->base + INTERRUPT_ENABLE); |
|
|
|
/* Set slave address */ |
|
dec_ctl = SLV_ADDR_DEC_SA1E; |
|
if (slave->flags & I2C_CLIENT_TEN) |
|
dec_ctl |= SLV_ADDR_DEC_SA1M; |
|
|
|
writel(SLV_RX_ACSA1, idev->base + SLV_RX_CTL); |
|
writel(dec_ctl, idev->base + SLV_ADDR_DEC_CTL); |
|
writel(slave->addr, idev->base + SLV_ADDR_1); |
|
|
|
/* Enable interrupts */ |
|
slv_int_mask |= SLV_STATUS_SRS1 | SLV_STATUS_SRRS1 | SLV_STATUS_SRND1; |
|
slv_int_mask |= SLV_STATUS_SRC1; |
|
writel(slv_int_mask, idev->base + SLV_INT_ENABLE); |
|
|
|
return 0; |
|
} |
|
|
|
static int axxia_i2c_unreg_slave(struct i2c_client *slave) |
|
{ |
|
struct axxia_i2c_dev *idev = i2c_get_adapdata(slave->adapter); |
|
|
|
/* Disable slave mode */ |
|
writel(GLOBAL_MST_EN, idev->base + GLOBAL_CONTROL); |
|
writel(INT_MST, idev->base + INTERRUPT_ENABLE); |
|
|
|
synchronize_irq(idev->irq); |
|
|
|
idev->slave = NULL; |
|
|
|
return 0; |
|
} |
|
|
|
static const struct i2c_algorithm axxia_i2c_algo = { |
|
.master_xfer = axxia_i2c_xfer, |
|
.functionality = axxia_i2c_func, |
|
.reg_slave = axxia_i2c_reg_slave, |
|
.unreg_slave = axxia_i2c_unreg_slave, |
|
}; |
|
|
|
static const struct i2c_adapter_quirks axxia_i2c_quirks = { |
|
.max_read_len = 255, |
|
.max_write_len = 255, |
|
}; |
|
|
|
static int axxia_i2c_probe(struct platform_device *pdev) |
|
{ |
|
struct device_node *np = pdev->dev.of_node; |
|
struct axxia_i2c_dev *idev = NULL; |
|
void __iomem *base; |
|
int ret = 0; |
|
|
|
idev = devm_kzalloc(&pdev->dev, sizeof(*idev), GFP_KERNEL); |
|
if (!idev) |
|
return -ENOMEM; |
|
|
|
base = devm_platform_ioremap_resource(pdev, 0); |
|
if (IS_ERR(base)) |
|
return PTR_ERR(base); |
|
|
|
idev->irq = platform_get_irq(pdev, 0); |
|
if (idev->irq < 0) |
|
return idev->irq; |
|
|
|
idev->i2c_clk = devm_clk_get(&pdev->dev, "i2c"); |
|
if (IS_ERR(idev->i2c_clk)) { |
|
dev_err(&pdev->dev, "missing clock\n"); |
|
return PTR_ERR(idev->i2c_clk); |
|
} |
|
|
|
idev->base = base; |
|
idev->dev = &pdev->dev; |
|
init_completion(&idev->msg_complete); |
|
|
|
of_property_read_u32(np, "clock-frequency", &idev->bus_clk_rate); |
|
if (idev->bus_clk_rate == 0) |
|
idev->bus_clk_rate = I2C_MAX_STANDARD_MODE_FREQ; /* default clock rate */ |
|
|
|
ret = clk_prepare_enable(idev->i2c_clk); |
|
if (ret) { |
|
dev_err(&pdev->dev, "failed to enable clock\n"); |
|
return ret; |
|
} |
|
|
|
ret = axxia_i2c_init(idev); |
|
if (ret) { |
|
dev_err(&pdev->dev, "failed to initialize\n"); |
|
goto error_disable_clk; |
|
} |
|
|
|
ret = devm_request_irq(&pdev->dev, idev->irq, axxia_i2c_isr, 0, |
|
pdev->name, idev); |
|
if (ret) { |
|
dev_err(&pdev->dev, "failed to claim IRQ%d\n", idev->irq); |
|
goto error_disable_clk; |
|
} |
|
|
|
i2c_set_adapdata(&idev->adapter, idev); |
|
strlcpy(idev->adapter.name, pdev->name, sizeof(idev->adapter.name)); |
|
idev->adapter.owner = THIS_MODULE; |
|
idev->adapter.algo = &axxia_i2c_algo; |
|
idev->adapter.bus_recovery_info = &axxia_i2c_recovery_info; |
|
idev->adapter.quirks = &axxia_i2c_quirks; |
|
idev->adapter.dev.parent = &pdev->dev; |
|
idev->adapter.dev.of_node = pdev->dev.of_node; |
|
|
|
platform_set_drvdata(pdev, idev); |
|
|
|
ret = i2c_add_adapter(&idev->adapter); |
|
if (ret) |
|
goto error_disable_clk; |
|
|
|
return 0; |
|
|
|
error_disable_clk: |
|
clk_disable_unprepare(idev->i2c_clk); |
|
return ret; |
|
} |
|
|
|
static int axxia_i2c_remove(struct platform_device *pdev) |
|
{ |
|
struct axxia_i2c_dev *idev = platform_get_drvdata(pdev); |
|
|
|
clk_disable_unprepare(idev->i2c_clk); |
|
i2c_del_adapter(&idev->adapter); |
|
|
|
return 0; |
|
} |
|
|
|
/* Match table for of_platform binding */ |
|
static const struct of_device_id axxia_i2c_of_match[] = { |
|
{ .compatible = "lsi,api2c", }, |
|
{}, |
|
}; |
|
|
|
MODULE_DEVICE_TABLE(of, axxia_i2c_of_match); |
|
|
|
static struct platform_driver axxia_i2c_driver = { |
|
.probe = axxia_i2c_probe, |
|
.remove = axxia_i2c_remove, |
|
.driver = { |
|
.name = "axxia-i2c", |
|
.of_match_table = axxia_i2c_of_match, |
|
}, |
|
}; |
|
|
|
module_platform_driver(axxia_i2c_driver); |
|
|
|
MODULE_DESCRIPTION("Axxia I2C Bus driver"); |
|
MODULE_AUTHOR("Anders Berg <[email protected]>"); |
|
MODULE_LICENSE("GPL v2");
|
|
|