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191 lines
6.7 KiB
191 lines
6.7 KiB
/* SPDX-License-Identifier: GPL-2.0 */ |
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/* |
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* i2c Support for Atmel's AT91 Two-Wire Interface (TWI) |
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* |
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* Copyright (C) 2011 Weinmann Medical GmbH |
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* Author: Nikolaus Voss <[email protected]> |
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* |
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* Evolved from original work by: |
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* Copyright (C) 2004 Rick Bronson |
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* Converted to 2.6 by Andrew Victor <[email protected]> |
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* |
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* Borrowed heavily from original work by: |
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* Copyright (C) 2000 Philip Edelbrock <[email protected]> |
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*/ |
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#include <linux/clk.h> |
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#include <linux/completion.h> |
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#include <linux/dma-mapping.h> |
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#include <linux/dmaengine.h> |
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#include <linux/i2c.h> |
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#include <linux/platform_device.h> |
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#define AT91_I2C_TIMEOUT msecs_to_jiffies(100) /* transfer timeout */ |
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#define AT91_I2C_DMA_THRESHOLD 8 /* enable DMA if transfer size is bigger than this threshold */ |
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#define AUTOSUSPEND_TIMEOUT 2000 |
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#define AT91_I2C_MAX_ALT_CMD_DATA_SIZE 256 |
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/* AT91 TWI register definitions */ |
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#define AT91_TWI_CR 0x0000 /* Control Register */ |
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#define AT91_TWI_START BIT(0) /* Send a Start Condition */ |
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#define AT91_TWI_STOP BIT(1) /* Send a Stop Condition */ |
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#define AT91_TWI_MSEN BIT(2) /* Master Transfer Enable */ |
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#define AT91_TWI_MSDIS BIT(3) /* Master Transfer Disable */ |
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#define AT91_TWI_SVEN BIT(4) /* Slave Transfer Enable */ |
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#define AT91_TWI_SVDIS BIT(5) /* Slave Transfer Disable */ |
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#define AT91_TWI_QUICK BIT(6) /* SMBus quick command */ |
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#define AT91_TWI_SWRST BIT(7) /* Software Reset */ |
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#define AT91_TWI_CLEAR BIT(15) /* Bus clear command */ |
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#define AT91_TWI_ACMEN BIT(16) /* Alternative Command Mode Enable */ |
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#define AT91_TWI_ACMDIS BIT(17) /* Alternative Command Mode Disable */ |
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#define AT91_TWI_THRCLR BIT(24) /* Transmit Holding Register Clear */ |
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#define AT91_TWI_RHRCLR BIT(25) /* Receive Holding Register Clear */ |
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#define AT91_TWI_LOCKCLR BIT(26) /* Lock Clear */ |
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#define AT91_TWI_FIFOEN BIT(28) /* FIFO Enable */ |
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#define AT91_TWI_FIFODIS BIT(29) /* FIFO Disable */ |
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#define AT91_TWI_MMR 0x0004 /* Master Mode Register */ |
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#define AT91_TWI_IADRSZ_1 0x0100 /* Internal Device Address Size */ |
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#define AT91_TWI_MREAD BIT(12) /* Master Read Direction */ |
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#define AT91_TWI_SMR 0x0008 /* Slave Mode Register */ |
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#define AT91_TWI_SMR_SADR_MAX 0x007f |
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#define AT91_TWI_SMR_SADR(x) (((x) & AT91_TWI_SMR_SADR_MAX) << 16) |
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#define AT91_TWI_IADR 0x000c /* Internal Address Register */ |
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#define AT91_TWI_CWGR 0x0010 /* Clock Waveform Generator Reg */ |
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#define AT91_TWI_CWGR_HOLD_MAX 0x1f |
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#define AT91_TWI_CWGR_HOLD(x) (((x) & AT91_TWI_CWGR_HOLD_MAX) << 24) |
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#define AT91_TWI_SR 0x0020 /* Status Register */ |
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#define AT91_TWI_TXCOMP BIT(0) /* Transmission Complete */ |
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#define AT91_TWI_RXRDY BIT(1) /* Receive Holding Register Ready */ |
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#define AT91_TWI_TXRDY BIT(2) /* Transmit Holding Register Ready */ |
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#define AT91_TWI_SVREAD BIT(3) /* Slave Read */ |
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#define AT91_TWI_SVACC BIT(4) /* Slave Access */ |
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#define AT91_TWI_OVRE BIT(6) /* Overrun Error */ |
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#define AT91_TWI_UNRE BIT(7) /* Underrun Error */ |
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#define AT91_TWI_NACK BIT(8) /* Not Acknowledged */ |
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#define AT91_TWI_EOSACC BIT(11) /* End Of Slave Access */ |
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#define AT91_TWI_LOCK BIT(23) /* TWI Lock due to Frame Errors */ |
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#define AT91_TWI_SCL BIT(24) /* TWI SCL status */ |
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#define AT91_TWI_SDA BIT(25) /* TWI SDA status */ |
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#define AT91_TWI_INT_MASK \ |
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(AT91_TWI_TXCOMP | AT91_TWI_RXRDY | AT91_TWI_TXRDY | AT91_TWI_NACK \ |
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| AT91_TWI_SVACC | AT91_TWI_EOSACC) |
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#define AT91_TWI_IER 0x0024 /* Interrupt Enable Register */ |
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#define AT91_TWI_IDR 0x0028 /* Interrupt Disable Register */ |
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#define AT91_TWI_IMR 0x002c /* Interrupt Mask Register */ |
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#define AT91_TWI_RHR 0x0030 /* Receive Holding Register */ |
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#define AT91_TWI_THR 0x0034 /* Transmit Holding Register */ |
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#define AT91_TWI_ACR 0x0040 /* Alternative Command Register */ |
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#define AT91_TWI_ACR_DATAL_MASK GENMASK(15, 0) |
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#define AT91_TWI_ACR_DATAL(len) ((len) & AT91_TWI_ACR_DATAL_MASK) |
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#define AT91_TWI_ACR_DIR BIT(8) |
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#define AT91_TWI_FILTR 0x0044 |
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#define AT91_TWI_FILTR_FILT BIT(0) |
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#define AT91_TWI_FILTR_PADFEN BIT(1) |
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#define AT91_TWI_FILTR_THRES(v) ((v) << 8) |
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#define AT91_TWI_FILTR_THRES_MAX 7 |
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#define AT91_TWI_FILTR_THRES_MASK GENMASK(10, 8) |
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#define AT91_TWI_FMR 0x0050 /* FIFO Mode Register */ |
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#define AT91_TWI_FMR_TXRDYM(mode) (((mode) & 0x3) << 0) |
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#define AT91_TWI_FMR_TXRDYM_MASK (0x3 << 0) |
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#define AT91_TWI_FMR_RXRDYM(mode) (((mode) & 0x3) << 4) |
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#define AT91_TWI_FMR_RXRDYM_MASK (0x3 << 4) |
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#define AT91_TWI_ONE_DATA 0x0 |
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#define AT91_TWI_TWO_DATA 0x1 |
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#define AT91_TWI_FOUR_DATA 0x2 |
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#define AT91_TWI_FLR 0x0054 /* FIFO Level Register */ |
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#define AT91_TWI_FSR 0x0060 /* FIFO Status Register */ |
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#define AT91_TWI_FIER 0x0064 /* FIFO Interrupt Enable Register */ |
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#define AT91_TWI_FIDR 0x0068 /* FIFO Interrupt Disable Register */ |
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#define AT91_TWI_FIMR 0x006c /* FIFO Interrupt Mask Register */ |
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#define AT91_TWI_VER 0x00fc /* Version Register */ |
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struct at91_twi_pdata { |
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unsigned clk_max_div; |
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unsigned clk_offset; |
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bool has_unre_flag; |
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bool has_alt_cmd; |
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bool has_hold_field; |
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bool has_dig_filtr; |
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bool has_adv_dig_filtr; |
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bool has_ana_filtr; |
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bool has_clear_cmd; |
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}; |
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struct at91_twi_dma { |
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struct dma_chan *chan_rx; |
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struct dma_chan *chan_tx; |
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struct scatterlist sg[2]; |
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struct dma_async_tx_descriptor *data_desc; |
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enum dma_data_direction direction; |
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bool buf_mapped; |
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bool xfer_in_progress; |
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}; |
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struct at91_twi_dev { |
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struct device *dev; |
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void __iomem *base; |
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struct completion cmd_complete; |
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struct clk *clk; |
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u8 *buf; |
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size_t buf_len; |
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struct i2c_msg *msg; |
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int irq; |
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unsigned imr; |
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unsigned transfer_status; |
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struct i2c_adapter adapter; |
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unsigned twi_cwgr_reg; |
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struct at91_twi_pdata *pdata; |
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bool use_dma; |
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bool use_alt_cmd; |
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bool recv_len_abort; |
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u32 fifo_size; |
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struct at91_twi_dma dma; |
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bool slave_detected; |
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struct i2c_bus_recovery_info rinfo; |
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#ifdef CONFIG_I2C_AT91_SLAVE_EXPERIMENTAL |
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unsigned smr; |
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struct i2c_client *slave; |
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#endif |
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bool enable_dig_filt; |
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bool enable_ana_filt; |
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u32 filter_width; |
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}; |
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unsigned at91_twi_read(struct at91_twi_dev *dev, unsigned reg); |
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void at91_twi_write(struct at91_twi_dev *dev, unsigned reg, unsigned val); |
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void at91_disable_twi_interrupts(struct at91_twi_dev *dev); |
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void at91_twi_irq_save(struct at91_twi_dev *dev); |
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void at91_twi_irq_restore(struct at91_twi_dev *dev); |
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void at91_init_twi_bus(struct at91_twi_dev *dev); |
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void at91_init_twi_bus_master(struct at91_twi_dev *dev); |
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int at91_twi_probe_master(struct platform_device *pdev, u32 phy_addr, |
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struct at91_twi_dev *dev); |
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#ifdef CONFIG_I2C_AT91_SLAVE_EXPERIMENTAL |
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void at91_init_twi_bus_slave(struct at91_twi_dev *dev); |
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int at91_twi_probe_slave(struct platform_device *pdev, u32 phy_addr, |
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struct at91_twi_dev *dev); |
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#else |
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static inline void at91_init_twi_bus_slave(struct at91_twi_dev *dev) {} |
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static inline int at91_twi_probe_slave(struct platform_device *pdev, |
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u32 phy_addr, struct at91_twi_dev *dev) |
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{ |
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return -EINVAL; |
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} |
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#endif
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