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182 lines
6.0 KiB
182 lines
6.0 KiB
// SPDX-License-Identifier: GPL-2.0 |
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/* |
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* Copyright(C) 2020 Linaro Limited. All rights reserved. |
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* Author: Mike Leach <[email protected]> |
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*/ |
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#include "coresight-etm4x.h" |
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#include "coresight-etm4x-cfg.h" |
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#include "coresight-priv.h" |
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#include "coresight-syscfg.h" |
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/* defines to associate register IDs with driver data locations */ |
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#define CHECKREG(cval, elem) \ |
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{ \ |
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if (offset == cval) { \ |
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reg_csdev->driver_regval = &drvcfg->elem; \ |
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err = 0; \ |
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break; \ |
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} \ |
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} |
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#define CHECKREGIDX(cval, elem, off_idx, mask) \ |
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{ \ |
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if (mask == cval) { \ |
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reg_csdev->driver_regval = &drvcfg->elem[off_idx]; \ |
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err = 0; \ |
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break; \ |
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} \ |
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} |
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/** |
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* etm4_cfg_map_reg_offset - validate and map the register offset into a |
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* location in the driver config struct. |
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* |
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* Limits the number of registers that can be accessed and programmed in |
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* features, to those which are used to control the trace capture parameters. |
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* |
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* Omits or limits access to those which the driver must use exclusively. |
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* |
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* Invalid offsets will result in fail code return and feature load failure. |
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* |
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* @drvdata: driver data to map into. |
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* @reg: register to map. |
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* @offset: device offset for the register |
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*/ |
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static int etm4_cfg_map_reg_offset(struct etmv4_drvdata *drvdata, |
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struct cscfg_regval_csdev *reg_csdev, u32 offset) |
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{ |
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int err = -EINVAL, idx; |
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struct etmv4_config *drvcfg = &drvdata->config; |
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u32 off_mask; |
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if (((offset >= TRCEVENTCTL0R) && (offset <= TRCVIPCSSCTLR)) || |
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((offset >= TRCSEQRSTEVR) && (offset <= TRCEXTINSELR)) || |
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((offset >= TRCCIDCCTLR0) && (offset <= TRCVMIDCCTLR1))) { |
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do { |
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CHECKREG(TRCEVENTCTL0R, eventctrl0); |
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CHECKREG(TRCEVENTCTL1R, eventctrl1); |
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CHECKREG(TRCSTALLCTLR, stall_ctrl); |
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CHECKREG(TRCTSCTLR, ts_ctrl); |
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CHECKREG(TRCSYNCPR, syncfreq); |
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CHECKREG(TRCCCCTLR, ccctlr); |
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CHECKREG(TRCBBCTLR, bb_ctrl); |
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CHECKREG(TRCVICTLR, vinst_ctrl); |
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CHECKREG(TRCVIIECTLR, viiectlr); |
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CHECKREG(TRCVISSCTLR, vissctlr); |
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CHECKREG(TRCVIPCSSCTLR, vipcssctlr); |
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CHECKREG(TRCSEQRSTEVR, seq_rst); |
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CHECKREG(TRCSEQSTR, seq_state); |
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CHECKREG(TRCEXTINSELR, ext_inp); |
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CHECKREG(TRCCIDCCTLR0, ctxid_mask0); |
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CHECKREG(TRCCIDCCTLR1, ctxid_mask1); |
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CHECKREG(TRCVMIDCCTLR0, vmid_mask0); |
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CHECKREG(TRCVMIDCCTLR1, vmid_mask1); |
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} while (0); |
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} else if ((offset & GENMASK(11, 4)) == TRCSEQEVRn(0)) { |
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/* sequencer state control registers */ |
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idx = (offset & GENMASK(3, 0)) / 4; |
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if (idx < ETM_MAX_SEQ_STATES) { |
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reg_csdev->driver_regval = &drvcfg->seq_ctrl[idx]; |
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err = 0; |
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} |
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} else if ((offset >= TRCSSCCRn(0)) && (offset <= TRCSSPCICRn(7))) { |
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/* 32 bit, 8 off indexed register sets */ |
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idx = (offset & GENMASK(4, 0)) / 4; |
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off_mask = (offset & GENMASK(11, 5)); |
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do { |
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CHECKREGIDX(TRCSSCCRn(0), ss_ctrl, idx, off_mask); |
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CHECKREGIDX(TRCSSCSRn(0), ss_status, idx, off_mask); |
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CHECKREGIDX(TRCSSPCICRn(0), ss_pe_cmp, idx, off_mask); |
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} while (0); |
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} else if ((offset >= TRCCIDCVRn(0)) && (offset <= TRCVMIDCVRn(7))) { |
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/* 64 bit, 8 off indexed register sets */ |
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idx = (offset & GENMASK(5, 0)) / 8; |
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off_mask = (offset & GENMASK(11, 6)); |
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do { |
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CHECKREGIDX(TRCCIDCVRn(0), ctxid_pid, idx, off_mask); |
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CHECKREGIDX(TRCVMIDCVRn(0), vmid_val, idx, off_mask); |
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} while (0); |
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} else if ((offset >= TRCRSCTLRn(2)) && |
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(offset <= TRCRSCTLRn((ETM_MAX_RES_SEL - 1)))) { |
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/* 32 bit resource selection regs, 32 off, skip fixed 0,1 */ |
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idx = (offset & GENMASK(6, 0)) / 4; |
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if (idx < ETM_MAX_RES_SEL) { |
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reg_csdev->driver_regval = &drvcfg->res_ctrl[idx]; |
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err = 0; |
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} |
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} else if ((offset >= TRCACVRn(0)) && |
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(offset <= TRCACATRn((ETM_MAX_SINGLE_ADDR_CMP - 1)))) { |
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/* 64 bit addr cmp regs, 16 off */ |
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idx = (offset & GENMASK(6, 0)) / 8; |
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off_mask = offset & GENMASK(11, 7); |
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do { |
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CHECKREGIDX(TRCACVRn(0), addr_val, idx, off_mask); |
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CHECKREGIDX(TRCACATRn(0), addr_acc, idx, off_mask); |
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} while (0); |
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} else if ((offset >= TRCCNTRLDVRn(0)) && |
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(offset <= TRCCNTVRn((ETMv4_MAX_CNTR - 1)))) { |
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/* 32 bit counter regs, 4 off (ETMv4_MAX_CNTR - 1) */ |
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idx = (offset & GENMASK(3, 0)) / 4; |
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off_mask = offset & GENMASK(11, 4); |
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do { |
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CHECKREGIDX(TRCCNTRLDVRn(0), cntrldvr, idx, off_mask); |
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CHECKREGIDX(TRCCNTCTLRn(0), cntr_ctrl, idx, off_mask); |
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CHECKREGIDX(TRCCNTVRn(0), cntr_val, idx, off_mask); |
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} while (0); |
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} |
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return err; |
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} |
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/** |
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* etm4_cfg_load_feature - load a feature into a device instance. |
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* |
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* @csdev: An ETMv4 CoreSight device. |
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* @feat: The feature to be loaded. |
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* |
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* The function will load a feature instance into the device, checking that |
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* the register definitions are valid for the device. |
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* |
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* Parameter and register definitions will be converted into internal |
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* structures that are used to set the values in the driver when the |
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* feature is enabled for the device. |
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* |
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* The feature spinlock pointer is initialised to the same spinlock |
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* that the driver uses to protect the internal register values. |
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*/ |
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static int etm4_cfg_load_feature(struct coresight_device *csdev, |
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struct cscfg_feature_csdev *feat_csdev) |
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{ |
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struct device *dev = csdev->dev.parent; |
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struct etmv4_drvdata *drvdata = dev_get_drvdata(dev); |
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const struct cscfg_feature_desc *feat_desc = feat_csdev->feat_desc; |
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u32 offset; |
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int i = 0, err = 0; |
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/* |
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* essential we set the device spinlock - this is used in the generic |
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* programming routines when copying values into the drvdata structures |
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* via the pointers setup in etm4_cfg_map_reg_offset(). |
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*/ |
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feat_csdev->drv_spinlock = &drvdata->spinlock; |
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/* process the register descriptions */ |
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for (i = 0; i < feat_csdev->nr_regs && !err; i++) { |
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offset = feat_desc->regs_desc[i].offset; |
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err = etm4_cfg_map_reg_offset(drvdata, &feat_csdev->regs_csdev[i], offset); |
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} |
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return err; |
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} |
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/* match information when loading configurations */ |
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#define CS_CFG_ETM4_MATCH_FLAGS (CS_CFG_MATCH_CLASS_SRC_ALL | \ |
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CS_CFG_MATCH_CLASS_SRC_ETM4) |
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int etm4_cscfg_register(struct coresight_device *csdev) |
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{ |
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struct cscfg_csdev_feat_ops ops; |
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ops.load_feat = &etm4_cfg_load_feature; |
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return cscfg_register_csdev(csdev, CS_CFG_ETM4_MATCH_FLAGS, &ops); |
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}
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