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157 lines
3.9 KiB
157 lines
3.9 KiB
// SPDX-License-Identifier: GPL-2.0 |
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/* |
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* u8500 HWSEM driver |
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* |
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* Copyright (C) 2010-2011 ST-Ericsson |
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* |
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* Implements u8500 semaphore handling for protocol 1, no interrupts. |
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* |
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* Author: Mathieu Poirier <[email protected]> |
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* Heavily borrowed from the work of : |
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* Simon Que <[email protected]> |
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* Hari Kanigeri <[email protected]> |
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* Ohad Ben-Cohen <[email protected]> |
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*/ |
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#include <linux/module.h> |
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#include <linux/delay.h> |
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#include <linux/io.h> |
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#include <linux/slab.h> |
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#include <linux/spinlock.h> |
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#include <linux/hwspinlock.h> |
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#include <linux/platform_device.h> |
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#include "hwspinlock_internal.h" |
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/* |
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* Implementation of STE's HSem protocol 1 without interrutps. |
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* The only masterID we allow is '0x01' to force people to use |
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* HSems for synchronisation between processors rather than processes |
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* on the ARM core. |
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*/ |
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#define U8500_MAX_SEMAPHORE 32 /* a total of 32 semaphore */ |
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#define RESET_SEMAPHORE (0) /* free */ |
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/* |
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* CPU ID for master running u8500 kernel. |
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* Hswpinlocks should only be used to synchonise operations |
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* between the Cortex A9 core and the other CPUs. Hence |
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* forcing the masterID to a preset value. |
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*/ |
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#define HSEM_MASTER_ID 0x01 |
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#define HSEM_REGISTER_OFFSET 0x08 |
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#define HSEM_CTRL_REG 0x00 |
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#define HSEM_ICRALL 0x90 |
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#define HSEM_PROTOCOL_1 0x01 |
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static int u8500_hsem_trylock(struct hwspinlock *lock) |
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{ |
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void __iomem *lock_addr = lock->priv; |
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writel(HSEM_MASTER_ID, lock_addr); |
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/* get only first 4 bit and compare to masterID. |
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* if equal, we have the semaphore, otherwise |
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* someone else has it. |
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*/ |
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return (HSEM_MASTER_ID == (0x0F & readl(lock_addr))); |
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} |
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static void u8500_hsem_unlock(struct hwspinlock *lock) |
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{ |
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void __iomem *lock_addr = lock->priv; |
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/* release the lock by writing 0 to it */ |
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writel(RESET_SEMAPHORE, lock_addr); |
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} |
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/* |
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* u8500: what value is recommended here ? |
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*/ |
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static void u8500_hsem_relax(struct hwspinlock *lock) |
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{ |
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ndelay(50); |
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} |
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static const struct hwspinlock_ops u8500_hwspinlock_ops = { |
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.trylock = u8500_hsem_trylock, |
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.unlock = u8500_hsem_unlock, |
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.relax = u8500_hsem_relax, |
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}; |
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static int u8500_hsem_probe(struct platform_device *pdev) |
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{ |
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struct hwspinlock_pdata *pdata = pdev->dev.platform_data; |
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struct hwspinlock_device *bank; |
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struct hwspinlock *hwlock; |
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void __iomem *io_base; |
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int i, num_locks = U8500_MAX_SEMAPHORE; |
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ulong val; |
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if (!pdata) |
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return -ENODEV; |
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io_base = devm_platform_ioremap_resource(pdev, 0); |
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if (IS_ERR(io_base)) |
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return PTR_ERR(io_base); |
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/* make sure protocol 1 is selected */ |
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val = readl(io_base + HSEM_CTRL_REG); |
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writel((val & ~HSEM_PROTOCOL_1), io_base + HSEM_CTRL_REG); |
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/* clear all interrupts */ |
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writel(0xFFFF, io_base + HSEM_ICRALL); |
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bank = devm_kzalloc(&pdev->dev, struct_size(bank, lock, num_locks), |
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GFP_KERNEL); |
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if (!bank) |
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return -ENOMEM; |
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platform_set_drvdata(pdev, bank); |
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for (i = 0, hwlock = &bank->lock[0]; i < num_locks; i++, hwlock++) |
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hwlock->priv = io_base + HSEM_REGISTER_OFFSET + sizeof(u32) * i; |
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return devm_hwspin_lock_register(&pdev->dev, bank, |
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&u8500_hwspinlock_ops, |
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pdata->base_id, num_locks); |
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} |
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static int u8500_hsem_remove(struct platform_device *pdev) |
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{ |
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struct hwspinlock_device *bank = platform_get_drvdata(pdev); |
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void __iomem *io_base = bank->lock[0].priv - HSEM_REGISTER_OFFSET; |
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/* clear all interrupts */ |
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writel(0xFFFF, io_base + HSEM_ICRALL); |
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return 0; |
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} |
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static struct platform_driver u8500_hsem_driver = { |
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.probe = u8500_hsem_probe, |
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.remove = u8500_hsem_remove, |
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.driver = { |
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.name = "u8500_hsem", |
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}, |
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}; |
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static int __init u8500_hsem_init(void) |
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{ |
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return platform_driver_register(&u8500_hsem_driver); |
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} |
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/* board init code might need to reserve hwspinlocks for predefined purposes */ |
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postcore_initcall(u8500_hsem_init); |
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static void __exit u8500_hsem_exit(void) |
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{ |
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platform_driver_unregister(&u8500_hsem_driver); |
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} |
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module_exit(u8500_hsem_exit); |
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MODULE_LICENSE("GPL v2"); |
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MODULE_DESCRIPTION("Hardware Spinlock driver for u8500"); |
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MODULE_AUTHOR("Mathieu Poirier <[email protected]>");
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