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425 lines
11 KiB
425 lines
11 KiB
// SPDX-License-Identifier: GPL-2.0-or-later |
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/* |
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* Copyright (c) 2010 Sascha Hauer <[email protected]> |
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* Copyright (C) 2005-2009 Freescale Semiconductor, Inc. |
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*/ |
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#include <linux/export.h> |
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#include <linux/module.h> |
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#include <linux/types.h> |
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#include <linux/errno.h> |
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#include <linux/delay.h> |
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#include <linux/interrupt.h> |
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#include <linux/io.h> |
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#include <video/imx-ipu-v3.h> |
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#include "ipu-prv.h" |
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#define DC_MAP_CONF_PTR(n) (0x108 + ((n) & ~0x1) * 2) |
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#define DC_MAP_CONF_VAL(n) (0x144 + ((n) & ~0x1) * 2) |
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#define DC_EVT_NF 0 |
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#define DC_EVT_NL 1 |
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#define DC_EVT_EOF 2 |
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#define DC_EVT_NFIELD 3 |
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#define DC_EVT_EOL 4 |
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#define DC_EVT_EOFIELD 5 |
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#define DC_EVT_NEW_ADDR 6 |
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#define DC_EVT_NEW_CHAN 7 |
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#define DC_EVT_NEW_DATA 8 |
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#define DC_EVT_NEW_ADDR_W_0 0 |
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#define DC_EVT_NEW_ADDR_W_1 1 |
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#define DC_EVT_NEW_CHAN_W_0 2 |
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#define DC_EVT_NEW_CHAN_W_1 3 |
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#define DC_EVT_NEW_DATA_W_0 4 |
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#define DC_EVT_NEW_DATA_W_1 5 |
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#define DC_EVT_NEW_ADDR_R_0 6 |
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#define DC_EVT_NEW_ADDR_R_1 7 |
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#define DC_EVT_NEW_CHAN_R_0 8 |
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#define DC_EVT_NEW_CHAN_R_1 9 |
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#define DC_EVT_NEW_DATA_R_0 10 |
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#define DC_EVT_NEW_DATA_R_1 11 |
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#define DC_WR_CH_CONF 0x0 |
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#define DC_WR_CH_ADDR 0x4 |
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#define DC_RL_CH(evt) (8 + ((evt) & ~0x1) * 2) |
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#define DC_GEN 0xd4 |
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#define DC_DISP_CONF1(disp) (0xd8 + (disp) * 4) |
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#define DC_DISP_CONF2(disp) (0xe8 + (disp) * 4) |
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#define DC_STAT 0x1c8 |
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#define WROD(lf) (0x18 | ((lf) << 1)) |
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#define WRG 0x01 |
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#define WCLK 0xc9 |
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#define SYNC_WAVE 0 |
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#define NULL_WAVE (-1) |
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#define DC_GEN_SYNC_1_6_SYNC (2 << 1) |
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#define DC_GEN_SYNC_PRIORITY_1 (1 << 7) |
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#define DC_WR_CH_CONF_WORD_SIZE_8 (0 << 0) |
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#define DC_WR_CH_CONF_WORD_SIZE_16 (1 << 0) |
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#define DC_WR_CH_CONF_WORD_SIZE_24 (2 << 0) |
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#define DC_WR_CH_CONF_WORD_SIZE_32 (3 << 0) |
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#define DC_WR_CH_CONF_DISP_ID_PARALLEL(i) (((i) & 0x1) << 3) |
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#define DC_WR_CH_CONF_DISP_ID_SERIAL (2 << 3) |
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#define DC_WR_CH_CONF_DISP_ID_ASYNC (3 << 4) |
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#define DC_WR_CH_CONF_FIELD_MODE (1 << 9) |
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#define DC_WR_CH_CONF_PROG_TYPE_NORMAL (4 << 5) |
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#define DC_WR_CH_CONF_PROG_TYPE_MASK (7 << 5) |
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#define DC_WR_CH_CONF_PROG_DI_ID (1 << 2) |
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#define DC_WR_CH_CONF_PROG_DISP_ID(i) (((i) & 0x1) << 3) |
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#define IPU_DC_NUM_CHANNELS 10 |
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struct ipu_dc_priv; |
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enum ipu_dc_map { |
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IPU_DC_MAP_RGB24, |
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IPU_DC_MAP_RGB565, |
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IPU_DC_MAP_GBR24, /* TVEv2 */ |
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IPU_DC_MAP_BGR666, |
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IPU_DC_MAP_LVDS666, |
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IPU_DC_MAP_BGR24, |
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}; |
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struct ipu_dc { |
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/* The display interface number assigned to this dc channel */ |
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unsigned int di; |
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void __iomem *base; |
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struct ipu_dc_priv *priv; |
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int chno; |
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bool in_use; |
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}; |
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struct ipu_dc_priv { |
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void __iomem *dc_reg; |
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void __iomem *dc_tmpl_reg; |
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struct ipu_soc *ipu; |
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struct device *dev; |
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struct ipu_dc channels[IPU_DC_NUM_CHANNELS]; |
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struct mutex mutex; |
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struct completion comp; |
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int use_count; |
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}; |
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static void dc_link_event(struct ipu_dc *dc, int event, int addr, int priority) |
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{ |
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u32 reg; |
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reg = readl(dc->base + DC_RL_CH(event)); |
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reg &= ~(0xffff << (16 * (event & 0x1))); |
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reg |= ((addr << 8) | priority) << (16 * (event & 0x1)); |
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writel(reg, dc->base + DC_RL_CH(event)); |
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} |
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static void dc_write_tmpl(struct ipu_dc *dc, int word, u32 opcode, u32 operand, |
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int map, int wave, int glue, int sync, int stop) |
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{ |
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struct ipu_dc_priv *priv = dc->priv; |
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u32 reg1, reg2; |
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if (opcode == WCLK) { |
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reg1 = (operand << 20) & 0xfff00000; |
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reg2 = operand >> 12 | opcode << 1 | stop << 9; |
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} else if (opcode == WRG) { |
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reg1 = sync | glue << 4 | ++wave << 11 | ((operand << 15) & 0xffff8000); |
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reg2 = operand >> 17 | opcode << 7 | stop << 9; |
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} else { |
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reg1 = sync | glue << 4 | ++wave << 11 | ++map << 15 | ((operand << 20) & 0xfff00000); |
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reg2 = operand >> 12 | opcode << 4 | stop << 9; |
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} |
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writel(reg1, priv->dc_tmpl_reg + word * 8); |
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writel(reg2, priv->dc_tmpl_reg + word * 8 + 4); |
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} |
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static int ipu_bus_format_to_map(u32 fmt) |
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{ |
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switch (fmt) { |
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default: |
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WARN_ON(1); |
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fallthrough; |
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case MEDIA_BUS_FMT_RGB888_1X24: |
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return IPU_DC_MAP_RGB24; |
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case MEDIA_BUS_FMT_RGB565_1X16: |
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return IPU_DC_MAP_RGB565; |
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case MEDIA_BUS_FMT_GBR888_1X24: |
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return IPU_DC_MAP_GBR24; |
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case MEDIA_BUS_FMT_RGB666_1X18: |
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return IPU_DC_MAP_BGR666; |
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case MEDIA_BUS_FMT_RGB666_1X24_CPADHI: |
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return IPU_DC_MAP_LVDS666; |
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case MEDIA_BUS_FMT_BGR888_1X24: |
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return IPU_DC_MAP_BGR24; |
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} |
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} |
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int ipu_dc_init_sync(struct ipu_dc *dc, struct ipu_di *di, bool interlaced, |
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u32 bus_format, u32 width) |
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{ |
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struct ipu_dc_priv *priv = dc->priv; |
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int addr, sync; |
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u32 reg = 0; |
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int map; |
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dc->di = ipu_di_get_num(di); |
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if (!IS_ALIGNED(width, 8)) { |
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dev_warn(priv->dev, |
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"%s: hactive does not align to 8 byte\n", __func__); |
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} |
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map = ipu_bus_format_to_map(bus_format); |
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/* |
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* In interlaced mode we need more counters to create the asymmetric |
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* per-field VSYNC signals. The pixel active signal synchronising DC |
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* to DI moves to signal generator #6 (see ipu-di.c). In progressive |
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* mode counter #5 is used. |
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*/ |
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sync = interlaced ? 6 : 5; |
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/* Reserve 5 microcode template words for each DI */ |
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if (dc->di) |
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addr = 5; |
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else |
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addr = 0; |
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if (interlaced) { |
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dc_link_event(dc, DC_EVT_NL, addr, 3); |
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dc_link_event(dc, DC_EVT_EOL, addr, 2); |
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dc_link_event(dc, DC_EVT_NEW_DATA, addr, 1); |
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/* Init template microcode */ |
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dc_write_tmpl(dc, addr, WROD(0), 0, map, SYNC_WAVE, 0, sync, 1); |
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} else { |
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dc_link_event(dc, DC_EVT_NL, addr + 2, 3); |
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dc_link_event(dc, DC_EVT_EOL, addr + 3, 2); |
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dc_link_event(dc, DC_EVT_NEW_DATA, addr + 1, 1); |
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/* Init template microcode */ |
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dc_write_tmpl(dc, addr + 2, WROD(0), 0, map, SYNC_WAVE, 8, sync, 1); |
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dc_write_tmpl(dc, addr + 3, WROD(0), 0, map, SYNC_WAVE, 4, sync, 0); |
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dc_write_tmpl(dc, addr + 4, WRG, 0, map, NULL_WAVE, 0, 0, 1); |
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dc_write_tmpl(dc, addr + 1, WROD(0), 0, map, SYNC_WAVE, 0, sync, 1); |
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} |
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dc_link_event(dc, DC_EVT_NF, 0, 0); |
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dc_link_event(dc, DC_EVT_NFIELD, 0, 0); |
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dc_link_event(dc, DC_EVT_EOF, 0, 0); |
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dc_link_event(dc, DC_EVT_EOFIELD, 0, 0); |
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dc_link_event(dc, DC_EVT_NEW_CHAN, 0, 0); |
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dc_link_event(dc, DC_EVT_NEW_ADDR, 0, 0); |
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reg = readl(dc->base + DC_WR_CH_CONF); |
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if (interlaced) |
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reg |= DC_WR_CH_CONF_FIELD_MODE; |
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else |
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reg &= ~DC_WR_CH_CONF_FIELD_MODE; |
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writel(reg, dc->base + DC_WR_CH_CONF); |
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writel(0x0, dc->base + DC_WR_CH_ADDR); |
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writel(width, priv->dc_reg + DC_DISP_CONF2(dc->di)); |
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return 0; |
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} |
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EXPORT_SYMBOL_GPL(ipu_dc_init_sync); |
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void ipu_dc_enable(struct ipu_soc *ipu) |
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{ |
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struct ipu_dc_priv *priv = ipu->dc_priv; |
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mutex_lock(&priv->mutex); |
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if (!priv->use_count) |
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ipu_module_enable(priv->ipu, IPU_CONF_DC_EN); |
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priv->use_count++; |
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mutex_unlock(&priv->mutex); |
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} |
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EXPORT_SYMBOL_GPL(ipu_dc_enable); |
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void ipu_dc_enable_channel(struct ipu_dc *dc) |
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{ |
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u32 reg; |
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reg = readl(dc->base + DC_WR_CH_CONF); |
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reg |= DC_WR_CH_CONF_PROG_TYPE_NORMAL; |
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writel(reg, dc->base + DC_WR_CH_CONF); |
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} |
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EXPORT_SYMBOL_GPL(ipu_dc_enable_channel); |
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void ipu_dc_disable_channel(struct ipu_dc *dc) |
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{ |
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u32 val; |
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val = readl(dc->base + DC_WR_CH_CONF); |
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val &= ~DC_WR_CH_CONF_PROG_TYPE_MASK; |
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writel(val, dc->base + DC_WR_CH_CONF); |
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} |
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EXPORT_SYMBOL_GPL(ipu_dc_disable_channel); |
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void ipu_dc_disable(struct ipu_soc *ipu) |
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{ |
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struct ipu_dc_priv *priv = ipu->dc_priv; |
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mutex_lock(&priv->mutex); |
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priv->use_count--; |
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if (!priv->use_count) |
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ipu_module_disable(priv->ipu, IPU_CONF_DC_EN); |
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if (priv->use_count < 0) |
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priv->use_count = 0; |
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mutex_unlock(&priv->mutex); |
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} |
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EXPORT_SYMBOL_GPL(ipu_dc_disable); |
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static void ipu_dc_map_config(struct ipu_dc_priv *priv, enum ipu_dc_map map, |
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int byte_num, int offset, int mask) |
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{ |
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int ptr = map * 3 + byte_num; |
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u32 reg; |
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reg = readl(priv->dc_reg + DC_MAP_CONF_VAL(ptr)); |
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reg &= ~(0xffff << (16 * (ptr & 0x1))); |
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reg |= ((offset << 8) | mask) << (16 * (ptr & 0x1)); |
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writel(reg, priv->dc_reg + DC_MAP_CONF_VAL(ptr)); |
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reg = readl(priv->dc_reg + DC_MAP_CONF_PTR(map)); |
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reg &= ~(0x1f << ((16 * (map & 0x1)) + (5 * byte_num))); |
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reg |= ptr << ((16 * (map & 0x1)) + (5 * byte_num)); |
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writel(reg, priv->dc_reg + DC_MAP_CONF_PTR(map)); |
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} |
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static void ipu_dc_map_clear(struct ipu_dc_priv *priv, int map) |
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{ |
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u32 reg = readl(priv->dc_reg + DC_MAP_CONF_PTR(map)); |
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writel(reg & ~(0xffff << (16 * (map & 0x1))), |
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priv->dc_reg + DC_MAP_CONF_PTR(map)); |
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} |
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struct ipu_dc *ipu_dc_get(struct ipu_soc *ipu, int channel) |
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{ |
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struct ipu_dc_priv *priv = ipu->dc_priv; |
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struct ipu_dc *dc; |
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if (channel >= IPU_DC_NUM_CHANNELS) |
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return ERR_PTR(-ENODEV); |
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dc = &priv->channels[channel]; |
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mutex_lock(&priv->mutex); |
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if (dc->in_use) { |
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mutex_unlock(&priv->mutex); |
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return ERR_PTR(-EBUSY); |
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} |
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dc->in_use = true; |
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mutex_unlock(&priv->mutex); |
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return dc; |
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} |
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EXPORT_SYMBOL_GPL(ipu_dc_get); |
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void ipu_dc_put(struct ipu_dc *dc) |
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{ |
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struct ipu_dc_priv *priv = dc->priv; |
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mutex_lock(&priv->mutex); |
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dc->in_use = false; |
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mutex_unlock(&priv->mutex); |
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} |
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EXPORT_SYMBOL_GPL(ipu_dc_put); |
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int ipu_dc_init(struct ipu_soc *ipu, struct device *dev, |
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unsigned long base, unsigned long template_base) |
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{ |
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struct ipu_dc_priv *priv; |
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static int channel_offsets[] = { 0, 0x1c, 0x38, 0x54, 0x58, 0x5c, |
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0x78, 0, 0x94, 0xb4}; |
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int i; |
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priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); |
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if (!priv) |
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return -ENOMEM; |
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mutex_init(&priv->mutex); |
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priv->dev = dev; |
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priv->ipu = ipu; |
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priv->dc_reg = devm_ioremap(dev, base, PAGE_SIZE); |
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priv->dc_tmpl_reg = devm_ioremap(dev, template_base, PAGE_SIZE); |
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if (!priv->dc_reg || !priv->dc_tmpl_reg) |
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return -ENOMEM; |
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for (i = 0; i < IPU_DC_NUM_CHANNELS; i++) { |
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priv->channels[i].chno = i; |
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priv->channels[i].priv = priv; |
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priv->channels[i].base = priv->dc_reg + channel_offsets[i]; |
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} |
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writel(DC_WR_CH_CONF_WORD_SIZE_24 | DC_WR_CH_CONF_DISP_ID_PARALLEL(1) | |
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DC_WR_CH_CONF_PROG_DI_ID, |
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priv->channels[1].base + DC_WR_CH_CONF); |
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writel(DC_WR_CH_CONF_WORD_SIZE_24 | DC_WR_CH_CONF_DISP_ID_PARALLEL(0), |
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priv->channels[5].base + DC_WR_CH_CONF); |
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writel(DC_GEN_SYNC_1_6_SYNC | DC_GEN_SYNC_PRIORITY_1, |
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priv->dc_reg + DC_GEN); |
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ipu->dc_priv = priv; |
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dev_dbg(dev, "DC base: 0x%08lx template base: 0x%08lx\n", |
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base, template_base); |
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/* rgb24 */ |
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ipu_dc_map_clear(priv, IPU_DC_MAP_RGB24); |
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ipu_dc_map_config(priv, IPU_DC_MAP_RGB24, 0, 7, 0xff); /* blue */ |
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ipu_dc_map_config(priv, IPU_DC_MAP_RGB24, 1, 15, 0xff); /* green */ |
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ipu_dc_map_config(priv, IPU_DC_MAP_RGB24, 2, 23, 0xff); /* red */ |
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/* rgb565 */ |
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ipu_dc_map_clear(priv, IPU_DC_MAP_RGB565); |
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ipu_dc_map_config(priv, IPU_DC_MAP_RGB565, 0, 4, 0xf8); /* blue */ |
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ipu_dc_map_config(priv, IPU_DC_MAP_RGB565, 1, 10, 0xfc); /* green */ |
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ipu_dc_map_config(priv, IPU_DC_MAP_RGB565, 2, 15, 0xf8); /* red */ |
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/* gbr24 */ |
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ipu_dc_map_clear(priv, IPU_DC_MAP_GBR24); |
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ipu_dc_map_config(priv, IPU_DC_MAP_GBR24, 2, 15, 0xff); /* green */ |
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ipu_dc_map_config(priv, IPU_DC_MAP_GBR24, 1, 7, 0xff); /* blue */ |
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ipu_dc_map_config(priv, IPU_DC_MAP_GBR24, 0, 23, 0xff); /* red */ |
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/* bgr666 */ |
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ipu_dc_map_clear(priv, IPU_DC_MAP_BGR666); |
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ipu_dc_map_config(priv, IPU_DC_MAP_BGR666, 0, 5, 0xfc); /* blue */ |
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ipu_dc_map_config(priv, IPU_DC_MAP_BGR666, 1, 11, 0xfc); /* green */ |
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ipu_dc_map_config(priv, IPU_DC_MAP_BGR666, 2, 17, 0xfc); /* red */ |
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/* lvds666 */ |
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ipu_dc_map_clear(priv, IPU_DC_MAP_LVDS666); |
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ipu_dc_map_config(priv, IPU_DC_MAP_LVDS666, 0, 5, 0xfc); /* blue */ |
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ipu_dc_map_config(priv, IPU_DC_MAP_LVDS666, 1, 13, 0xfc); /* green */ |
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ipu_dc_map_config(priv, IPU_DC_MAP_LVDS666, 2, 21, 0xfc); /* red */ |
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/* bgr24 */ |
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ipu_dc_map_clear(priv, IPU_DC_MAP_BGR24); |
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ipu_dc_map_config(priv, IPU_DC_MAP_BGR24, 2, 7, 0xff); /* red */ |
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ipu_dc_map_config(priv, IPU_DC_MAP_BGR24, 1, 15, 0xff); /* green */ |
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ipu_dc_map_config(priv, IPU_DC_MAP_BGR24, 0, 23, 0xff); /* blue */ |
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return 0; |
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} |
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void ipu_dc_exit(struct ipu_soc *ipu) |
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{ |
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}
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