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822 lines
21 KiB
822 lines
21 KiB
// SPDX-License-Identifier: GPL-2.0-only |
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/* |
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* arch/arm/mach-tegra/gpio.c |
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* |
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* Copyright (c) 2010 Google, Inc |
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* Copyright (c) 2011-2016, NVIDIA CORPORATION. All rights reserved. |
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* |
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* Author: |
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* Erik Gilling <[email protected]> |
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*/ |
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|
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#include <linux/err.h> |
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#include <linux/init.h> |
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#include <linux/irq.h> |
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#include <linux/interrupt.h> |
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#include <linux/io.h> |
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#include <linux/gpio/driver.h> |
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#include <linux/of_device.h> |
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#include <linux/platform_device.h> |
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#include <linux/module.h> |
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#include <linux/irqdomain.h> |
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#include <linux/irqchip/chained_irq.h> |
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#include <linux/pinctrl/consumer.h> |
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#include <linux/pm.h> |
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#define GPIO_BANK(x) ((x) >> 5) |
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#define GPIO_PORT(x) (((x) >> 3) & 0x3) |
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#define GPIO_BIT(x) ((x) & 0x7) |
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#define GPIO_REG(tgi, x) (GPIO_BANK(x) * tgi->soc->bank_stride + \ |
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GPIO_PORT(x) * 4) |
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#define GPIO_CNF(t, x) (GPIO_REG(t, x) + 0x00) |
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#define GPIO_OE(t, x) (GPIO_REG(t, x) + 0x10) |
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#define GPIO_OUT(t, x) (GPIO_REG(t, x) + 0X20) |
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#define GPIO_IN(t, x) (GPIO_REG(t, x) + 0x30) |
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#define GPIO_INT_STA(t, x) (GPIO_REG(t, x) + 0x40) |
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#define GPIO_INT_ENB(t, x) (GPIO_REG(t, x) + 0x50) |
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#define GPIO_INT_LVL(t, x) (GPIO_REG(t, x) + 0x60) |
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#define GPIO_INT_CLR(t, x) (GPIO_REG(t, x) + 0x70) |
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#define GPIO_DBC_CNT(t, x) (GPIO_REG(t, x) + 0xF0) |
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#define GPIO_MSK_CNF(t, x) (GPIO_REG(t, x) + t->soc->upper_offset + 0x00) |
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#define GPIO_MSK_OE(t, x) (GPIO_REG(t, x) + t->soc->upper_offset + 0x10) |
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#define GPIO_MSK_OUT(t, x) (GPIO_REG(t, x) + t->soc->upper_offset + 0X20) |
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#define GPIO_MSK_DBC_EN(t, x) (GPIO_REG(t, x) + t->soc->upper_offset + 0x30) |
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#define GPIO_MSK_INT_STA(t, x) (GPIO_REG(t, x) + t->soc->upper_offset + 0x40) |
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#define GPIO_MSK_INT_ENB(t, x) (GPIO_REG(t, x) + t->soc->upper_offset + 0x50) |
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#define GPIO_MSK_INT_LVL(t, x) (GPIO_REG(t, x) + t->soc->upper_offset + 0x60) |
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#define GPIO_INT_LVL_MASK 0x010101 |
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#define GPIO_INT_LVL_EDGE_RISING 0x000101 |
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#define GPIO_INT_LVL_EDGE_FALLING 0x000100 |
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#define GPIO_INT_LVL_EDGE_BOTH 0x010100 |
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#define GPIO_INT_LVL_LEVEL_HIGH 0x000001 |
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#define GPIO_INT_LVL_LEVEL_LOW 0x000000 |
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struct tegra_gpio_info; |
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struct tegra_gpio_bank { |
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unsigned int bank; |
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/* |
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* IRQ-core code uses raw locking, and thus, nested locking also |
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* should be raw in order not to trip spinlock debug warnings. |
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*/ |
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raw_spinlock_t lvl_lock[4]; |
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/* Lock for updating debounce count register */ |
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spinlock_t dbc_lock[4]; |
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#ifdef CONFIG_PM_SLEEP |
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u32 cnf[4]; |
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u32 out[4]; |
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u32 oe[4]; |
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u32 int_enb[4]; |
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u32 int_lvl[4]; |
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u32 wake_enb[4]; |
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u32 dbc_enb[4]; |
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#endif |
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u32 dbc_cnt[4]; |
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}; |
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struct tegra_gpio_soc_config { |
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bool debounce_supported; |
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u32 bank_stride; |
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u32 upper_offset; |
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}; |
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struct tegra_gpio_info { |
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struct device *dev; |
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void __iomem *regs; |
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struct tegra_gpio_bank *bank_info; |
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const struct tegra_gpio_soc_config *soc; |
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struct gpio_chip gc; |
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struct irq_chip ic; |
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u32 bank_count; |
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unsigned int *irqs; |
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}; |
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static inline void tegra_gpio_writel(struct tegra_gpio_info *tgi, |
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u32 val, u32 reg) |
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{ |
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writel_relaxed(val, tgi->regs + reg); |
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} |
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static inline u32 tegra_gpio_readl(struct tegra_gpio_info *tgi, u32 reg) |
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{ |
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return readl_relaxed(tgi->regs + reg); |
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} |
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static unsigned int tegra_gpio_compose(unsigned int bank, unsigned int port, |
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unsigned int bit) |
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{ |
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return (bank << 5) | ((port & 0x3) << 3) | (bit & 0x7); |
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} |
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static void tegra_gpio_mask_write(struct tegra_gpio_info *tgi, u32 reg, |
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unsigned int gpio, u32 value) |
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{ |
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u32 val; |
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val = 0x100 << GPIO_BIT(gpio); |
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if (value) |
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val |= 1 << GPIO_BIT(gpio); |
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tegra_gpio_writel(tgi, val, reg); |
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} |
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static void tegra_gpio_enable(struct tegra_gpio_info *tgi, unsigned int gpio) |
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{ |
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tegra_gpio_mask_write(tgi, GPIO_MSK_CNF(tgi, gpio), gpio, 1); |
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} |
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static void tegra_gpio_disable(struct tegra_gpio_info *tgi, unsigned int gpio) |
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{ |
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tegra_gpio_mask_write(tgi, GPIO_MSK_CNF(tgi, gpio), gpio, 0); |
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} |
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static int tegra_gpio_request(struct gpio_chip *chip, unsigned int offset) |
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{ |
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return pinctrl_gpio_request(chip->base + offset); |
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} |
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static void tegra_gpio_free(struct gpio_chip *chip, unsigned int offset) |
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{ |
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struct tegra_gpio_info *tgi = gpiochip_get_data(chip); |
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pinctrl_gpio_free(chip->base + offset); |
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tegra_gpio_disable(tgi, offset); |
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} |
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static void tegra_gpio_set(struct gpio_chip *chip, unsigned int offset, |
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int value) |
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{ |
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struct tegra_gpio_info *tgi = gpiochip_get_data(chip); |
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tegra_gpio_mask_write(tgi, GPIO_MSK_OUT(tgi, offset), offset, value); |
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} |
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static int tegra_gpio_get(struct gpio_chip *chip, unsigned int offset) |
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{ |
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struct tegra_gpio_info *tgi = gpiochip_get_data(chip); |
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unsigned int bval = BIT(GPIO_BIT(offset)); |
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/* If gpio is in output mode then read from the out value */ |
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if (tegra_gpio_readl(tgi, GPIO_OE(tgi, offset)) & bval) |
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return !!(tegra_gpio_readl(tgi, GPIO_OUT(tgi, offset)) & bval); |
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return !!(tegra_gpio_readl(tgi, GPIO_IN(tgi, offset)) & bval); |
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} |
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static int tegra_gpio_direction_input(struct gpio_chip *chip, |
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unsigned int offset) |
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{ |
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struct tegra_gpio_info *tgi = gpiochip_get_data(chip); |
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int ret; |
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tegra_gpio_mask_write(tgi, GPIO_MSK_OE(tgi, offset), offset, 0); |
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tegra_gpio_enable(tgi, offset); |
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ret = pinctrl_gpio_direction_input(chip->base + offset); |
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if (ret < 0) |
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dev_err(tgi->dev, |
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"Failed to set pinctrl input direction of GPIO %d: %d", |
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chip->base + offset, ret); |
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return ret; |
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} |
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static int tegra_gpio_direction_output(struct gpio_chip *chip, |
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unsigned int offset, |
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int value) |
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{ |
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struct tegra_gpio_info *tgi = gpiochip_get_data(chip); |
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int ret; |
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tegra_gpio_set(chip, offset, value); |
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tegra_gpio_mask_write(tgi, GPIO_MSK_OE(tgi, offset), offset, 1); |
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tegra_gpio_enable(tgi, offset); |
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ret = pinctrl_gpio_direction_output(chip->base + offset); |
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if (ret < 0) |
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dev_err(tgi->dev, |
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"Failed to set pinctrl output direction of GPIO %d: %d", |
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chip->base + offset, ret); |
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return ret; |
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} |
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static int tegra_gpio_get_direction(struct gpio_chip *chip, |
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unsigned int offset) |
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{ |
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struct tegra_gpio_info *tgi = gpiochip_get_data(chip); |
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u32 pin_mask = BIT(GPIO_BIT(offset)); |
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u32 cnf, oe; |
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cnf = tegra_gpio_readl(tgi, GPIO_CNF(tgi, offset)); |
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if (!(cnf & pin_mask)) |
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return -EINVAL; |
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oe = tegra_gpio_readl(tgi, GPIO_OE(tgi, offset)); |
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if (oe & pin_mask) |
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return GPIO_LINE_DIRECTION_OUT; |
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return GPIO_LINE_DIRECTION_IN; |
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} |
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static int tegra_gpio_set_debounce(struct gpio_chip *chip, unsigned int offset, |
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unsigned int debounce) |
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{ |
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struct tegra_gpio_info *tgi = gpiochip_get_data(chip); |
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struct tegra_gpio_bank *bank = &tgi->bank_info[GPIO_BANK(offset)]; |
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unsigned int debounce_ms = DIV_ROUND_UP(debounce, 1000); |
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unsigned long flags; |
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unsigned int port; |
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if (!debounce_ms) { |
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tegra_gpio_mask_write(tgi, GPIO_MSK_DBC_EN(tgi, offset), |
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offset, 0); |
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return 0; |
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} |
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debounce_ms = min(debounce_ms, 255U); |
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port = GPIO_PORT(offset); |
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/* There is only one debounce count register per port and hence |
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* set the maximum of current and requested debounce time. |
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*/ |
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spin_lock_irqsave(&bank->dbc_lock[port], flags); |
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if (bank->dbc_cnt[port] < debounce_ms) { |
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tegra_gpio_writel(tgi, debounce_ms, GPIO_DBC_CNT(tgi, offset)); |
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bank->dbc_cnt[port] = debounce_ms; |
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} |
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spin_unlock_irqrestore(&bank->dbc_lock[port], flags); |
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tegra_gpio_mask_write(tgi, GPIO_MSK_DBC_EN(tgi, offset), offset, 1); |
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return 0; |
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} |
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static int tegra_gpio_set_config(struct gpio_chip *chip, unsigned int offset, |
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unsigned long config) |
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{ |
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u32 debounce; |
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if (pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE) |
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return -ENOTSUPP; |
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debounce = pinconf_to_config_argument(config); |
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return tegra_gpio_set_debounce(chip, offset, debounce); |
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} |
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static void tegra_gpio_irq_ack(struct irq_data *d) |
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{ |
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struct gpio_chip *chip = irq_data_get_irq_chip_data(d); |
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struct tegra_gpio_info *tgi = gpiochip_get_data(chip); |
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unsigned int gpio = d->hwirq; |
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tegra_gpio_writel(tgi, 1 << GPIO_BIT(gpio), GPIO_INT_CLR(tgi, gpio)); |
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} |
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static void tegra_gpio_irq_mask(struct irq_data *d) |
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{ |
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struct gpio_chip *chip = irq_data_get_irq_chip_data(d); |
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struct tegra_gpio_info *tgi = gpiochip_get_data(chip); |
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unsigned int gpio = d->hwirq; |
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tegra_gpio_mask_write(tgi, GPIO_MSK_INT_ENB(tgi, gpio), gpio, 0); |
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} |
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static void tegra_gpio_irq_unmask(struct irq_data *d) |
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{ |
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struct gpio_chip *chip = irq_data_get_irq_chip_data(d); |
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struct tegra_gpio_info *tgi = gpiochip_get_data(chip); |
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unsigned int gpio = d->hwirq; |
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tegra_gpio_mask_write(tgi, GPIO_MSK_INT_ENB(tgi, gpio), gpio, 1); |
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} |
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static int tegra_gpio_irq_set_type(struct irq_data *d, unsigned int type) |
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{ |
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unsigned int gpio = d->hwirq, port = GPIO_PORT(gpio), lvl_type; |
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struct gpio_chip *chip = irq_data_get_irq_chip_data(d); |
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struct tegra_gpio_info *tgi = gpiochip_get_data(chip); |
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struct tegra_gpio_bank *bank; |
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unsigned long flags; |
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int ret; |
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u32 val; |
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bank = &tgi->bank_info[GPIO_BANK(d->hwirq)]; |
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switch (type & IRQ_TYPE_SENSE_MASK) { |
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case IRQ_TYPE_EDGE_RISING: |
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lvl_type = GPIO_INT_LVL_EDGE_RISING; |
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break; |
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case IRQ_TYPE_EDGE_FALLING: |
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lvl_type = GPIO_INT_LVL_EDGE_FALLING; |
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break; |
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case IRQ_TYPE_EDGE_BOTH: |
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lvl_type = GPIO_INT_LVL_EDGE_BOTH; |
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break; |
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case IRQ_TYPE_LEVEL_HIGH: |
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lvl_type = GPIO_INT_LVL_LEVEL_HIGH; |
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break; |
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case IRQ_TYPE_LEVEL_LOW: |
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lvl_type = GPIO_INT_LVL_LEVEL_LOW; |
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break; |
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default: |
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return -EINVAL; |
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} |
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raw_spin_lock_irqsave(&bank->lvl_lock[port], flags); |
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val = tegra_gpio_readl(tgi, GPIO_INT_LVL(tgi, gpio)); |
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val &= ~(GPIO_INT_LVL_MASK << GPIO_BIT(gpio)); |
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val |= lvl_type << GPIO_BIT(gpio); |
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tegra_gpio_writel(tgi, val, GPIO_INT_LVL(tgi, gpio)); |
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raw_spin_unlock_irqrestore(&bank->lvl_lock[port], flags); |
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tegra_gpio_mask_write(tgi, GPIO_MSK_OE(tgi, gpio), gpio, 0); |
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tegra_gpio_enable(tgi, gpio); |
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ret = gpiochip_lock_as_irq(&tgi->gc, gpio); |
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if (ret) { |
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dev_err(tgi->dev, |
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"unable to lock Tegra GPIO %u as IRQ\n", gpio); |
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tegra_gpio_disable(tgi, gpio); |
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return ret; |
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} |
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if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH)) |
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irq_set_handler_locked(d, handle_level_irq); |
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else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) |
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irq_set_handler_locked(d, handle_edge_irq); |
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if (d->parent_data) |
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ret = irq_chip_set_type_parent(d, type); |
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return ret; |
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} |
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static void tegra_gpio_irq_shutdown(struct irq_data *d) |
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{ |
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struct gpio_chip *chip = irq_data_get_irq_chip_data(d); |
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struct tegra_gpio_info *tgi = gpiochip_get_data(chip); |
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unsigned int gpio = d->hwirq; |
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tegra_gpio_irq_mask(d); |
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gpiochip_unlock_as_irq(&tgi->gc, gpio); |
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} |
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static void tegra_gpio_irq_handler(struct irq_desc *desc) |
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{ |
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struct tegra_gpio_info *tgi = irq_desc_get_handler_data(desc); |
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struct irq_chip *chip = irq_desc_get_chip(desc); |
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struct irq_domain *domain = tgi->gc.irq.domain; |
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unsigned int irq = irq_desc_get_irq(desc); |
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struct tegra_gpio_bank *bank = NULL; |
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unsigned int port, pin, gpio, i; |
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bool unmasked = false; |
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unsigned long sta; |
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u32 lvl; |
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for (i = 0; i < tgi->bank_count; i++) { |
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if (tgi->irqs[i] == irq) { |
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bank = &tgi->bank_info[i]; |
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break; |
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} |
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} |
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if (WARN_ON(bank == NULL)) |
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return; |
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chained_irq_enter(chip, desc); |
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for (port = 0; port < 4; port++) { |
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gpio = tegra_gpio_compose(bank->bank, port, 0); |
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sta = tegra_gpio_readl(tgi, GPIO_INT_STA(tgi, gpio)) & |
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tegra_gpio_readl(tgi, GPIO_INT_ENB(tgi, gpio)); |
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lvl = tegra_gpio_readl(tgi, GPIO_INT_LVL(tgi, gpio)); |
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for_each_set_bit(pin, &sta, 8) { |
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int ret; |
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tegra_gpio_writel(tgi, 1 << pin, |
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GPIO_INT_CLR(tgi, gpio)); |
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/* if gpio is edge triggered, clear condition |
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* before executing the handler so that we don't |
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* miss edges |
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*/ |
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if (!unmasked && lvl & (0x100 << pin)) { |
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unmasked = true; |
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chained_irq_exit(chip, desc); |
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} |
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ret = generic_handle_domain_irq(domain, gpio + pin); |
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WARN_RATELIMIT(ret, "hwirq = %d", gpio + pin); |
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} |
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} |
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if (!unmasked) |
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chained_irq_exit(chip, desc); |
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} |
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static int tegra_gpio_child_to_parent_hwirq(struct gpio_chip *chip, |
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unsigned int hwirq, |
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unsigned int type, |
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unsigned int *parent_hwirq, |
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unsigned int *parent_type) |
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{ |
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*parent_hwirq = chip->irq.child_offset_to_irq(chip, hwirq); |
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*parent_type = type; |
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return 0; |
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} |
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static void *tegra_gpio_populate_parent_fwspec(struct gpio_chip *chip, |
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unsigned int parent_hwirq, |
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unsigned int parent_type) |
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{ |
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struct irq_fwspec *fwspec; |
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fwspec = kmalloc(sizeof(*fwspec), GFP_KERNEL); |
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if (!fwspec) |
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return NULL; |
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fwspec->fwnode = chip->irq.parent_domain->fwnode; |
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fwspec->param_count = 3; |
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fwspec->param[0] = 0; |
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fwspec->param[1] = parent_hwirq; |
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fwspec->param[2] = parent_type; |
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return fwspec; |
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} |
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#ifdef CONFIG_PM_SLEEP |
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static int tegra_gpio_resume(struct device *dev) |
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{ |
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struct tegra_gpio_info *tgi = dev_get_drvdata(dev); |
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unsigned int b, p; |
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for (b = 0; b < tgi->bank_count; b++) { |
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struct tegra_gpio_bank *bank = &tgi->bank_info[b]; |
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for (p = 0; p < ARRAY_SIZE(bank->oe); p++) { |
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unsigned int gpio = (b << 5) | (p << 3); |
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tegra_gpio_writel(tgi, bank->cnf[p], |
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GPIO_CNF(tgi, gpio)); |
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|
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if (tgi->soc->debounce_supported) { |
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tegra_gpio_writel(tgi, bank->dbc_cnt[p], |
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GPIO_DBC_CNT(tgi, gpio)); |
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tegra_gpio_writel(tgi, bank->dbc_enb[p], |
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GPIO_MSK_DBC_EN(tgi, gpio)); |
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} |
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tegra_gpio_writel(tgi, bank->out[p], |
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GPIO_OUT(tgi, gpio)); |
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tegra_gpio_writel(tgi, bank->oe[p], |
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GPIO_OE(tgi, gpio)); |
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tegra_gpio_writel(tgi, bank->int_lvl[p], |
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GPIO_INT_LVL(tgi, gpio)); |
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tegra_gpio_writel(tgi, bank->int_enb[p], |
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GPIO_INT_ENB(tgi, gpio)); |
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} |
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} |
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return 0; |
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} |
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static int tegra_gpio_suspend(struct device *dev) |
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{ |
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struct tegra_gpio_info *tgi = dev_get_drvdata(dev); |
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unsigned int b, p; |
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|
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for (b = 0; b < tgi->bank_count; b++) { |
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struct tegra_gpio_bank *bank = &tgi->bank_info[b]; |
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|
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for (p = 0; p < ARRAY_SIZE(bank->oe); p++) { |
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unsigned int gpio = (b << 5) | (p << 3); |
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bank->cnf[p] = tegra_gpio_readl(tgi, |
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GPIO_CNF(tgi, gpio)); |
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bank->out[p] = tegra_gpio_readl(tgi, |
|
GPIO_OUT(tgi, gpio)); |
|
bank->oe[p] = tegra_gpio_readl(tgi, |
|
GPIO_OE(tgi, gpio)); |
|
if (tgi->soc->debounce_supported) { |
|
bank->dbc_enb[p] = tegra_gpio_readl(tgi, |
|
GPIO_MSK_DBC_EN(tgi, gpio)); |
|
bank->dbc_enb[p] = (bank->dbc_enb[p] << 8) | |
|
bank->dbc_enb[p]; |
|
} |
|
|
|
bank->int_enb[p] = tegra_gpio_readl(tgi, |
|
GPIO_INT_ENB(tgi, gpio)); |
|
bank->int_lvl[p] = tegra_gpio_readl(tgi, |
|
GPIO_INT_LVL(tgi, gpio)); |
|
|
|
/* Enable gpio irq for wake up source */ |
|
tegra_gpio_writel(tgi, bank->wake_enb[p], |
|
GPIO_INT_ENB(tgi, gpio)); |
|
} |
|
} |
|
|
|
return 0; |
|
} |
|
|
|
static int tegra_gpio_irq_set_wake(struct irq_data *d, unsigned int enable) |
|
{ |
|
struct gpio_chip *chip = irq_data_get_irq_chip_data(d); |
|
struct tegra_gpio_info *tgi = gpiochip_get_data(chip); |
|
struct tegra_gpio_bank *bank; |
|
unsigned int gpio = d->hwirq; |
|
u32 port, bit, mask; |
|
int err; |
|
|
|
bank = &tgi->bank_info[GPIO_BANK(d->hwirq)]; |
|
|
|
port = GPIO_PORT(gpio); |
|
bit = GPIO_BIT(gpio); |
|
mask = BIT(bit); |
|
|
|
err = irq_set_irq_wake(tgi->irqs[bank->bank], enable); |
|
if (err) |
|
return err; |
|
|
|
if (d->parent_data) { |
|
err = irq_chip_set_wake_parent(d, enable); |
|
if (err) { |
|
irq_set_irq_wake(tgi->irqs[bank->bank], !enable); |
|
return err; |
|
} |
|
} |
|
|
|
if (enable) |
|
bank->wake_enb[port] |= mask; |
|
else |
|
bank->wake_enb[port] &= ~mask; |
|
|
|
return 0; |
|
} |
|
#endif |
|
|
|
static int tegra_gpio_irq_set_affinity(struct irq_data *data, |
|
const struct cpumask *dest, |
|
bool force) |
|
{ |
|
if (data->parent_data) |
|
return irq_chip_set_affinity_parent(data, dest, force); |
|
|
|
return -EINVAL; |
|
} |
|
|
|
static int tegra_gpio_irq_request_resources(struct irq_data *d) |
|
{ |
|
struct gpio_chip *chip = irq_data_get_irq_chip_data(d); |
|
struct tegra_gpio_info *tgi = gpiochip_get_data(chip); |
|
|
|
tegra_gpio_enable(tgi, d->hwirq); |
|
|
|
return gpiochip_reqres_irq(chip, d->hwirq); |
|
} |
|
|
|
static void tegra_gpio_irq_release_resources(struct irq_data *d) |
|
{ |
|
struct gpio_chip *chip = irq_data_get_irq_chip_data(d); |
|
struct tegra_gpio_info *tgi = gpiochip_get_data(chip); |
|
|
|
gpiochip_relres_irq(chip, d->hwirq); |
|
tegra_gpio_enable(tgi, d->hwirq); |
|
} |
|
|
|
#ifdef CONFIG_DEBUG_FS |
|
|
|
#include <linux/debugfs.h> |
|
#include <linux/seq_file.h> |
|
|
|
static int tegra_dbg_gpio_show(struct seq_file *s, void *unused) |
|
{ |
|
struct tegra_gpio_info *tgi = dev_get_drvdata(s->private); |
|
unsigned int i, j; |
|
|
|
for (i = 0; i < tgi->bank_count; i++) { |
|
for (j = 0; j < 4; j++) { |
|
unsigned int gpio = tegra_gpio_compose(i, j, 0); |
|
|
|
seq_printf(s, |
|
"%u:%u %02x %02x %02x %02x %02x %02x %06x\n", |
|
i, j, |
|
tegra_gpio_readl(tgi, GPIO_CNF(tgi, gpio)), |
|
tegra_gpio_readl(tgi, GPIO_OE(tgi, gpio)), |
|
tegra_gpio_readl(tgi, GPIO_OUT(tgi, gpio)), |
|
tegra_gpio_readl(tgi, GPIO_IN(tgi, gpio)), |
|
tegra_gpio_readl(tgi, GPIO_INT_STA(tgi, gpio)), |
|
tegra_gpio_readl(tgi, GPIO_INT_ENB(tgi, gpio)), |
|
tegra_gpio_readl(tgi, GPIO_INT_LVL(tgi, gpio))); |
|
} |
|
} |
|
return 0; |
|
} |
|
|
|
static void tegra_gpio_debuginit(struct tegra_gpio_info *tgi) |
|
{ |
|
debugfs_create_devm_seqfile(tgi->dev, "tegra_gpio", NULL, |
|
tegra_dbg_gpio_show); |
|
} |
|
|
|
#else |
|
|
|
static inline void tegra_gpio_debuginit(struct tegra_gpio_info *tgi) |
|
{ |
|
} |
|
|
|
#endif |
|
|
|
static const struct dev_pm_ops tegra_gpio_pm_ops = { |
|
SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(tegra_gpio_suspend, tegra_gpio_resume) |
|
}; |
|
|
|
static const struct of_device_id tegra_pmc_of_match[] = { |
|
{ .compatible = "nvidia,tegra210-pmc", }, |
|
{ /* sentinel */ }, |
|
}; |
|
|
|
static int tegra_gpio_probe(struct platform_device *pdev) |
|
{ |
|
struct tegra_gpio_bank *bank; |
|
struct tegra_gpio_info *tgi; |
|
struct gpio_irq_chip *irq; |
|
struct device_node *np; |
|
unsigned int i, j; |
|
int ret; |
|
|
|
tgi = devm_kzalloc(&pdev->dev, sizeof(*tgi), GFP_KERNEL); |
|
if (!tgi) |
|
return -ENODEV; |
|
|
|
tgi->soc = of_device_get_match_data(&pdev->dev); |
|
tgi->dev = &pdev->dev; |
|
|
|
ret = platform_irq_count(pdev); |
|
if (ret < 0) |
|
return ret; |
|
|
|
tgi->bank_count = ret; |
|
|
|
if (!tgi->bank_count) { |
|
dev_err(&pdev->dev, "Missing IRQ resource\n"); |
|
return -ENODEV; |
|
} |
|
|
|
tgi->gc.label = "tegra-gpio"; |
|
tgi->gc.request = tegra_gpio_request; |
|
tgi->gc.free = tegra_gpio_free; |
|
tgi->gc.direction_input = tegra_gpio_direction_input; |
|
tgi->gc.get = tegra_gpio_get; |
|
tgi->gc.direction_output = tegra_gpio_direction_output; |
|
tgi->gc.set = tegra_gpio_set; |
|
tgi->gc.get_direction = tegra_gpio_get_direction; |
|
tgi->gc.base = 0; |
|
tgi->gc.ngpio = tgi->bank_count * 32; |
|
tgi->gc.parent = &pdev->dev; |
|
tgi->gc.of_node = pdev->dev.of_node; |
|
|
|
tgi->ic.name = "GPIO"; |
|
tgi->ic.irq_ack = tegra_gpio_irq_ack; |
|
tgi->ic.irq_mask = tegra_gpio_irq_mask; |
|
tgi->ic.irq_unmask = tegra_gpio_irq_unmask; |
|
tgi->ic.irq_set_type = tegra_gpio_irq_set_type; |
|
tgi->ic.irq_shutdown = tegra_gpio_irq_shutdown; |
|
#ifdef CONFIG_PM_SLEEP |
|
tgi->ic.irq_set_wake = tegra_gpio_irq_set_wake; |
|
#endif |
|
tgi->ic.irq_request_resources = tegra_gpio_irq_request_resources; |
|
tgi->ic.irq_release_resources = tegra_gpio_irq_release_resources; |
|
|
|
platform_set_drvdata(pdev, tgi); |
|
|
|
if (tgi->soc->debounce_supported) |
|
tgi->gc.set_config = tegra_gpio_set_config; |
|
|
|
tgi->bank_info = devm_kcalloc(&pdev->dev, tgi->bank_count, |
|
sizeof(*tgi->bank_info), GFP_KERNEL); |
|
if (!tgi->bank_info) |
|
return -ENOMEM; |
|
|
|
tgi->irqs = devm_kcalloc(&pdev->dev, tgi->bank_count, |
|
sizeof(*tgi->irqs), GFP_KERNEL); |
|
if (!tgi->irqs) |
|
return -ENOMEM; |
|
|
|
for (i = 0; i < tgi->bank_count; i++) { |
|
ret = platform_get_irq(pdev, i); |
|
if (ret < 0) |
|
return ret; |
|
|
|
bank = &tgi->bank_info[i]; |
|
bank->bank = i; |
|
|
|
tgi->irqs[i] = ret; |
|
|
|
for (j = 0; j < 4; j++) { |
|
raw_spin_lock_init(&bank->lvl_lock[j]); |
|
spin_lock_init(&bank->dbc_lock[j]); |
|
} |
|
} |
|
|
|
irq = &tgi->gc.irq; |
|
irq->chip = &tgi->ic; |
|
irq->fwnode = of_node_to_fwnode(pdev->dev.of_node); |
|
irq->child_to_parent_hwirq = tegra_gpio_child_to_parent_hwirq; |
|
irq->populate_parent_alloc_arg = tegra_gpio_populate_parent_fwspec; |
|
irq->handler = handle_simple_irq; |
|
irq->default_type = IRQ_TYPE_NONE; |
|
irq->parent_handler = tegra_gpio_irq_handler; |
|
irq->parent_handler_data = tgi; |
|
irq->num_parents = tgi->bank_count; |
|
irq->parents = tgi->irqs; |
|
|
|
np = of_find_matching_node(NULL, tegra_pmc_of_match); |
|
if (np) { |
|
irq->parent_domain = irq_find_host(np); |
|
of_node_put(np); |
|
|
|
if (!irq->parent_domain) |
|
return -EPROBE_DEFER; |
|
|
|
tgi->ic.irq_set_affinity = tegra_gpio_irq_set_affinity; |
|
} |
|
|
|
tgi->regs = devm_platform_ioremap_resource(pdev, 0); |
|
if (IS_ERR(tgi->regs)) |
|
return PTR_ERR(tgi->regs); |
|
|
|
for (i = 0; i < tgi->bank_count; i++) { |
|
for (j = 0; j < 4; j++) { |
|
int gpio = tegra_gpio_compose(i, j, 0); |
|
|
|
tegra_gpio_writel(tgi, 0x00, GPIO_INT_ENB(tgi, gpio)); |
|
} |
|
} |
|
|
|
ret = devm_gpiochip_add_data(&pdev->dev, &tgi->gc, tgi); |
|
if (ret < 0) |
|
return ret; |
|
|
|
tegra_gpio_debuginit(tgi); |
|
|
|
return 0; |
|
} |
|
|
|
static const struct tegra_gpio_soc_config tegra20_gpio_config = { |
|
.bank_stride = 0x80, |
|
.upper_offset = 0x800, |
|
}; |
|
|
|
static const struct tegra_gpio_soc_config tegra30_gpio_config = { |
|
.bank_stride = 0x100, |
|
.upper_offset = 0x80, |
|
}; |
|
|
|
static const struct tegra_gpio_soc_config tegra210_gpio_config = { |
|
.debounce_supported = true, |
|
.bank_stride = 0x100, |
|
.upper_offset = 0x80, |
|
}; |
|
|
|
static const struct of_device_id tegra_gpio_of_match[] = { |
|
{ .compatible = "nvidia,tegra210-gpio", .data = &tegra210_gpio_config }, |
|
{ .compatible = "nvidia,tegra30-gpio", .data = &tegra30_gpio_config }, |
|
{ .compatible = "nvidia,tegra20-gpio", .data = &tegra20_gpio_config }, |
|
{ }, |
|
}; |
|
MODULE_DEVICE_TABLE(of, tegra_gpio_of_match); |
|
|
|
static struct platform_driver tegra_gpio_driver = { |
|
.driver = { |
|
.name = "tegra-gpio", |
|
.pm = &tegra_gpio_pm_ops, |
|
.of_match_table = tegra_gpio_of_match, |
|
}, |
|
.probe = tegra_gpio_probe, |
|
}; |
|
module_platform_driver(tegra_gpio_driver); |
|
|
|
MODULE_DESCRIPTION("NVIDIA Tegra GPIO controller driver"); |
|
MODULE_AUTHOR("Laxman Dewangan <[email protected]>"); |
|
MODULE_AUTHOR("Stephen Warren <[email protected]>"); |
|
MODULE_AUTHOR("Thierry Reding <[email protected]>"); |
|
MODULE_AUTHOR("Erik Gilling <[email protected]>"); |
|
MODULE_LICENSE("GPL v2");
|
|
|