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458 lines
12 KiB
458 lines
12 KiB
/* |
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* GPIOs on MPC512x/8349/8572/8610/QorIQ and compatible |
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* |
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* Copyright (C) 2008 Peter Korsgaard <[email protected]> |
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* Copyright (C) 2016 Freescale Semiconductor Inc. |
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* |
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* This file is licensed under the terms of the GNU General Public License |
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* version 2. This program is licensed "as is" without any warranty of any |
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* kind, whether express or implied. |
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*/ |
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#include <linux/acpi.h> |
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#include <linux/kernel.h> |
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#include <linux/init.h> |
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#include <linux/spinlock.h> |
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#include <linux/io.h> |
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#include <linux/of.h> |
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#include <linux/of_gpio.h> |
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#include <linux/of_address.h> |
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#include <linux/of_irq.h> |
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#include <linux/of_platform.h> |
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#include <linux/property.h> |
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#include <linux/mod_devicetable.h> |
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#include <linux/slab.h> |
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#include <linux/irq.h> |
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#include <linux/gpio/driver.h> |
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#include <linux/bitops.h> |
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#include <linux/interrupt.h> |
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#define MPC8XXX_GPIO_PINS 32 |
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#define GPIO_DIR 0x00 |
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#define GPIO_ODR 0x04 |
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#define GPIO_DAT 0x08 |
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#define GPIO_IER 0x0c |
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#define GPIO_IMR 0x10 |
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#define GPIO_ICR 0x14 |
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#define GPIO_ICR2 0x18 |
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#define GPIO_IBE 0x18 |
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struct mpc8xxx_gpio_chip { |
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struct gpio_chip gc; |
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void __iomem *regs; |
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raw_spinlock_t lock; |
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int (*direction_output)(struct gpio_chip *chip, |
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unsigned offset, int value); |
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struct irq_domain *irq; |
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unsigned int irqn; |
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}; |
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/* |
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* This hardware has a big endian bit assignment such that GPIO line 0 is |
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* connected to bit 31, line 1 to bit 30 ... line 31 to bit 0. |
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* This inline helper give the right bitmask for a certain line. |
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*/ |
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static inline u32 mpc_pin2mask(unsigned int offset) |
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{ |
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return BIT(31 - offset); |
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} |
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/* Workaround GPIO 1 errata on MPC8572/MPC8536. The status of GPIOs |
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* defined as output cannot be determined by reading GPDAT register, |
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* so we use shadow data register instead. The status of input pins |
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* is determined by reading GPDAT register. |
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*/ |
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static int mpc8572_gpio_get(struct gpio_chip *gc, unsigned int gpio) |
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{ |
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u32 val; |
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struct mpc8xxx_gpio_chip *mpc8xxx_gc = gpiochip_get_data(gc); |
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u32 out_mask, out_shadow; |
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out_mask = gc->read_reg(mpc8xxx_gc->regs + GPIO_DIR); |
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val = gc->read_reg(mpc8xxx_gc->regs + GPIO_DAT) & ~out_mask; |
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out_shadow = gc->bgpio_data & out_mask; |
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return !!((val | out_shadow) & mpc_pin2mask(gpio)); |
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} |
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static int mpc5121_gpio_dir_out(struct gpio_chip *gc, |
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unsigned int gpio, int val) |
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{ |
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struct mpc8xxx_gpio_chip *mpc8xxx_gc = gpiochip_get_data(gc); |
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/* GPIO 28..31 are input only on MPC5121 */ |
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if (gpio >= 28) |
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return -EINVAL; |
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return mpc8xxx_gc->direction_output(gc, gpio, val); |
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} |
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static int mpc5125_gpio_dir_out(struct gpio_chip *gc, |
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unsigned int gpio, int val) |
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{ |
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struct mpc8xxx_gpio_chip *mpc8xxx_gc = gpiochip_get_data(gc); |
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/* GPIO 0..3 are input only on MPC5125 */ |
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if (gpio <= 3) |
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return -EINVAL; |
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return mpc8xxx_gc->direction_output(gc, gpio, val); |
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} |
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static int mpc8xxx_gpio_to_irq(struct gpio_chip *gc, unsigned offset) |
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{ |
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struct mpc8xxx_gpio_chip *mpc8xxx_gc = gpiochip_get_data(gc); |
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if (mpc8xxx_gc->irq && offset < MPC8XXX_GPIO_PINS) |
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return irq_create_mapping(mpc8xxx_gc->irq, offset); |
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else |
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return -ENXIO; |
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} |
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static irqreturn_t mpc8xxx_gpio_irq_cascade(int irq, void *data) |
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{ |
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struct mpc8xxx_gpio_chip *mpc8xxx_gc = data; |
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struct gpio_chip *gc = &mpc8xxx_gc->gc; |
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unsigned long mask; |
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int i; |
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mask = gc->read_reg(mpc8xxx_gc->regs + GPIO_IER) |
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& gc->read_reg(mpc8xxx_gc->regs + GPIO_IMR); |
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for_each_set_bit(i, &mask, 32) |
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generic_handle_domain_irq(mpc8xxx_gc->irq, 31 - i); |
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return IRQ_HANDLED; |
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} |
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static void mpc8xxx_irq_unmask(struct irq_data *d) |
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{ |
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struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d); |
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struct gpio_chip *gc = &mpc8xxx_gc->gc; |
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unsigned long flags; |
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raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags); |
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gc->write_reg(mpc8xxx_gc->regs + GPIO_IMR, |
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gc->read_reg(mpc8xxx_gc->regs + GPIO_IMR) |
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| mpc_pin2mask(irqd_to_hwirq(d))); |
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raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags); |
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} |
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static void mpc8xxx_irq_mask(struct irq_data *d) |
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{ |
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struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d); |
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struct gpio_chip *gc = &mpc8xxx_gc->gc; |
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unsigned long flags; |
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raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags); |
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gc->write_reg(mpc8xxx_gc->regs + GPIO_IMR, |
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gc->read_reg(mpc8xxx_gc->regs + GPIO_IMR) |
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& ~mpc_pin2mask(irqd_to_hwirq(d))); |
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raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags); |
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} |
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static void mpc8xxx_irq_ack(struct irq_data *d) |
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{ |
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struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d); |
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struct gpio_chip *gc = &mpc8xxx_gc->gc; |
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gc->write_reg(mpc8xxx_gc->regs + GPIO_IER, |
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mpc_pin2mask(irqd_to_hwirq(d))); |
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} |
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static int mpc8xxx_irq_set_type(struct irq_data *d, unsigned int flow_type) |
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{ |
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struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d); |
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struct gpio_chip *gc = &mpc8xxx_gc->gc; |
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unsigned long flags; |
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switch (flow_type) { |
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case IRQ_TYPE_EDGE_FALLING: |
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raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags); |
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gc->write_reg(mpc8xxx_gc->regs + GPIO_ICR, |
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gc->read_reg(mpc8xxx_gc->regs + GPIO_ICR) |
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| mpc_pin2mask(irqd_to_hwirq(d))); |
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raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags); |
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break; |
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case IRQ_TYPE_EDGE_BOTH: |
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raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags); |
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gc->write_reg(mpc8xxx_gc->regs + GPIO_ICR, |
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gc->read_reg(mpc8xxx_gc->regs + GPIO_ICR) |
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& ~mpc_pin2mask(irqd_to_hwirq(d))); |
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raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags); |
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break; |
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default: |
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return -EINVAL; |
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} |
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return 0; |
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} |
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static int mpc512x_irq_set_type(struct irq_data *d, unsigned int flow_type) |
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{ |
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struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d); |
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struct gpio_chip *gc = &mpc8xxx_gc->gc; |
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unsigned long gpio = irqd_to_hwirq(d); |
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void __iomem *reg; |
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unsigned int shift; |
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unsigned long flags; |
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if (gpio < 16) { |
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reg = mpc8xxx_gc->regs + GPIO_ICR; |
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shift = (15 - gpio) * 2; |
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} else { |
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reg = mpc8xxx_gc->regs + GPIO_ICR2; |
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shift = (15 - (gpio % 16)) * 2; |
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} |
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switch (flow_type) { |
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case IRQ_TYPE_EDGE_FALLING: |
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case IRQ_TYPE_LEVEL_LOW: |
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raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags); |
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gc->write_reg(reg, (gc->read_reg(reg) & ~(3 << shift)) |
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| (2 << shift)); |
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raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags); |
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break; |
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case IRQ_TYPE_EDGE_RISING: |
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case IRQ_TYPE_LEVEL_HIGH: |
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raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags); |
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gc->write_reg(reg, (gc->read_reg(reg) & ~(3 << shift)) |
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| (1 << shift)); |
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raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags); |
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break; |
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case IRQ_TYPE_EDGE_BOTH: |
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raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags); |
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gc->write_reg(reg, (gc->read_reg(reg) & ~(3 << shift))); |
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raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags); |
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break; |
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default: |
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return -EINVAL; |
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} |
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return 0; |
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} |
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static struct irq_chip mpc8xxx_irq_chip = { |
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.name = "mpc8xxx-gpio", |
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.irq_unmask = mpc8xxx_irq_unmask, |
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.irq_mask = mpc8xxx_irq_mask, |
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.irq_ack = mpc8xxx_irq_ack, |
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/* this might get overwritten in mpc8xxx_probe() */ |
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.irq_set_type = mpc8xxx_irq_set_type, |
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}; |
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static int mpc8xxx_gpio_irq_map(struct irq_domain *h, unsigned int irq, |
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irq_hw_number_t hwirq) |
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{ |
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irq_set_chip_data(irq, h->host_data); |
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irq_set_chip_and_handler(irq, &mpc8xxx_irq_chip, handle_edge_irq); |
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return 0; |
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} |
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static const struct irq_domain_ops mpc8xxx_gpio_irq_ops = { |
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.map = mpc8xxx_gpio_irq_map, |
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.xlate = irq_domain_xlate_twocell, |
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}; |
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struct mpc8xxx_gpio_devtype { |
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int (*gpio_dir_out)(struct gpio_chip *, unsigned int, int); |
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int (*gpio_get)(struct gpio_chip *, unsigned int); |
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int (*irq_set_type)(struct irq_data *, unsigned int); |
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}; |
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static const struct mpc8xxx_gpio_devtype mpc512x_gpio_devtype = { |
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.gpio_dir_out = mpc5121_gpio_dir_out, |
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.irq_set_type = mpc512x_irq_set_type, |
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}; |
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static const struct mpc8xxx_gpio_devtype mpc5125_gpio_devtype = { |
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.gpio_dir_out = mpc5125_gpio_dir_out, |
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.irq_set_type = mpc512x_irq_set_type, |
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}; |
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static const struct mpc8xxx_gpio_devtype mpc8572_gpio_devtype = { |
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.gpio_get = mpc8572_gpio_get, |
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}; |
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static const struct mpc8xxx_gpio_devtype mpc8xxx_gpio_devtype_default = { |
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.irq_set_type = mpc8xxx_irq_set_type, |
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}; |
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static const struct of_device_id mpc8xxx_gpio_ids[] = { |
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{ .compatible = "fsl,mpc8349-gpio", }, |
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{ .compatible = "fsl,mpc8572-gpio", .data = &mpc8572_gpio_devtype, }, |
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{ .compatible = "fsl,mpc8610-gpio", }, |
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{ .compatible = "fsl,mpc5121-gpio", .data = &mpc512x_gpio_devtype, }, |
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{ .compatible = "fsl,mpc5125-gpio", .data = &mpc5125_gpio_devtype, }, |
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{ .compatible = "fsl,pq3-gpio", }, |
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{ .compatible = "fsl,ls1028a-gpio", }, |
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{ .compatible = "fsl,ls1088a-gpio", }, |
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{ .compatible = "fsl,qoriq-gpio", }, |
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{} |
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}; |
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static int mpc8xxx_probe(struct platform_device *pdev) |
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{ |
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struct device_node *np = pdev->dev.of_node; |
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struct mpc8xxx_gpio_chip *mpc8xxx_gc; |
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struct gpio_chip *gc; |
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const struct mpc8xxx_gpio_devtype *devtype = NULL; |
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struct fwnode_handle *fwnode; |
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int ret; |
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mpc8xxx_gc = devm_kzalloc(&pdev->dev, sizeof(*mpc8xxx_gc), GFP_KERNEL); |
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if (!mpc8xxx_gc) |
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return -ENOMEM; |
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platform_set_drvdata(pdev, mpc8xxx_gc); |
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raw_spin_lock_init(&mpc8xxx_gc->lock); |
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mpc8xxx_gc->regs = devm_platform_ioremap_resource(pdev, 0); |
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if (IS_ERR(mpc8xxx_gc->regs)) |
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return PTR_ERR(mpc8xxx_gc->regs); |
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gc = &mpc8xxx_gc->gc; |
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gc->parent = &pdev->dev; |
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if (device_property_read_bool(&pdev->dev, "little-endian")) { |
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ret = bgpio_init(gc, &pdev->dev, 4, |
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mpc8xxx_gc->regs + GPIO_DAT, |
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NULL, NULL, |
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mpc8xxx_gc->regs + GPIO_DIR, NULL, |
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BGPIOF_BIG_ENDIAN); |
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if (ret) |
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return ret; |
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dev_dbg(&pdev->dev, "GPIO registers are LITTLE endian\n"); |
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} else { |
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ret = bgpio_init(gc, &pdev->dev, 4, |
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mpc8xxx_gc->regs + GPIO_DAT, |
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NULL, NULL, |
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mpc8xxx_gc->regs + GPIO_DIR, NULL, |
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BGPIOF_BIG_ENDIAN |
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| BGPIOF_BIG_ENDIAN_BYTE_ORDER); |
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if (ret) |
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return ret; |
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dev_dbg(&pdev->dev, "GPIO registers are BIG endian\n"); |
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} |
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mpc8xxx_gc->direction_output = gc->direction_output; |
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devtype = device_get_match_data(&pdev->dev); |
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if (!devtype) |
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devtype = &mpc8xxx_gpio_devtype_default; |
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/* |
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* It's assumed that only a single type of gpio controller is available |
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* on the current machine, so overwriting global data is fine. |
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*/ |
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if (devtype->irq_set_type) |
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mpc8xxx_irq_chip.irq_set_type = devtype->irq_set_type; |
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if (devtype->gpio_dir_out) |
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gc->direction_output = devtype->gpio_dir_out; |
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if (devtype->gpio_get) |
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gc->get = devtype->gpio_get; |
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gc->to_irq = mpc8xxx_gpio_to_irq; |
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/* |
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* The GPIO Input Buffer Enable register(GPIO_IBE) is used to control |
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* the input enable of each individual GPIO port. When an individual |
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* GPIO port’s direction is set to input (GPIO_GPDIR[DRn=0]), the |
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* associated input enable must be set (GPIOxGPIE[IEn]=1) to propagate |
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* the port value to the GPIO Data Register. |
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*/ |
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fwnode = dev_fwnode(&pdev->dev); |
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if (of_device_is_compatible(np, "fsl,qoriq-gpio") || |
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of_device_is_compatible(np, "fsl,ls1028a-gpio") || |
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of_device_is_compatible(np, "fsl,ls1088a-gpio") || |
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is_acpi_node(fwnode)) |
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gc->write_reg(mpc8xxx_gc->regs + GPIO_IBE, 0xffffffff); |
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ret = devm_gpiochip_add_data(&pdev->dev, gc, mpc8xxx_gc); |
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if (ret) { |
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dev_err(&pdev->dev, |
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"GPIO chip registration failed with status %d\n", ret); |
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return ret; |
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} |
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mpc8xxx_gc->irqn = platform_get_irq(pdev, 0); |
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if (!mpc8xxx_gc->irqn) |
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return 0; |
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mpc8xxx_gc->irq = irq_domain_create_linear(fwnode, |
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MPC8XXX_GPIO_PINS, |
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&mpc8xxx_gpio_irq_ops, |
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mpc8xxx_gc); |
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if (!mpc8xxx_gc->irq) |
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return 0; |
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/* ack and mask all irqs */ |
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gc->write_reg(mpc8xxx_gc->regs + GPIO_IER, 0xffffffff); |
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gc->write_reg(mpc8xxx_gc->regs + GPIO_IMR, 0); |
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ret = devm_request_irq(&pdev->dev, mpc8xxx_gc->irqn, |
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mpc8xxx_gpio_irq_cascade, |
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IRQF_NO_THREAD | IRQF_SHARED, "gpio-cascade", |
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mpc8xxx_gc); |
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if (ret) { |
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dev_err(&pdev->dev, |
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"failed to devm_request_irq(%d), ret = %d\n", |
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mpc8xxx_gc->irqn, ret); |
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goto err; |
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} |
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return 0; |
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err: |
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irq_domain_remove(mpc8xxx_gc->irq); |
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return ret; |
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} |
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static int mpc8xxx_remove(struct platform_device *pdev) |
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{ |
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struct mpc8xxx_gpio_chip *mpc8xxx_gc = platform_get_drvdata(pdev); |
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if (mpc8xxx_gc->irq) { |
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irq_set_chained_handler_and_data(mpc8xxx_gc->irqn, NULL, NULL); |
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irq_domain_remove(mpc8xxx_gc->irq); |
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} |
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return 0; |
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} |
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#ifdef CONFIG_ACPI |
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static const struct acpi_device_id gpio_acpi_ids[] = { |
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{"NXP0031",}, |
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{ } |
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}; |
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MODULE_DEVICE_TABLE(acpi, gpio_acpi_ids); |
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#endif |
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static struct platform_driver mpc8xxx_plat_driver = { |
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.probe = mpc8xxx_probe, |
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.remove = mpc8xxx_remove, |
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.driver = { |
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.name = "gpio-mpc8xxx", |
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.of_match_table = mpc8xxx_gpio_ids, |
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.acpi_match_table = ACPI_PTR(gpio_acpi_ids), |
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}, |
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}; |
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static int __init mpc8xxx_init(void) |
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{ |
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return platform_driver_register(&mpc8xxx_plat_driver); |
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} |
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arch_initcall(mpc8xxx_init);
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