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666 lines
16 KiB
666 lines
16 KiB
// SPDX-License-Identifier: GPL-2.0-or-later |
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// Copyright (C) IBM Corporation 2018 |
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// FSI master driver for AST2600 |
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#include <linux/clk.h> |
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#include <linux/delay.h> |
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#include <linux/fsi.h> |
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#include <linux/io.h> |
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#include <linux/mfd/syscon.h> |
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#include <linux/module.h> |
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#include <linux/mutex.h> |
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#include <linux/of.h> |
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#include <linux/platform_device.h> |
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#include <linux/regmap.h> |
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#include <linux/slab.h> |
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#include <linux/iopoll.h> |
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#include <linux/gpio/consumer.h> |
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#include "fsi-master.h" |
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struct fsi_master_aspeed { |
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struct fsi_master master; |
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struct mutex lock; /* protect HW access */ |
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struct device *dev; |
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void __iomem *base; |
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struct clk *clk; |
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struct gpio_desc *cfam_reset_gpio; |
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}; |
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#define to_fsi_master_aspeed(m) \ |
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container_of(m, struct fsi_master_aspeed, master) |
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/* Control register (size 0x400) */ |
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static const u32 ctrl_base = 0x80000000; |
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static const u32 fsi_base = 0xa0000000; |
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#define OPB_FSI_VER 0x00 |
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#define OPB_TRIGGER 0x04 |
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#define OPB_CTRL_BASE 0x08 |
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#define OPB_FSI_BASE 0x0c |
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#define OPB_CLK_SYNC 0x3c |
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#define OPB_IRQ_CLEAR 0x40 |
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#define OPB_IRQ_MASK 0x44 |
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#define OPB_IRQ_STATUS 0x48 |
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#define OPB0_SELECT 0x10 |
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#define OPB0_RW 0x14 |
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#define OPB0_XFER_SIZE 0x18 |
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#define OPB0_FSI_ADDR 0x1c |
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#define OPB0_FSI_DATA_W 0x20 |
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#define OPB0_STATUS 0x80 |
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#define OPB0_FSI_DATA_R 0x84 |
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#define OPB0_WRITE_ORDER1 0x4c |
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#define OPB0_WRITE_ORDER2 0x50 |
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#define OPB1_WRITE_ORDER1 0x54 |
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#define OPB1_WRITE_ORDER2 0x58 |
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#define OPB0_READ_ORDER1 0x5c |
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#define OPB1_READ_ORDER2 0x60 |
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#define OPB_RETRY_COUNTER 0x64 |
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/* OPBn_STATUS */ |
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#define STATUS_HALFWORD_ACK BIT(0) |
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#define STATUS_FULLWORD_ACK BIT(1) |
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#define STATUS_ERR_ACK BIT(2) |
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#define STATUS_RETRY BIT(3) |
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#define STATUS_TIMEOUT BIT(4) |
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/* OPB_IRQ_MASK */ |
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#define OPB1_XFER_ACK_EN BIT(17) |
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#define OPB0_XFER_ACK_EN BIT(16) |
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/* OPB_RW */ |
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#define CMD_READ BIT(0) |
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#define CMD_WRITE 0 |
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/* OPBx_XFER_SIZE */ |
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#define XFER_FULLWORD (BIT(1) | BIT(0)) |
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#define XFER_HALFWORD (BIT(0)) |
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#define XFER_BYTE (0) |
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#define CREATE_TRACE_POINTS |
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#include <trace/events/fsi_master_aspeed.h> |
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#define FSI_LINK_ENABLE_SETUP_TIME 10 /* in mS */ |
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/* Run the bus at maximum speed by default */ |
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#define FSI_DIVISOR_DEFAULT 1 |
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#define FSI_DIVISOR_CABLED 2 |
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static u16 aspeed_fsi_divisor = FSI_DIVISOR_DEFAULT; |
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module_param_named(bus_div,aspeed_fsi_divisor, ushort, 0); |
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#define OPB_POLL_TIMEOUT 500 |
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static int __opb_write(struct fsi_master_aspeed *aspeed, u32 addr, |
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u32 val, u32 transfer_size) |
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{ |
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void __iomem *base = aspeed->base; |
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u32 reg, status; |
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int ret; |
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/* |
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* The ordering of these writes up until the trigger |
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* write does not matter, so use writel_relaxed. |
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*/ |
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writel_relaxed(CMD_WRITE, base + OPB0_RW); |
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writel_relaxed(transfer_size, base + OPB0_XFER_SIZE); |
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writel_relaxed(addr, base + OPB0_FSI_ADDR); |
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writel_relaxed(val, base + OPB0_FSI_DATA_W); |
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writel_relaxed(0x1, base + OPB_IRQ_CLEAR); |
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writel(0x1, base + OPB_TRIGGER); |
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ret = readl_poll_timeout(base + OPB_IRQ_STATUS, reg, |
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(reg & OPB0_XFER_ACK_EN) != 0, |
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0, OPB_POLL_TIMEOUT); |
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status = readl(base + OPB0_STATUS); |
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trace_fsi_master_aspeed_opb_write(addr, val, transfer_size, status, reg); |
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/* Return error when poll timed out */ |
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if (ret) |
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return ret; |
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/* Command failed, master will reset */ |
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if (status & STATUS_ERR_ACK) |
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return -EIO; |
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return 0; |
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} |
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static int opb_writeb(struct fsi_master_aspeed *aspeed, u32 addr, u8 val) |
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{ |
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return __opb_write(aspeed, addr, val, XFER_BYTE); |
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} |
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static int opb_writew(struct fsi_master_aspeed *aspeed, u32 addr, __be16 val) |
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{ |
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return __opb_write(aspeed, addr, (__force u16)val, XFER_HALFWORD); |
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} |
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static int opb_writel(struct fsi_master_aspeed *aspeed, u32 addr, __be32 val) |
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{ |
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return __opb_write(aspeed, addr, (__force u32)val, XFER_FULLWORD); |
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} |
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static int __opb_read(struct fsi_master_aspeed *aspeed, uint32_t addr, |
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u32 transfer_size, void *out) |
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{ |
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void __iomem *base = aspeed->base; |
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u32 result, reg; |
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int status, ret; |
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/* |
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* The ordering of these writes up until the trigger |
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* write does not matter, so use writel_relaxed. |
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*/ |
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writel_relaxed(CMD_READ, base + OPB0_RW); |
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writel_relaxed(transfer_size, base + OPB0_XFER_SIZE); |
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writel_relaxed(addr, base + OPB0_FSI_ADDR); |
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writel_relaxed(0x1, base + OPB_IRQ_CLEAR); |
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writel(0x1, base + OPB_TRIGGER); |
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ret = readl_poll_timeout(base + OPB_IRQ_STATUS, reg, |
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(reg & OPB0_XFER_ACK_EN) != 0, |
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0, OPB_POLL_TIMEOUT); |
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status = readl(base + OPB0_STATUS); |
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result = readl(base + OPB0_FSI_DATA_R); |
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trace_fsi_master_aspeed_opb_read(addr, transfer_size, result, |
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readl(base + OPB0_STATUS), |
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reg); |
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/* Return error when poll timed out */ |
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if (ret) |
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return ret; |
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/* Command failed, master will reset */ |
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if (status & STATUS_ERR_ACK) |
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return -EIO; |
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if (out) { |
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switch (transfer_size) { |
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case XFER_BYTE: |
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*(u8 *)out = result; |
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break; |
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case XFER_HALFWORD: |
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*(u16 *)out = result; |
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break; |
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case XFER_FULLWORD: |
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*(u32 *)out = result; |
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break; |
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default: |
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return -EINVAL; |
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} |
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} |
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return 0; |
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} |
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static int opb_readl(struct fsi_master_aspeed *aspeed, uint32_t addr, __be32 *out) |
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{ |
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return __opb_read(aspeed, addr, XFER_FULLWORD, out); |
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} |
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static int opb_readw(struct fsi_master_aspeed *aspeed, uint32_t addr, __be16 *out) |
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{ |
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return __opb_read(aspeed, addr, XFER_HALFWORD, (void *)out); |
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} |
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static int opb_readb(struct fsi_master_aspeed *aspeed, uint32_t addr, u8 *out) |
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{ |
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return __opb_read(aspeed, addr, XFER_BYTE, (void *)out); |
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} |
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static int check_errors(struct fsi_master_aspeed *aspeed, int err) |
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{ |
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int ret; |
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if (trace_fsi_master_aspeed_opb_error_enabled()) { |
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__be32 mresp0, mstap0, mesrb0; |
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opb_readl(aspeed, ctrl_base + FSI_MRESP0, &mresp0); |
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opb_readl(aspeed, ctrl_base + FSI_MSTAP0, &mstap0); |
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opb_readl(aspeed, ctrl_base + FSI_MESRB0, &mesrb0); |
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trace_fsi_master_aspeed_opb_error( |
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be32_to_cpu(mresp0), |
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be32_to_cpu(mstap0), |
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be32_to_cpu(mesrb0)); |
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} |
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if (err == -EIO) { |
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/* Check MAEB (0x70) ? */ |
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/* Then clear errors in master */ |
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ret = opb_writel(aspeed, ctrl_base + FSI_MRESP0, |
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cpu_to_be32(FSI_MRESP_RST_ALL_MASTER)); |
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if (ret) { |
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/* TODO: log? return different code? */ |
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return ret; |
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} |
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/* TODO: confirm that 0x70 was okay */ |
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} |
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/* This will pass through timeout errors */ |
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return err; |
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} |
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static int aspeed_master_read(struct fsi_master *master, int link, |
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uint8_t id, uint32_t addr, void *val, size_t size) |
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{ |
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struct fsi_master_aspeed *aspeed = to_fsi_master_aspeed(master); |
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int ret; |
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if (id > 0x3) |
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return -EINVAL; |
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addr |= id << 21; |
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addr += link * FSI_HUB_LINK_SIZE; |
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mutex_lock(&aspeed->lock); |
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switch (size) { |
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case 1: |
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ret = opb_readb(aspeed, fsi_base + addr, val); |
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break; |
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case 2: |
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ret = opb_readw(aspeed, fsi_base + addr, val); |
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break; |
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case 4: |
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ret = opb_readl(aspeed, fsi_base + addr, val); |
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break; |
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default: |
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ret = -EINVAL; |
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goto done; |
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} |
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ret = check_errors(aspeed, ret); |
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done: |
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mutex_unlock(&aspeed->lock); |
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return ret; |
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} |
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static int aspeed_master_write(struct fsi_master *master, int link, |
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uint8_t id, uint32_t addr, const void *val, size_t size) |
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{ |
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struct fsi_master_aspeed *aspeed = to_fsi_master_aspeed(master); |
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int ret; |
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if (id > 0x3) |
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return -EINVAL; |
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addr |= id << 21; |
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addr += link * FSI_HUB_LINK_SIZE; |
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mutex_lock(&aspeed->lock); |
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switch (size) { |
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case 1: |
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ret = opb_writeb(aspeed, fsi_base + addr, *(u8 *)val); |
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break; |
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case 2: |
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ret = opb_writew(aspeed, fsi_base + addr, *(__be16 *)val); |
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break; |
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case 4: |
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ret = opb_writel(aspeed, fsi_base + addr, *(__be32 *)val); |
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break; |
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default: |
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ret = -EINVAL; |
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goto done; |
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} |
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ret = check_errors(aspeed, ret); |
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done: |
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mutex_unlock(&aspeed->lock); |
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return ret; |
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} |
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static int aspeed_master_link_enable(struct fsi_master *master, int link, |
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bool enable) |
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{ |
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struct fsi_master_aspeed *aspeed = to_fsi_master_aspeed(master); |
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int idx, bit, ret; |
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__be32 reg; |
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idx = link / 32; |
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bit = link % 32; |
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reg = cpu_to_be32(0x80000000 >> bit); |
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mutex_lock(&aspeed->lock); |
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if (!enable) { |
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ret = opb_writel(aspeed, ctrl_base + FSI_MCENP0 + (4 * idx), reg); |
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goto done; |
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} |
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ret = opb_writel(aspeed, ctrl_base + FSI_MSENP0 + (4 * idx), reg); |
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if (ret) |
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goto done; |
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mdelay(FSI_LINK_ENABLE_SETUP_TIME); |
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done: |
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mutex_unlock(&aspeed->lock); |
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return ret; |
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} |
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static int aspeed_master_term(struct fsi_master *master, int link, uint8_t id) |
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{ |
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uint32_t addr; |
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__be32 cmd; |
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addr = 0x4; |
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cmd = cpu_to_be32(0xecc00000); |
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return aspeed_master_write(master, link, id, addr, &cmd, 4); |
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} |
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static int aspeed_master_break(struct fsi_master *master, int link) |
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{ |
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uint32_t addr; |
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__be32 cmd; |
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addr = 0x0; |
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cmd = cpu_to_be32(0xc0de0000); |
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return aspeed_master_write(master, link, 0, addr, &cmd, 4); |
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} |
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static void aspeed_master_release(struct device *dev) |
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{ |
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struct fsi_master_aspeed *aspeed = |
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to_fsi_master_aspeed(dev_to_fsi_master(dev)); |
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kfree(aspeed); |
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} |
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/* mmode encoders */ |
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static inline u32 fsi_mmode_crs0(u32 x) |
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{ |
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return (x & FSI_MMODE_CRS0MASK) << FSI_MMODE_CRS0SHFT; |
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} |
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static inline u32 fsi_mmode_crs1(u32 x) |
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{ |
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return (x & FSI_MMODE_CRS1MASK) << FSI_MMODE_CRS1SHFT; |
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} |
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static int aspeed_master_init(struct fsi_master_aspeed *aspeed) |
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{ |
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__be32 reg; |
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reg = cpu_to_be32(FSI_MRESP_RST_ALL_MASTER | FSI_MRESP_RST_ALL_LINK |
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| FSI_MRESP_RST_MCR | FSI_MRESP_RST_PYE); |
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opb_writel(aspeed, ctrl_base + FSI_MRESP0, reg); |
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/* Initialize the MFSI (hub master) engine */ |
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reg = cpu_to_be32(FSI_MRESP_RST_ALL_MASTER | FSI_MRESP_RST_ALL_LINK |
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| FSI_MRESP_RST_MCR | FSI_MRESP_RST_PYE); |
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opb_writel(aspeed, ctrl_base + FSI_MRESP0, reg); |
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reg = cpu_to_be32(FSI_MECTRL_EOAE | FSI_MECTRL_P8_AUTO_TERM); |
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opb_writel(aspeed, ctrl_base + FSI_MECTRL, reg); |
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reg = cpu_to_be32(FSI_MMODE_ECRC | FSI_MMODE_EPC | FSI_MMODE_RELA |
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| fsi_mmode_crs0(aspeed_fsi_divisor) |
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| fsi_mmode_crs1(aspeed_fsi_divisor) |
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| FSI_MMODE_P8_TO_LSB); |
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dev_info(aspeed->dev, "mmode set to %08x (divisor %d)\n", |
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be32_to_cpu(reg), aspeed_fsi_divisor); |
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opb_writel(aspeed, ctrl_base + FSI_MMODE, reg); |
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reg = cpu_to_be32(0xffff0000); |
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opb_writel(aspeed, ctrl_base + FSI_MDLYR, reg); |
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reg = cpu_to_be32(~0); |
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opb_writel(aspeed, ctrl_base + FSI_MSENP0, reg); |
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/* Leave enabled long enough for master logic to set up */ |
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mdelay(FSI_LINK_ENABLE_SETUP_TIME); |
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opb_writel(aspeed, ctrl_base + FSI_MCENP0, reg); |
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opb_readl(aspeed, ctrl_base + FSI_MAEB, NULL); |
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reg = cpu_to_be32(FSI_MRESP_RST_ALL_MASTER | FSI_MRESP_RST_ALL_LINK); |
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opb_writel(aspeed, ctrl_base + FSI_MRESP0, reg); |
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opb_readl(aspeed, ctrl_base + FSI_MLEVP0, NULL); |
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/* Reset the master bridge */ |
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reg = cpu_to_be32(FSI_MRESB_RST_GEN); |
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opb_writel(aspeed, ctrl_base + FSI_MRESB0, reg); |
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reg = cpu_to_be32(FSI_MRESB_RST_ERR); |
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opb_writel(aspeed, ctrl_base + FSI_MRESB0, reg); |
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return 0; |
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} |
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static ssize_t cfam_reset_store(struct device *dev, struct device_attribute *attr, |
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const char *buf, size_t count) |
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{ |
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struct fsi_master_aspeed *aspeed = dev_get_drvdata(dev); |
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mutex_lock(&aspeed->lock); |
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gpiod_set_value(aspeed->cfam_reset_gpio, 1); |
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usleep_range(900, 1000); |
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gpiod_set_value(aspeed->cfam_reset_gpio, 0); |
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mutex_unlock(&aspeed->lock); |
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return count; |
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} |
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static DEVICE_ATTR(cfam_reset, 0200, NULL, cfam_reset_store); |
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static int setup_cfam_reset(struct fsi_master_aspeed *aspeed) |
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{ |
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struct device *dev = aspeed->dev; |
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struct gpio_desc *gpio; |
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int rc; |
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gpio = devm_gpiod_get_optional(dev, "cfam-reset", GPIOD_OUT_LOW); |
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if (IS_ERR(gpio)) |
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return PTR_ERR(gpio); |
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if (!gpio) |
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return 0; |
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aspeed->cfam_reset_gpio = gpio; |
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rc = device_create_file(dev, &dev_attr_cfam_reset); |
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if (rc) { |
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devm_gpiod_put(dev, gpio); |
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return rc; |
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} |
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return 0; |
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} |
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static int tacoma_cabled_fsi_fixup(struct device *dev) |
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{ |
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struct gpio_desc *routing_gpio, *mux_gpio; |
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int gpio; |
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/* |
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* The routing GPIO is a jumper indicating we should mux for the |
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* externally connected FSI cable. |
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*/ |
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routing_gpio = devm_gpiod_get_optional(dev, "fsi-routing", |
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GPIOD_IN | GPIOD_FLAGS_BIT_NONEXCLUSIVE); |
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if (IS_ERR(routing_gpio)) |
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return PTR_ERR(routing_gpio); |
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if (!routing_gpio) |
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return 0; |
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mux_gpio = devm_gpiod_get_optional(dev, "fsi-mux", GPIOD_ASIS); |
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if (IS_ERR(mux_gpio)) |
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return PTR_ERR(mux_gpio); |
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if (!mux_gpio) |
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return 0; |
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gpio = gpiod_get_value(routing_gpio); |
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if (gpio < 0) |
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return gpio; |
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|
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/* If the routing GPIO is high we should set the mux to low. */ |
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if (gpio) { |
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/* |
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* Cable signal integrity means we should run the bus |
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* slightly slower. Do not override if a kernel param |
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* has already overridden. |
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*/ |
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if (aspeed_fsi_divisor == FSI_DIVISOR_DEFAULT) |
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aspeed_fsi_divisor = FSI_DIVISOR_CABLED; |
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gpiod_direction_output(mux_gpio, 0); |
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dev_info(dev, "FSI configured for external cable\n"); |
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} else { |
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gpiod_direction_output(mux_gpio, 1); |
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} |
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devm_gpiod_put(dev, routing_gpio); |
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return 0; |
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} |
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static int fsi_master_aspeed_probe(struct platform_device *pdev) |
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{ |
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struct fsi_master_aspeed *aspeed; |
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int rc, links, reg; |
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__be32 raw; |
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rc = tacoma_cabled_fsi_fixup(&pdev->dev); |
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if (rc) { |
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dev_err(&pdev->dev, "Tacoma FSI cable fixup failed\n"); |
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return rc; |
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} |
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|
|
aspeed = devm_kzalloc(&pdev->dev, sizeof(*aspeed), GFP_KERNEL); |
|
if (!aspeed) |
|
return -ENOMEM; |
|
|
|
aspeed->dev = &pdev->dev; |
|
|
|
aspeed->base = devm_platform_ioremap_resource(pdev, 0); |
|
if (IS_ERR(aspeed->base)) |
|
return PTR_ERR(aspeed->base); |
|
|
|
aspeed->clk = devm_clk_get(aspeed->dev, NULL); |
|
if (IS_ERR(aspeed->clk)) { |
|
dev_err(aspeed->dev, "couldn't get clock\n"); |
|
return PTR_ERR(aspeed->clk); |
|
} |
|
rc = clk_prepare_enable(aspeed->clk); |
|
if (rc) { |
|
dev_err(aspeed->dev, "couldn't enable clock\n"); |
|
return rc; |
|
} |
|
|
|
rc = setup_cfam_reset(aspeed); |
|
if (rc) { |
|
dev_err(&pdev->dev, "CFAM reset GPIO setup failed\n"); |
|
} |
|
|
|
writel(0x1, aspeed->base + OPB_CLK_SYNC); |
|
writel(OPB1_XFER_ACK_EN | OPB0_XFER_ACK_EN, |
|
aspeed->base + OPB_IRQ_MASK); |
|
|
|
/* TODO: determine an appropriate value */ |
|
writel(0x10, aspeed->base + OPB_RETRY_COUNTER); |
|
|
|
writel(ctrl_base, aspeed->base + OPB_CTRL_BASE); |
|
writel(fsi_base, aspeed->base + OPB_FSI_BASE); |
|
|
|
/* Set read data order */ |
|
writel(0x00030b1b, aspeed->base + OPB0_READ_ORDER1); |
|
|
|
/* Set write data order */ |
|
writel(0x0011101b, aspeed->base + OPB0_WRITE_ORDER1); |
|
writel(0x0c330f3f, aspeed->base + OPB0_WRITE_ORDER2); |
|
|
|
/* |
|
* Select OPB0 for all operations. |
|
* Will need to be reworked when enabling DMA or anything that uses |
|
* OPB1. |
|
*/ |
|
writel(0x1, aspeed->base + OPB0_SELECT); |
|
|
|
rc = opb_readl(aspeed, ctrl_base + FSI_MVER, &raw); |
|
if (rc) { |
|
dev_err(&pdev->dev, "failed to read hub version\n"); |
|
return rc; |
|
} |
|
|
|
reg = be32_to_cpu(raw); |
|
links = (reg >> 8) & 0xff; |
|
dev_info(&pdev->dev, "hub version %08x (%d links)\n", reg, links); |
|
|
|
aspeed->master.dev.parent = &pdev->dev; |
|
aspeed->master.dev.release = aspeed_master_release; |
|
aspeed->master.dev.of_node = of_node_get(dev_of_node(&pdev->dev)); |
|
|
|
aspeed->master.n_links = links; |
|
aspeed->master.read = aspeed_master_read; |
|
aspeed->master.write = aspeed_master_write; |
|
aspeed->master.send_break = aspeed_master_break; |
|
aspeed->master.term = aspeed_master_term; |
|
aspeed->master.link_enable = aspeed_master_link_enable; |
|
|
|
dev_set_drvdata(&pdev->dev, aspeed); |
|
|
|
mutex_init(&aspeed->lock); |
|
aspeed_master_init(aspeed); |
|
|
|
rc = fsi_master_register(&aspeed->master); |
|
if (rc) |
|
goto err_release; |
|
|
|
/* At this point, fsi_master_register performs the device_initialize(), |
|
* and holds the sole reference on master.dev. This means the device |
|
* will be freed (via ->release) during any subsequent call to |
|
* fsi_master_unregister. We add our own reference to it here, so we |
|
* can perform cleanup (in _remove()) without it being freed before |
|
* we're ready. |
|
*/ |
|
get_device(&aspeed->master.dev); |
|
return 0; |
|
|
|
err_release: |
|
clk_disable_unprepare(aspeed->clk); |
|
return rc; |
|
} |
|
|
|
static int fsi_master_aspeed_remove(struct platform_device *pdev) |
|
{ |
|
struct fsi_master_aspeed *aspeed = platform_get_drvdata(pdev); |
|
|
|
fsi_master_unregister(&aspeed->master); |
|
clk_disable_unprepare(aspeed->clk); |
|
|
|
return 0; |
|
} |
|
|
|
static const struct of_device_id fsi_master_aspeed_match[] = { |
|
{ .compatible = "aspeed,ast2600-fsi-master" }, |
|
{ }, |
|
}; |
|
MODULE_DEVICE_TABLE(of, fsi_master_aspeed_match); |
|
|
|
static struct platform_driver fsi_master_aspeed_driver = { |
|
.driver = { |
|
.name = "fsi-master-aspeed", |
|
.of_match_table = fsi_master_aspeed_match, |
|
}, |
|
.probe = fsi_master_aspeed_probe, |
|
.remove = fsi_master_aspeed_remove, |
|
}; |
|
|
|
module_platform_driver(fsi_master_aspeed_driver); |
|
MODULE_LICENSE("GPL");
|
|
|