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343 lines
8.6 KiB
343 lines
8.6 KiB
// SPDX-License-Identifier: GPL-2.0 |
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/* |
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* Copyright (C) 2017 Texas Instruments Incorporated - https://www.ti.com/ |
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* |
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* Texas Instruments DDR3 ECC error correction and detection driver |
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* |
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* This program is free software; you can redistribute it and/or modify it |
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* under the terms and conditions of the GNU General Public License, |
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* version 2, as published by the Free Software Foundation. |
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* |
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* This program is distributed in the hope it will be useful, but WITHOUT |
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
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* more details. |
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* |
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* You should have received a copy of the GNU General Public License along with |
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* this program. If not, see <http://www.gnu.org/licenses/>. |
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*/ |
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#include <linux/init.h> |
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#include <linux/edac.h> |
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#include <linux/io.h> |
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#include <linux/interrupt.h> |
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#include <linux/of_address.h> |
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#include <linux/of_device.h> |
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#include <linux/module.h> |
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#include "edac_module.h" |
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/* EMIF controller registers */ |
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#define EMIF_SDRAM_CONFIG 0x008 |
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#define EMIF_IRQ_STATUS 0x0ac |
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#define EMIF_IRQ_ENABLE_SET 0x0b4 |
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#define EMIF_ECC_CTRL 0x110 |
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#define EMIF_1B_ECC_ERR_CNT 0x130 |
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#define EMIF_1B_ECC_ERR_THRSH 0x134 |
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#define EMIF_1B_ECC_ERR_ADDR_LOG 0x13c |
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#define EMIF_2B_ECC_ERR_ADDR_LOG 0x140 |
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/* Bit definitions for EMIF_SDRAM_CONFIG */ |
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#define SDRAM_TYPE_SHIFT 29 |
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#define SDRAM_TYPE_MASK GENMASK(31, 29) |
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#define SDRAM_TYPE_DDR3 (3 << SDRAM_TYPE_SHIFT) |
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#define SDRAM_TYPE_DDR2 (2 << SDRAM_TYPE_SHIFT) |
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#define SDRAM_NARROW_MODE_MASK GENMASK(15, 14) |
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#define SDRAM_K2_NARROW_MODE_SHIFT 12 |
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#define SDRAM_K2_NARROW_MODE_MASK GENMASK(13, 12) |
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#define SDRAM_ROWSIZE_SHIFT 7 |
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#define SDRAM_ROWSIZE_MASK GENMASK(9, 7) |
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#define SDRAM_IBANK_SHIFT 4 |
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#define SDRAM_IBANK_MASK GENMASK(6, 4) |
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#define SDRAM_K2_IBANK_SHIFT 5 |
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#define SDRAM_K2_IBANK_MASK GENMASK(6, 5) |
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#define SDRAM_K2_EBANK_SHIFT 3 |
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#define SDRAM_K2_EBANK_MASK BIT(SDRAM_K2_EBANK_SHIFT) |
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#define SDRAM_PAGESIZE_SHIFT 0 |
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#define SDRAM_PAGESIZE_MASK GENMASK(2, 0) |
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#define SDRAM_K2_PAGESIZE_SHIFT 0 |
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#define SDRAM_K2_PAGESIZE_MASK GENMASK(1, 0) |
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#define EMIF_1B_ECC_ERR_THRSH_SHIFT 24 |
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/* IRQ bit definitions */ |
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#define EMIF_1B_ECC_ERR BIT(5) |
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#define EMIF_2B_ECC_ERR BIT(4) |
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#define EMIF_WR_ECC_ERR BIT(3) |
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#define EMIF_SYS_ERR BIT(0) |
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/* Bit 31 enables ECC and 28 enables RMW */ |
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#define ECC_ENABLED (BIT(31) | BIT(28)) |
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#define EDAC_MOD_NAME "ti-emif-edac" |
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enum { |
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EMIF_TYPE_DRA7, |
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EMIF_TYPE_K2 |
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}; |
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struct ti_edac { |
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void __iomem *reg; |
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}; |
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static u32 ti_edac_readl(struct ti_edac *edac, u16 offset) |
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{ |
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return readl_relaxed(edac->reg + offset); |
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} |
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static void ti_edac_writel(struct ti_edac *edac, u32 val, u16 offset) |
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{ |
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writel_relaxed(val, edac->reg + offset); |
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} |
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static irqreturn_t ti_edac_isr(int irq, void *data) |
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{ |
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struct mem_ctl_info *mci = data; |
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struct ti_edac *edac = mci->pvt_info; |
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u32 irq_status; |
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u32 err_addr; |
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int err_count; |
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irq_status = ti_edac_readl(edac, EMIF_IRQ_STATUS); |
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if (irq_status & EMIF_1B_ECC_ERR) { |
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err_addr = ti_edac_readl(edac, EMIF_1B_ECC_ERR_ADDR_LOG); |
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err_count = ti_edac_readl(edac, EMIF_1B_ECC_ERR_CNT); |
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ti_edac_writel(edac, err_count, EMIF_1B_ECC_ERR_CNT); |
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edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, err_count, |
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err_addr >> PAGE_SHIFT, |
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err_addr & ~PAGE_MASK, -1, 0, 0, 0, |
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mci->ctl_name, "1B"); |
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} |
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if (irq_status & EMIF_2B_ECC_ERR) { |
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err_addr = ti_edac_readl(edac, EMIF_2B_ECC_ERR_ADDR_LOG); |
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edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1, |
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err_addr >> PAGE_SHIFT, |
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err_addr & ~PAGE_MASK, -1, 0, 0, 0, |
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mci->ctl_name, "2B"); |
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} |
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if (irq_status & EMIF_WR_ECC_ERR) |
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edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1, |
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0, 0, -1, 0, 0, 0, |
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mci->ctl_name, "WR"); |
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ti_edac_writel(edac, irq_status, EMIF_IRQ_STATUS); |
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return IRQ_HANDLED; |
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} |
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static void ti_edac_setup_dimm(struct mem_ctl_info *mci, u32 type) |
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{ |
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struct dimm_info *dimm; |
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struct ti_edac *edac = mci->pvt_info; |
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int bits; |
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u32 val; |
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u32 memsize; |
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dimm = edac_get_dimm(mci, 0, 0, 0); |
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val = ti_edac_readl(edac, EMIF_SDRAM_CONFIG); |
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if (type == EMIF_TYPE_DRA7) { |
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bits = ((val & SDRAM_PAGESIZE_MASK) >> SDRAM_PAGESIZE_SHIFT) + 8; |
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bits += ((val & SDRAM_ROWSIZE_MASK) >> SDRAM_ROWSIZE_SHIFT) + 9; |
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bits += (val & SDRAM_IBANK_MASK) >> SDRAM_IBANK_SHIFT; |
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if (val & SDRAM_NARROW_MODE_MASK) { |
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bits++; |
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dimm->dtype = DEV_X16; |
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} else { |
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bits += 2; |
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dimm->dtype = DEV_X32; |
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} |
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} else { |
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bits = 16; |
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bits += ((val & SDRAM_K2_PAGESIZE_MASK) >> |
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SDRAM_K2_PAGESIZE_SHIFT) + 8; |
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bits += (val & SDRAM_K2_IBANK_MASK) >> SDRAM_K2_IBANK_SHIFT; |
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bits += (val & SDRAM_K2_EBANK_MASK) >> SDRAM_K2_EBANK_SHIFT; |
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val = (val & SDRAM_K2_NARROW_MODE_MASK) >> |
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SDRAM_K2_NARROW_MODE_SHIFT; |
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switch (val) { |
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case 0: |
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bits += 3; |
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dimm->dtype = DEV_X64; |
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break; |
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case 1: |
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bits += 2; |
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dimm->dtype = DEV_X32; |
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break; |
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case 2: |
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bits++; |
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dimm->dtype = DEV_X16; |
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break; |
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} |
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} |
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memsize = 1 << bits; |
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dimm->nr_pages = memsize >> PAGE_SHIFT; |
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dimm->grain = 4; |
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if ((val & SDRAM_TYPE_MASK) == SDRAM_TYPE_DDR2) |
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dimm->mtype = MEM_DDR2; |
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else |
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dimm->mtype = MEM_DDR3; |
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val = ti_edac_readl(edac, EMIF_ECC_CTRL); |
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if (val & ECC_ENABLED) |
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dimm->edac_mode = EDAC_SECDED; |
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else |
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dimm->edac_mode = EDAC_NONE; |
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} |
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static const struct of_device_id ti_edac_of_match[] = { |
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{ .compatible = "ti,emif-keystone", .data = (void *)EMIF_TYPE_K2 }, |
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{ .compatible = "ti,emif-dra7xx", .data = (void *)EMIF_TYPE_DRA7 }, |
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{}, |
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}; |
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MODULE_DEVICE_TABLE(of, ti_edac_of_match); |
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static int _emif_get_id(struct device_node *node) |
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{ |
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struct device_node *np; |
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const __be32 *addrp; |
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u32 addr, my_addr; |
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int my_id = 0; |
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addrp = of_get_address(node, 0, NULL, NULL); |
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my_addr = (u32)of_translate_address(node, addrp); |
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for_each_matching_node(np, ti_edac_of_match) { |
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if (np == node) |
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continue; |
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addrp = of_get_address(np, 0, NULL, NULL); |
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addr = (u32)of_translate_address(np, addrp); |
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edac_printk(KERN_INFO, EDAC_MOD_NAME, |
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"addr=%x, my_addr=%x\n", |
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addr, my_addr); |
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if (addr < my_addr) |
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my_id++; |
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} |
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return my_id; |
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} |
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static int ti_edac_probe(struct platform_device *pdev) |
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{ |
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int error_irq = 0, ret = -ENODEV; |
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struct device *dev = &pdev->dev; |
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struct resource *res; |
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void __iomem *reg; |
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struct mem_ctl_info *mci; |
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struct edac_mc_layer layers[1]; |
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const struct of_device_id *id; |
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struct ti_edac *edac; |
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int emif_id; |
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id = of_match_device(ti_edac_of_match, &pdev->dev); |
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if (!id) |
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return -ENODEV; |
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
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reg = devm_ioremap_resource(dev, res); |
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if (IS_ERR(reg)) { |
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edac_printk(KERN_ERR, EDAC_MOD_NAME, |
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"EMIF controller regs not defined\n"); |
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return PTR_ERR(reg); |
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} |
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layers[0].type = EDAC_MC_LAYER_ALL_MEM; |
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layers[0].size = 1; |
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/* Allocate ID number for our EMIF controller */ |
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emif_id = _emif_get_id(pdev->dev.of_node); |
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if (emif_id < 0) |
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return -EINVAL; |
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mci = edac_mc_alloc(emif_id, 1, layers, sizeof(*edac)); |
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if (!mci) |
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return -ENOMEM; |
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mci->pdev = &pdev->dev; |
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edac = mci->pvt_info; |
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edac->reg = reg; |
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platform_set_drvdata(pdev, mci); |
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mci->mtype_cap = MEM_FLAG_DDR3 | MEM_FLAG_DDR2; |
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mci->edac_ctl_cap = EDAC_FLAG_SECDED | EDAC_FLAG_NONE; |
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mci->mod_name = EDAC_MOD_NAME; |
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mci->ctl_name = id->compatible; |
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mci->dev_name = dev_name(&pdev->dev); |
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/* Setup memory layout */ |
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ti_edac_setup_dimm(mci, (u32)(id->data)); |
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/* add EMIF ECC error handler */ |
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error_irq = platform_get_irq(pdev, 0); |
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if (error_irq < 0) { |
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ret = error_irq; |
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edac_printk(KERN_ERR, EDAC_MOD_NAME, |
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"EMIF irq number not defined.\n"); |
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goto err; |
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} |
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ret = devm_request_irq(dev, error_irq, ti_edac_isr, 0, |
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"emif-edac-irq", mci); |
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if (ret) { |
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edac_printk(KERN_ERR, EDAC_MOD_NAME, |
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"request_irq fail for EMIF EDAC irq\n"); |
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goto err; |
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} |
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ret = edac_mc_add_mc(mci); |
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if (ret) { |
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edac_printk(KERN_ERR, EDAC_MOD_NAME, |
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"Failed to register mci: %d.\n", ret); |
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goto err; |
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} |
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/* Generate an interrupt with each 1b error */ |
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ti_edac_writel(edac, 1 << EMIF_1B_ECC_ERR_THRSH_SHIFT, |
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EMIF_1B_ECC_ERR_THRSH); |
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/* Enable interrupts */ |
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ti_edac_writel(edac, |
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EMIF_1B_ECC_ERR | EMIF_2B_ECC_ERR | EMIF_WR_ECC_ERR, |
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EMIF_IRQ_ENABLE_SET); |
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return 0; |
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err: |
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edac_mc_free(mci); |
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return ret; |
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} |
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static int ti_edac_remove(struct platform_device *pdev) |
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{ |
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struct mem_ctl_info *mci = platform_get_drvdata(pdev); |
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edac_mc_del_mc(&pdev->dev); |
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edac_mc_free(mci); |
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return 0; |
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} |
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static struct platform_driver ti_edac_driver = { |
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.probe = ti_edac_probe, |
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.remove = ti_edac_remove, |
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.driver = { |
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.name = EDAC_MOD_NAME, |
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.of_match_table = ti_edac_of_match, |
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}, |
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}; |
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module_platform_driver(ti_edac_driver); |
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MODULE_AUTHOR("Texas Instruments Inc."); |
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MODULE_DESCRIPTION("EDAC Driver for Texas Instruments DDR3 MC"); |
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MODULE_LICENSE("GPL v2");
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