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462 lines
14 KiB
462 lines
14 KiB
/* |
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* Intel 82443BX/GX (440BX/GX chipset) Memory Controller EDAC kernel |
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* module (C) 2006 Tim Small |
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* |
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* This file may be distributed under the terms of the GNU General |
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* Public License. |
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* |
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* Written by Tim Small <[email protected]>, based on work by Linux |
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* Networx, Thayne Harbaugh, Dan Hollis <goemon at anime dot net> and |
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* others. |
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* |
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* 440GX fix by Jason Uhlenkott <[email protected]>. |
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* |
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* Written with reference to 82443BX Host Bridge Datasheet: |
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* http://download.intel.com/design/chipsets/datashts/29063301.pdf |
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* references to this document given in []. |
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* |
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* This module doesn't support the 440LX, but it may be possible to |
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* make it do so (the 440LX's register definitions are different, but |
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* not completely so - I haven't studied them in enough detail to know |
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* how easy this would be). |
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*/ |
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#include <linux/module.h> |
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#include <linux/init.h> |
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#include <linux/pci.h> |
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#include <linux/pci_ids.h> |
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#include <linux/edac.h> |
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#include "edac_module.h" |
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#define EDAC_MOD_STR "i82443bxgx_edac" |
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/* The 82443BX supports SDRAM, or EDO (EDO for mobile only), "Memory |
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* Size: 8 MB to 512 MB (1GB with Registered DIMMs) with eight memory |
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* rows" "The 82443BX supports multiple-bit error detection and |
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* single-bit error correction when ECC mode is enabled and |
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* single/multi-bit error detection when correction is disabled. |
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* During writes to the DRAM, the 82443BX generates ECC for the data |
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* on a QWord basis. Partial QWord writes require a read-modify-write |
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* cycle when ECC is enabled." |
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*/ |
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|
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/* "Additionally, the 82443BX ensures that the data is corrected in |
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* main memory so that accumulation of errors is prevented. Another |
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* error within the same QWord would result in a double-bit error |
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* which is unrecoverable. This is known as hardware scrubbing since |
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* it requires no software intervention to correct the data in memory." |
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*/ |
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/* [Also see page 100 (section 4.3), "DRAM Interface"] |
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* [Also see page 112 (section 4.6.1.4), ECC] |
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*/ |
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#define I82443BXGX_NR_CSROWS 8 |
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#define I82443BXGX_NR_CHANS 1 |
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#define I82443BXGX_NR_DIMMS 4 |
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|
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/* 82443 PCI Device 0 */ |
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#define I82443BXGX_NBXCFG 0x50 /* 32bit register starting at this PCI |
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* config space offset */ |
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#define I82443BXGX_NBXCFG_OFFSET_NON_ECCROW 24 /* Array of bits, zero if |
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* row is non-ECC */ |
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#define I82443BXGX_NBXCFG_OFFSET_DRAM_FREQ 12 /* 2 bits,00=100MHz,10=66 MHz */ |
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#define I82443BXGX_NBXCFG_OFFSET_DRAM_INTEGRITY 7 /* 2 bits: */ |
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#define I82443BXGX_NBXCFG_INTEGRITY_NONE 0x0 /* 00 = Non-ECC */ |
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#define I82443BXGX_NBXCFG_INTEGRITY_EC 0x1 /* 01 = EC (only) */ |
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#define I82443BXGX_NBXCFG_INTEGRITY_ECC 0x2 /* 10 = ECC */ |
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#define I82443BXGX_NBXCFG_INTEGRITY_SCRUB 0x3 /* 11 = ECC + HW Scrub */ |
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#define I82443BXGX_NBXCFG_OFFSET_ECC_DIAG_ENABLE 6 |
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|
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/* 82443 PCI Device 0 */ |
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#define I82443BXGX_EAP 0x80 /* 32bit register starting at this PCI |
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* config space offset, Error Address |
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* Pointer Register */ |
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#define I82443BXGX_EAP_OFFSET_EAP 12 /* High 20 bits of error address */ |
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#define I82443BXGX_EAP_OFFSET_MBE BIT(1) /* Err at EAP was multi-bit (W1TC) */ |
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#define I82443BXGX_EAP_OFFSET_SBE BIT(0) /* Err at EAP was single-bit (W1TC) */ |
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#define I82443BXGX_ERRCMD 0x90 /* 8bit register starting at this PCI |
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* config space offset. */ |
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#define I82443BXGX_ERRCMD_OFFSET_SERR_ON_MBE BIT(1) /* 1 = enable */ |
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#define I82443BXGX_ERRCMD_OFFSET_SERR_ON_SBE BIT(0) /* 1 = enable */ |
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#define I82443BXGX_ERRSTS 0x91 /* 16bit register starting at this PCI |
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* config space offset. */ |
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#define I82443BXGX_ERRSTS_OFFSET_MBFRE 5 /* 3 bits - first err row multibit */ |
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#define I82443BXGX_ERRSTS_OFFSET_MEF BIT(4) /* 1 = MBE occurred */ |
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#define I82443BXGX_ERRSTS_OFFSET_SBFRE 1 /* 3 bits - first err row singlebit */ |
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#define I82443BXGX_ERRSTS_OFFSET_SEF BIT(0) /* 1 = SBE occurred */ |
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#define I82443BXGX_DRAMC 0x57 /* 8bit register starting at this PCI |
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* config space offset. */ |
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#define I82443BXGX_DRAMC_OFFSET_DT 3 /* 2 bits, DRAM Type */ |
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#define I82443BXGX_DRAMC_DRAM_IS_EDO 0 /* 00 = EDO */ |
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#define I82443BXGX_DRAMC_DRAM_IS_SDRAM 1 /* 01 = SDRAM */ |
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#define I82443BXGX_DRAMC_DRAM_IS_RSDRAM 2 /* 10 = Registered SDRAM */ |
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#define I82443BXGX_DRB 0x60 /* 8x 8bit registers starting at this PCI |
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* config space offset. */ |
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/* FIXME - don't poll when ECC disabled? */ |
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struct i82443bxgx_edacmc_error_info { |
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u32 eap; |
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}; |
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static struct edac_pci_ctl_info *i82443bxgx_pci; |
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static struct pci_dev *mci_pdev; /* init dev: in case that AGP code has |
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* already registered driver |
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*/ |
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static int i82443bxgx_registered = 1; |
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static void i82443bxgx_edacmc_get_error_info(struct mem_ctl_info *mci, |
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struct i82443bxgx_edacmc_error_info |
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*info) |
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{ |
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struct pci_dev *pdev; |
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pdev = to_pci_dev(mci->pdev); |
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pci_read_config_dword(pdev, I82443BXGX_EAP, &info->eap); |
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if (info->eap & I82443BXGX_EAP_OFFSET_SBE) |
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/* Clear error to allow next error to be reported [p.61] */ |
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pci_write_bits32(pdev, I82443BXGX_EAP, |
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I82443BXGX_EAP_OFFSET_SBE, |
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I82443BXGX_EAP_OFFSET_SBE); |
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if (info->eap & I82443BXGX_EAP_OFFSET_MBE) |
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/* Clear error to allow next error to be reported [p.61] */ |
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pci_write_bits32(pdev, I82443BXGX_EAP, |
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I82443BXGX_EAP_OFFSET_MBE, |
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I82443BXGX_EAP_OFFSET_MBE); |
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} |
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static int i82443bxgx_edacmc_process_error_info(struct mem_ctl_info *mci, |
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struct |
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i82443bxgx_edacmc_error_info |
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*info, int handle_errors) |
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{ |
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int error_found = 0; |
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u32 eapaddr, page, pageoffset; |
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|
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/* bits 30:12 hold the 4kb block in which the error occurred |
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* [p.61] */ |
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eapaddr = (info->eap & 0xfffff000); |
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page = eapaddr >> PAGE_SHIFT; |
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pageoffset = eapaddr - (page << PAGE_SHIFT); |
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if (info->eap & I82443BXGX_EAP_OFFSET_SBE) { |
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error_found = 1; |
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if (handle_errors) |
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edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, 1, |
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page, pageoffset, 0, |
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edac_mc_find_csrow_by_page(mci, page), |
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0, -1, mci->ctl_name, ""); |
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} |
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if (info->eap & I82443BXGX_EAP_OFFSET_MBE) { |
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error_found = 1; |
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if (handle_errors) |
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edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1, |
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page, pageoffset, 0, |
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edac_mc_find_csrow_by_page(mci, page), |
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0, -1, mci->ctl_name, ""); |
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} |
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return error_found; |
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} |
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static void i82443bxgx_edacmc_check(struct mem_ctl_info *mci) |
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{ |
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struct i82443bxgx_edacmc_error_info info; |
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i82443bxgx_edacmc_get_error_info(mci, &info); |
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i82443bxgx_edacmc_process_error_info(mci, &info, 1); |
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} |
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static void i82443bxgx_init_csrows(struct mem_ctl_info *mci, |
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struct pci_dev *pdev, |
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enum edac_type edac_mode, |
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enum mem_type mtype) |
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{ |
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struct csrow_info *csrow; |
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struct dimm_info *dimm; |
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int index; |
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u8 drbar, dramc; |
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u32 row_base, row_high_limit, row_high_limit_last; |
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pci_read_config_byte(pdev, I82443BXGX_DRAMC, &dramc); |
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row_high_limit_last = 0; |
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for (index = 0; index < mci->nr_csrows; index++) { |
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csrow = mci->csrows[index]; |
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dimm = csrow->channels[0]->dimm; |
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pci_read_config_byte(pdev, I82443BXGX_DRB + index, &drbar); |
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edac_dbg(1, "MC%d: Row=%d DRB = %#0x\n", |
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mci->mc_idx, index, drbar); |
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row_high_limit = ((u32) drbar << 23); |
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/* find the DRAM Chip Select Base address and mask */ |
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edac_dbg(1, "MC%d: Row=%d, Boundary Address=%#0x, Last = %#0x\n", |
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mci->mc_idx, index, row_high_limit, |
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row_high_limit_last); |
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/* 440GX goes to 2GB, represented with a DRB of 0. */ |
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if (row_high_limit_last && !row_high_limit) |
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row_high_limit = 1UL << 31; |
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/* This row is empty [p.49] */ |
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if (row_high_limit == row_high_limit_last) |
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continue; |
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row_base = row_high_limit_last; |
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csrow->first_page = row_base >> PAGE_SHIFT; |
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csrow->last_page = (row_high_limit >> PAGE_SHIFT) - 1; |
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dimm->nr_pages = csrow->last_page - csrow->first_page + 1; |
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/* EAP reports in 4kilobyte granularity [61] */ |
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dimm->grain = 1 << 12; |
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dimm->mtype = mtype; |
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/* I don't think 440BX can tell you device type? FIXME? */ |
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dimm->dtype = DEV_UNKNOWN; |
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/* Mode is global to all rows on 440BX */ |
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dimm->edac_mode = edac_mode; |
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row_high_limit_last = row_high_limit; |
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} |
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} |
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static int i82443bxgx_edacmc_probe1(struct pci_dev *pdev, int dev_idx) |
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{ |
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struct mem_ctl_info *mci; |
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struct edac_mc_layer layers[2]; |
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u8 dramc; |
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u32 nbxcfg, ecc_mode; |
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enum mem_type mtype; |
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enum edac_type edac_mode; |
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edac_dbg(0, "MC:\n"); |
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/* Something is really hosed if PCI config space reads from |
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* the MC aren't working. |
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*/ |
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if (pci_read_config_dword(pdev, I82443BXGX_NBXCFG, &nbxcfg)) |
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return -EIO; |
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layers[0].type = EDAC_MC_LAYER_CHIP_SELECT; |
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layers[0].size = I82443BXGX_NR_CSROWS; |
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layers[0].is_virt_csrow = true; |
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layers[1].type = EDAC_MC_LAYER_CHANNEL; |
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layers[1].size = I82443BXGX_NR_CHANS; |
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layers[1].is_virt_csrow = false; |
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mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, 0); |
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if (mci == NULL) |
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return -ENOMEM; |
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edac_dbg(0, "MC: mci = %p\n", mci); |
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mci->pdev = &pdev->dev; |
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mci->mtype_cap = MEM_FLAG_EDO | MEM_FLAG_SDR | MEM_FLAG_RDR; |
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mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_EC | EDAC_FLAG_SECDED; |
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pci_read_config_byte(pdev, I82443BXGX_DRAMC, &dramc); |
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switch ((dramc >> I82443BXGX_DRAMC_OFFSET_DT) & (BIT(0) | BIT(1))) { |
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case I82443BXGX_DRAMC_DRAM_IS_EDO: |
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mtype = MEM_EDO; |
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break; |
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case I82443BXGX_DRAMC_DRAM_IS_SDRAM: |
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mtype = MEM_SDR; |
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break; |
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case I82443BXGX_DRAMC_DRAM_IS_RSDRAM: |
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mtype = MEM_RDR; |
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break; |
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default: |
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edac_dbg(0, "Unknown/reserved DRAM type value in DRAMC register!\n"); |
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mtype = -MEM_UNKNOWN; |
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} |
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if ((mtype == MEM_SDR) || (mtype == MEM_RDR)) |
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mci->edac_cap = mci->edac_ctl_cap; |
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else |
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mci->edac_cap = EDAC_FLAG_NONE; |
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mci->scrub_cap = SCRUB_FLAG_HW_SRC; |
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pci_read_config_dword(pdev, I82443BXGX_NBXCFG, &nbxcfg); |
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ecc_mode = ((nbxcfg >> I82443BXGX_NBXCFG_OFFSET_DRAM_INTEGRITY) & |
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(BIT(0) | BIT(1))); |
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mci->scrub_mode = (ecc_mode == I82443BXGX_NBXCFG_INTEGRITY_SCRUB) |
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? SCRUB_HW_SRC : SCRUB_NONE; |
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switch (ecc_mode) { |
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case I82443BXGX_NBXCFG_INTEGRITY_NONE: |
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edac_mode = EDAC_NONE; |
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break; |
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case I82443BXGX_NBXCFG_INTEGRITY_EC: |
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edac_mode = EDAC_EC; |
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break; |
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case I82443BXGX_NBXCFG_INTEGRITY_ECC: |
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case I82443BXGX_NBXCFG_INTEGRITY_SCRUB: |
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edac_mode = EDAC_SECDED; |
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break; |
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default: |
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edac_dbg(0, "Unknown/reserved ECC state in NBXCFG register!\n"); |
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edac_mode = EDAC_UNKNOWN; |
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break; |
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} |
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i82443bxgx_init_csrows(mci, pdev, edac_mode, mtype); |
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/* Many BIOSes don't clear error flags on boot, so do this |
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* here, or we get "phantom" errors occurring at module-load |
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* time. */ |
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pci_write_bits32(pdev, I82443BXGX_EAP, |
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(I82443BXGX_EAP_OFFSET_SBE | |
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I82443BXGX_EAP_OFFSET_MBE), |
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(I82443BXGX_EAP_OFFSET_SBE | |
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I82443BXGX_EAP_OFFSET_MBE)); |
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mci->mod_name = EDAC_MOD_STR; |
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mci->ctl_name = "I82443BXGX"; |
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mci->dev_name = pci_name(pdev); |
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mci->edac_check = i82443bxgx_edacmc_check; |
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mci->ctl_page_to_phys = NULL; |
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if (edac_mc_add_mc(mci)) { |
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edac_dbg(3, "failed edac_mc_add_mc()\n"); |
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goto fail; |
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} |
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/* allocating generic PCI control info */ |
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i82443bxgx_pci = edac_pci_create_generic_ctl(&pdev->dev, EDAC_MOD_STR); |
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if (!i82443bxgx_pci) { |
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printk(KERN_WARNING |
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"%s(): Unable to create PCI control\n", |
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__func__); |
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printk(KERN_WARNING |
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"%s(): PCI error report via EDAC not setup\n", |
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__func__); |
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} |
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edac_dbg(3, "MC: success\n"); |
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return 0; |
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fail: |
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edac_mc_free(mci); |
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return -ENODEV; |
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} |
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/* returns count (>= 0), or negative on error */ |
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static int i82443bxgx_edacmc_init_one(struct pci_dev *pdev, |
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const struct pci_device_id *ent) |
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{ |
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int rc; |
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edac_dbg(0, "MC:\n"); |
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/* don't need to call pci_enable_device() */ |
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rc = i82443bxgx_edacmc_probe1(pdev, ent->driver_data); |
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if (mci_pdev == NULL) |
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mci_pdev = pci_dev_get(pdev); |
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return rc; |
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} |
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static void i82443bxgx_edacmc_remove_one(struct pci_dev *pdev) |
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{ |
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struct mem_ctl_info *mci; |
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edac_dbg(0, "\n"); |
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if (i82443bxgx_pci) |
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edac_pci_release_generic_ctl(i82443bxgx_pci); |
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if ((mci = edac_mc_del_mc(&pdev->dev)) == NULL) |
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return; |
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edac_mc_free(mci); |
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} |
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static const struct pci_device_id i82443bxgx_pci_tbl[] = { |
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{PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_0)}, |
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{PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_2)}, |
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{PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443GX_0)}, |
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{PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443GX_2)}, |
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{0,} /* 0 terminated list. */ |
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}; |
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MODULE_DEVICE_TABLE(pci, i82443bxgx_pci_tbl); |
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static struct pci_driver i82443bxgx_edacmc_driver = { |
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.name = EDAC_MOD_STR, |
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.probe = i82443bxgx_edacmc_init_one, |
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.remove = i82443bxgx_edacmc_remove_one, |
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.id_table = i82443bxgx_pci_tbl, |
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}; |
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static int __init i82443bxgx_edacmc_init(void) |
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{ |
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int pci_rc; |
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/* Ensure that the OPSTATE is set correctly for POLL or NMI */ |
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opstate_init(); |
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pci_rc = pci_register_driver(&i82443bxgx_edacmc_driver); |
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if (pci_rc < 0) |
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goto fail0; |
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if (mci_pdev == NULL) { |
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const struct pci_device_id *id = &i82443bxgx_pci_tbl[0]; |
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int i = 0; |
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i82443bxgx_registered = 0; |
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while (mci_pdev == NULL && id->vendor != 0) { |
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mci_pdev = pci_get_device(id->vendor, |
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id->device, NULL); |
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i++; |
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id = &i82443bxgx_pci_tbl[i]; |
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} |
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if (!mci_pdev) { |
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edac_dbg(0, "i82443bxgx pci_get_device fail\n"); |
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pci_rc = -ENODEV; |
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goto fail1; |
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} |
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pci_rc = i82443bxgx_edacmc_init_one(mci_pdev, i82443bxgx_pci_tbl); |
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if (pci_rc < 0) { |
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edac_dbg(0, "i82443bxgx init fail\n"); |
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pci_rc = -ENODEV; |
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goto fail1; |
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} |
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} |
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return 0; |
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fail1: |
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pci_unregister_driver(&i82443bxgx_edacmc_driver); |
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fail0: |
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pci_dev_put(mci_pdev); |
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return pci_rc; |
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} |
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static void __exit i82443bxgx_edacmc_exit(void) |
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{ |
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pci_unregister_driver(&i82443bxgx_edacmc_driver); |
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if (!i82443bxgx_registered) |
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i82443bxgx_edacmc_remove_one(mci_pdev); |
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pci_dev_put(mci_pdev); |
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} |
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module_init(i82443bxgx_edacmc_init); |
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module_exit(i82443bxgx_edacmc_exit); |
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MODULE_LICENSE("GPL"); |
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MODULE_AUTHOR("Tim Small <[email protected]> - WPAD"); |
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MODULE_DESCRIPTION("EDAC MC support for Intel 82443BX/GX memory controllers"); |
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module_param(edac_op_state, int, 0444); |
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MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI");
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