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737 lines
21 KiB
737 lines
21 KiB
// SPDX-License-Identifier: GPL-2.0-only |
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/* |
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* Intel I/OAT DMA Linux driver |
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* Copyright(c) 2004 - 2015 Intel Corporation. |
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*/ |
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#include <linux/module.h> |
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#include <linux/pci.h> |
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#include <linux/gfp.h> |
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#include <linux/dmaengine.h> |
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#include <linux/dma-mapping.h> |
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#include <linux/prefetch.h> |
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#include "../dmaengine.h" |
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#include "registers.h" |
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#include "hw.h" |
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#include "dma.h" |
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#define MAX_SCF 256 |
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|
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/* provide a lookup table for setting the source address in the base or |
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* extended descriptor of an xor or pq descriptor |
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*/ |
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static const u8 xor_idx_to_desc = 0xe0; |
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static const u8 xor_idx_to_field[] = { 1, 4, 5, 6, 7, 0, 1, 2 }; |
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static const u8 pq_idx_to_desc = 0xf8; |
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static const u8 pq16_idx_to_desc[] = { 0, 0, 1, 1, 1, 1, 1, 1, 1, |
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2, 2, 2, 2, 2, 2, 2 }; |
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static const u8 pq_idx_to_field[] = { 1, 4, 5, 0, 1, 2, 4, 5 }; |
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static const u8 pq16_idx_to_field[] = { 1, 4, 1, 2, 3, 4, 5, 6, 7, |
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0, 1, 2, 3, 4, 5, 6 }; |
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static void xor_set_src(struct ioat_raw_descriptor *descs[2], |
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dma_addr_t addr, u32 offset, int idx) |
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{ |
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struct ioat_raw_descriptor *raw = descs[xor_idx_to_desc >> idx & 1]; |
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raw->field[xor_idx_to_field[idx]] = addr + offset; |
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} |
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static dma_addr_t pq_get_src(struct ioat_raw_descriptor *descs[2], int idx) |
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{ |
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struct ioat_raw_descriptor *raw = descs[pq_idx_to_desc >> idx & 1]; |
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return raw->field[pq_idx_to_field[idx]]; |
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} |
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static dma_addr_t pq16_get_src(struct ioat_raw_descriptor *desc[3], int idx) |
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{ |
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struct ioat_raw_descriptor *raw = desc[pq16_idx_to_desc[idx]]; |
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return raw->field[pq16_idx_to_field[idx]]; |
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} |
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static void pq_set_src(struct ioat_raw_descriptor *descs[2], |
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dma_addr_t addr, u32 offset, u8 coef, int idx) |
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{ |
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struct ioat_pq_descriptor *pq = (struct ioat_pq_descriptor *) descs[0]; |
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struct ioat_raw_descriptor *raw = descs[pq_idx_to_desc >> idx & 1]; |
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raw->field[pq_idx_to_field[idx]] = addr + offset; |
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pq->coef[idx] = coef; |
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} |
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static void pq16_set_src(struct ioat_raw_descriptor *desc[3], |
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dma_addr_t addr, u32 offset, u8 coef, unsigned idx) |
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{ |
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struct ioat_pq_descriptor *pq = (struct ioat_pq_descriptor *)desc[0]; |
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struct ioat_pq16a_descriptor *pq16 = |
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(struct ioat_pq16a_descriptor *)desc[1]; |
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struct ioat_raw_descriptor *raw = desc[pq16_idx_to_desc[idx]]; |
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raw->field[pq16_idx_to_field[idx]] = addr + offset; |
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if (idx < 8) |
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pq->coef[idx] = coef; |
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else |
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pq16->coef[idx - 8] = coef; |
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} |
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static struct ioat_sed_ent * |
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ioat3_alloc_sed(struct ioatdma_device *ioat_dma, unsigned int hw_pool) |
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{ |
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struct ioat_sed_ent *sed; |
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gfp_t flags = __GFP_ZERO | GFP_ATOMIC; |
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sed = kmem_cache_alloc(ioat_sed_cache, flags); |
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if (!sed) |
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return NULL; |
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sed->hw_pool = hw_pool; |
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sed->hw = dma_pool_alloc(ioat_dma->sed_hw_pool[hw_pool], |
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flags, &sed->dma); |
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if (!sed->hw) { |
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kmem_cache_free(ioat_sed_cache, sed); |
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return NULL; |
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} |
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return sed; |
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} |
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struct dma_async_tx_descriptor * |
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ioat_dma_prep_memcpy_lock(struct dma_chan *c, dma_addr_t dma_dest, |
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dma_addr_t dma_src, size_t len, unsigned long flags) |
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{ |
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struct ioatdma_chan *ioat_chan = to_ioat_chan(c); |
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struct ioat_dma_descriptor *hw; |
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struct ioat_ring_ent *desc; |
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dma_addr_t dst = dma_dest; |
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dma_addr_t src = dma_src; |
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size_t total_len = len; |
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int num_descs, idx, i; |
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if (test_bit(IOAT_CHAN_DOWN, &ioat_chan->state)) |
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return NULL; |
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num_descs = ioat_xferlen_to_descs(ioat_chan, len); |
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if (likely(num_descs) && |
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ioat_check_space_lock(ioat_chan, num_descs) == 0) |
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idx = ioat_chan->head; |
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else |
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return NULL; |
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i = 0; |
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do { |
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size_t copy = min_t(size_t, len, 1 << ioat_chan->xfercap_log); |
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desc = ioat_get_ring_ent(ioat_chan, idx + i); |
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hw = desc->hw; |
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hw->size = copy; |
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hw->ctl = 0; |
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hw->src_addr = src; |
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hw->dst_addr = dst; |
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len -= copy; |
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dst += copy; |
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src += copy; |
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dump_desc_dbg(ioat_chan, desc); |
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} while (++i < num_descs); |
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desc->txd.flags = flags; |
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desc->len = total_len; |
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hw->ctl_f.int_en = !!(flags & DMA_PREP_INTERRUPT); |
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hw->ctl_f.fence = !!(flags & DMA_PREP_FENCE); |
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hw->ctl_f.compl_write = 1; |
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dump_desc_dbg(ioat_chan, desc); |
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/* we leave the channel locked to ensure in order submission */ |
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return &desc->txd; |
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} |
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static struct dma_async_tx_descriptor * |
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__ioat_prep_xor_lock(struct dma_chan *c, enum sum_check_flags *result, |
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dma_addr_t dest, dma_addr_t *src, unsigned int src_cnt, |
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size_t len, unsigned long flags) |
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{ |
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struct ioatdma_chan *ioat_chan = to_ioat_chan(c); |
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struct ioat_ring_ent *compl_desc; |
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struct ioat_ring_ent *desc; |
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struct ioat_ring_ent *ext; |
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size_t total_len = len; |
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struct ioat_xor_descriptor *xor; |
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struct ioat_xor_ext_descriptor *xor_ex = NULL; |
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struct ioat_dma_descriptor *hw; |
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int num_descs, with_ext, idx, i; |
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u32 offset = 0; |
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u8 op = result ? IOAT_OP_XOR_VAL : IOAT_OP_XOR; |
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BUG_ON(src_cnt < 2); |
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num_descs = ioat_xferlen_to_descs(ioat_chan, len); |
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/* we need 2x the number of descriptors to cover greater than 5 |
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* sources |
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*/ |
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if (src_cnt > 5) { |
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with_ext = 1; |
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num_descs *= 2; |
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} else |
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with_ext = 0; |
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/* completion writes from the raid engine may pass completion |
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* writes from the legacy engine, so we need one extra null |
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* (legacy) descriptor to ensure all completion writes arrive in |
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* order. |
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*/ |
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if (likely(num_descs) && |
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ioat_check_space_lock(ioat_chan, num_descs+1) == 0) |
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idx = ioat_chan->head; |
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else |
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return NULL; |
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i = 0; |
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do { |
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struct ioat_raw_descriptor *descs[2]; |
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size_t xfer_size = min_t(size_t, |
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len, 1 << ioat_chan->xfercap_log); |
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int s; |
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desc = ioat_get_ring_ent(ioat_chan, idx + i); |
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xor = desc->xor; |
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/* save a branch by unconditionally retrieving the |
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* extended descriptor xor_set_src() knows to not write |
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* to it in the single descriptor case |
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*/ |
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ext = ioat_get_ring_ent(ioat_chan, idx + i + 1); |
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xor_ex = ext->xor_ex; |
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descs[0] = (struct ioat_raw_descriptor *) xor; |
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descs[1] = (struct ioat_raw_descriptor *) xor_ex; |
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for (s = 0; s < src_cnt; s++) |
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xor_set_src(descs, src[s], offset, s); |
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xor->size = xfer_size; |
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xor->dst_addr = dest + offset; |
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xor->ctl = 0; |
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xor->ctl_f.op = op; |
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xor->ctl_f.src_cnt = src_cnt_to_hw(src_cnt); |
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len -= xfer_size; |
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offset += xfer_size; |
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dump_desc_dbg(ioat_chan, desc); |
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} while ((i += 1 + with_ext) < num_descs); |
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/* last xor descriptor carries the unmap parameters and fence bit */ |
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desc->txd.flags = flags; |
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desc->len = total_len; |
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if (result) |
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desc->result = result; |
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xor->ctl_f.fence = !!(flags & DMA_PREP_FENCE); |
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/* completion descriptor carries interrupt bit */ |
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compl_desc = ioat_get_ring_ent(ioat_chan, idx + i); |
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compl_desc->txd.flags = flags & DMA_PREP_INTERRUPT; |
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hw = compl_desc->hw; |
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hw->ctl = 0; |
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hw->ctl_f.null = 1; |
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hw->ctl_f.int_en = !!(flags & DMA_PREP_INTERRUPT); |
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hw->ctl_f.compl_write = 1; |
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hw->size = NULL_DESC_BUFFER_SIZE; |
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dump_desc_dbg(ioat_chan, compl_desc); |
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/* we leave the channel locked to ensure in order submission */ |
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return &compl_desc->txd; |
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} |
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struct dma_async_tx_descriptor * |
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ioat_prep_xor(struct dma_chan *chan, dma_addr_t dest, dma_addr_t *src, |
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unsigned int src_cnt, size_t len, unsigned long flags) |
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{ |
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struct ioatdma_chan *ioat_chan = to_ioat_chan(chan); |
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if (test_bit(IOAT_CHAN_DOWN, &ioat_chan->state)) |
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return NULL; |
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return __ioat_prep_xor_lock(chan, NULL, dest, src, src_cnt, len, flags); |
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} |
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struct dma_async_tx_descriptor * |
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ioat_prep_xor_val(struct dma_chan *chan, dma_addr_t *src, |
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unsigned int src_cnt, size_t len, |
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enum sum_check_flags *result, unsigned long flags) |
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{ |
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struct ioatdma_chan *ioat_chan = to_ioat_chan(chan); |
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if (test_bit(IOAT_CHAN_DOWN, &ioat_chan->state)) |
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return NULL; |
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/* the cleanup routine only sets bits on validate failure, it |
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* does not clear bits on validate success... so clear it here |
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*/ |
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*result = 0; |
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return __ioat_prep_xor_lock(chan, result, src[0], &src[1], |
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src_cnt - 1, len, flags); |
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} |
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static void |
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dump_pq_desc_dbg(struct ioatdma_chan *ioat_chan, struct ioat_ring_ent *desc, |
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struct ioat_ring_ent *ext) |
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{ |
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struct device *dev = to_dev(ioat_chan); |
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struct ioat_pq_descriptor *pq = desc->pq; |
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struct ioat_pq_ext_descriptor *pq_ex = ext ? ext->pq_ex : NULL; |
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struct ioat_raw_descriptor *descs[] = { (void *) pq, (void *) pq_ex }; |
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int src_cnt = src_cnt_to_sw(pq->ctl_f.src_cnt); |
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int i; |
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dev_dbg(dev, "desc[%d]: (%#llx->%#llx) flags: %#x" |
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" sz: %#10.8x ctl: %#x (op: %#x int: %d compl: %d pq: '%s%s'" |
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" src_cnt: %d)\n", |
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desc_id(desc), (unsigned long long) desc->txd.phys, |
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(unsigned long long) (pq_ex ? pq_ex->next : pq->next), |
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desc->txd.flags, pq->size, pq->ctl, pq->ctl_f.op, |
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pq->ctl_f.int_en, pq->ctl_f.compl_write, |
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pq->ctl_f.p_disable ? "" : "p", pq->ctl_f.q_disable ? "" : "q", |
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pq->ctl_f.src_cnt); |
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for (i = 0; i < src_cnt; i++) |
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dev_dbg(dev, "\tsrc[%d]: %#llx coef: %#x\n", i, |
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(unsigned long long) pq_get_src(descs, i), pq->coef[i]); |
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dev_dbg(dev, "\tP: %#llx\n", pq->p_addr); |
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dev_dbg(dev, "\tQ: %#llx\n", pq->q_addr); |
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dev_dbg(dev, "\tNEXT: %#llx\n", pq->next); |
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} |
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static void dump_pq16_desc_dbg(struct ioatdma_chan *ioat_chan, |
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struct ioat_ring_ent *desc) |
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{ |
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struct device *dev = to_dev(ioat_chan); |
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struct ioat_pq_descriptor *pq = desc->pq; |
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struct ioat_raw_descriptor *descs[] = { (void *)pq, |
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(void *)pq, |
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(void *)pq }; |
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int src_cnt = src16_cnt_to_sw(pq->ctl_f.src_cnt); |
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int i; |
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if (desc->sed) { |
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descs[1] = (void *)desc->sed->hw; |
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descs[2] = (void *)desc->sed->hw + 64; |
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} |
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dev_dbg(dev, "desc[%d]: (%#llx->%#llx) flags: %#x" |
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" sz: %#x ctl: %#x (op: %#x int: %d compl: %d pq: '%s%s'" |
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" src_cnt: %d)\n", |
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desc_id(desc), (unsigned long long) desc->txd.phys, |
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(unsigned long long) pq->next, |
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desc->txd.flags, pq->size, pq->ctl, |
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pq->ctl_f.op, pq->ctl_f.int_en, |
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pq->ctl_f.compl_write, |
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pq->ctl_f.p_disable ? "" : "p", pq->ctl_f.q_disable ? "" : "q", |
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pq->ctl_f.src_cnt); |
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for (i = 0; i < src_cnt; i++) { |
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dev_dbg(dev, "\tsrc[%d]: %#llx coef: %#x\n", i, |
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(unsigned long long) pq16_get_src(descs, i), |
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pq->coef[i]); |
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} |
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dev_dbg(dev, "\tP: %#llx\n", pq->p_addr); |
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dev_dbg(dev, "\tQ: %#llx\n", pq->q_addr); |
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} |
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static struct dma_async_tx_descriptor * |
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__ioat_prep_pq_lock(struct dma_chan *c, enum sum_check_flags *result, |
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const dma_addr_t *dst, const dma_addr_t *src, |
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unsigned int src_cnt, const unsigned char *scf, |
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size_t len, unsigned long flags) |
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{ |
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struct ioatdma_chan *ioat_chan = to_ioat_chan(c); |
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struct ioatdma_device *ioat_dma = ioat_chan->ioat_dma; |
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struct ioat_ring_ent *compl_desc; |
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struct ioat_ring_ent *desc; |
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struct ioat_ring_ent *ext; |
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size_t total_len = len; |
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struct ioat_pq_descriptor *pq; |
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struct ioat_pq_ext_descriptor *pq_ex = NULL; |
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struct ioat_dma_descriptor *hw; |
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u32 offset = 0; |
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u8 op = result ? IOAT_OP_PQ_VAL : IOAT_OP_PQ; |
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int i, s, idx, with_ext, num_descs; |
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int cb32 = (ioat_dma->version < IOAT_VER_3_3) ? 1 : 0; |
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dev_dbg(to_dev(ioat_chan), "%s\n", __func__); |
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/* the engine requires at least two sources (we provide |
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* at least 1 implied source in the DMA_PREP_CONTINUE case) |
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*/ |
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BUG_ON(src_cnt + dmaf_continue(flags) < 2); |
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num_descs = ioat_xferlen_to_descs(ioat_chan, len); |
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/* we need 2x the number of descriptors to cover greater than 3 |
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* sources (we need 1 extra source in the q-only continuation |
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* case and 3 extra sources in the p+q continuation case. |
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*/ |
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if (src_cnt + dmaf_p_disabled_continue(flags) > 3 || |
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(dmaf_continue(flags) && !dmaf_p_disabled_continue(flags))) { |
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with_ext = 1; |
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num_descs *= 2; |
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} else |
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with_ext = 0; |
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/* completion writes from the raid engine may pass completion |
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* writes from the legacy engine, so we need one extra null |
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* (legacy) descriptor to ensure all completion writes arrive in |
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* order. |
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*/ |
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if (likely(num_descs) && |
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ioat_check_space_lock(ioat_chan, num_descs + cb32) == 0) |
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idx = ioat_chan->head; |
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else |
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return NULL; |
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i = 0; |
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do { |
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struct ioat_raw_descriptor *descs[2]; |
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size_t xfer_size = min_t(size_t, len, |
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1 << ioat_chan->xfercap_log); |
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desc = ioat_get_ring_ent(ioat_chan, idx + i); |
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pq = desc->pq; |
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/* save a branch by unconditionally retrieving the |
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* extended descriptor pq_set_src() knows to not write |
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* to it in the single descriptor case |
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*/ |
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ext = ioat_get_ring_ent(ioat_chan, idx + i + with_ext); |
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pq_ex = ext->pq_ex; |
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descs[0] = (struct ioat_raw_descriptor *) pq; |
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descs[1] = (struct ioat_raw_descriptor *) pq_ex; |
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for (s = 0; s < src_cnt; s++) |
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pq_set_src(descs, src[s], offset, scf[s], s); |
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/* see the comment for dma_maxpq in include/linux/dmaengine.h */ |
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if (dmaf_p_disabled_continue(flags)) |
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pq_set_src(descs, dst[1], offset, 1, s++); |
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else if (dmaf_continue(flags)) { |
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pq_set_src(descs, dst[0], offset, 0, s++); |
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pq_set_src(descs, dst[1], offset, 1, s++); |
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pq_set_src(descs, dst[1], offset, 0, s++); |
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} |
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pq->size = xfer_size; |
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pq->p_addr = dst[0] + offset; |
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pq->q_addr = dst[1] + offset; |
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pq->ctl = 0; |
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pq->ctl_f.op = op; |
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/* we turn on descriptor write back error status */ |
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if (ioat_dma->cap & IOAT_CAP_DWBES) |
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pq->ctl_f.wb_en = result ? 1 : 0; |
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pq->ctl_f.src_cnt = src_cnt_to_hw(s); |
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pq->ctl_f.p_disable = !!(flags & DMA_PREP_PQ_DISABLE_P); |
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pq->ctl_f.q_disable = !!(flags & DMA_PREP_PQ_DISABLE_Q); |
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len -= xfer_size; |
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offset += xfer_size; |
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} while ((i += 1 + with_ext) < num_descs); |
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/* last pq descriptor carries the unmap parameters and fence bit */ |
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desc->txd.flags = flags; |
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desc->len = total_len; |
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if (result) |
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desc->result = result; |
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pq->ctl_f.fence = !!(flags & DMA_PREP_FENCE); |
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dump_pq_desc_dbg(ioat_chan, desc, ext); |
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if (!cb32) { |
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pq->ctl_f.int_en = !!(flags & DMA_PREP_INTERRUPT); |
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pq->ctl_f.compl_write = 1; |
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compl_desc = desc; |
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} else { |
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/* completion descriptor carries interrupt bit */ |
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compl_desc = ioat_get_ring_ent(ioat_chan, idx + i); |
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compl_desc->txd.flags = flags & DMA_PREP_INTERRUPT; |
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hw = compl_desc->hw; |
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hw->ctl = 0; |
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hw->ctl_f.null = 1; |
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hw->ctl_f.int_en = !!(flags & DMA_PREP_INTERRUPT); |
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hw->ctl_f.compl_write = 1; |
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hw->size = NULL_DESC_BUFFER_SIZE; |
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dump_desc_dbg(ioat_chan, compl_desc); |
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} |
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/* we leave the channel locked to ensure in order submission */ |
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return &compl_desc->txd; |
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} |
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|
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static struct dma_async_tx_descriptor * |
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__ioat_prep_pq16_lock(struct dma_chan *c, enum sum_check_flags *result, |
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const dma_addr_t *dst, const dma_addr_t *src, |
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unsigned int src_cnt, const unsigned char *scf, |
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size_t len, unsigned long flags) |
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{ |
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struct ioatdma_chan *ioat_chan = to_ioat_chan(c); |
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struct ioatdma_device *ioat_dma = ioat_chan->ioat_dma; |
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struct ioat_ring_ent *desc; |
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size_t total_len = len; |
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struct ioat_pq_descriptor *pq; |
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u32 offset = 0; |
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u8 op; |
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int i, s, idx, num_descs; |
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|
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/* this function is only called with 9-16 sources */ |
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op = result ? IOAT_OP_PQ_VAL_16S : IOAT_OP_PQ_16S; |
|
|
|
dev_dbg(to_dev(ioat_chan), "%s\n", __func__); |
|
|
|
num_descs = ioat_xferlen_to_descs(ioat_chan, len); |
|
|
|
/* |
|
* 16 source pq is only available on cb3.3 and has no completion |
|
* write hw bug. |
|
*/ |
|
if (num_descs && ioat_check_space_lock(ioat_chan, num_descs) == 0) |
|
idx = ioat_chan->head; |
|
else |
|
return NULL; |
|
|
|
i = 0; |
|
|
|
do { |
|
struct ioat_raw_descriptor *descs[4]; |
|
size_t xfer_size = min_t(size_t, len, |
|
1 << ioat_chan->xfercap_log); |
|
|
|
desc = ioat_get_ring_ent(ioat_chan, idx + i); |
|
pq = desc->pq; |
|
|
|
descs[0] = (struct ioat_raw_descriptor *) pq; |
|
|
|
desc->sed = ioat3_alloc_sed(ioat_dma, (src_cnt-2) >> 3); |
|
if (!desc->sed) { |
|
dev_err(to_dev(ioat_chan), |
|
"%s: no free sed entries\n", __func__); |
|
return NULL; |
|
} |
|
|
|
pq->sed_addr = desc->sed->dma; |
|
desc->sed->parent = desc; |
|
|
|
descs[1] = (struct ioat_raw_descriptor *)desc->sed->hw; |
|
descs[2] = (void *)descs[1] + 64; |
|
|
|
for (s = 0; s < src_cnt; s++) |
|
pq16_set_src(descs, src[s], offset, scf[s], s); |
|
|
|
/* see the comment for dma_maxpq in include/linux/dmaengine.h */ |
|
if (dmaf_p_disabled_continue(flags)) |
|
pq16_set_src(descs, dst[1], offset, 1, s++); |
|
else if (dmaf_continue(flags)) { |
|
pq16_set_src(descs, dst[0], offset, 0, s++); |
|
pq16_set_src(descs, dst[1], offset, 1, s++); |
|
pq16_set_src(descs, dst[1], offset, 0, s++); |
|
} |
|
|
|
pq->size = xfer_size; |
|
pq->p_addr = dst[0] + offset; |
|
pq->q_addr = dst[1] + offset; |
|
pq->ctl = 0; |
|
pq->ctl_f.op = op; |
|
pq->ctl_f.src_cnt = src16_cnt_to_hw(s); |
|
/* we turn on descriptor write back error status */ |
|
if (ioat_dma->cap & IOAT_CAP_DWBES) |
|
pq->ctl_f.wb_en = result ? 1 : 0; |
|
pq->ctl_f.p_disable = !!(flags & DMA_PREP_PQ_DISABLE_P); |
|
pq->ctl_f.q_disable = !!(flags & DMA_PREP_PQ_DISABLE_Q); |
|
|
|
len -= xfer_size; |
|
offset += xfer_size; |
|
} while (++i < num_descs); |
|
|
|
/* last pq descriptor carries the unmap parameters and fence bit */ |
|
desc->txd.flags = flags; |
|
desc->len = total_len; |
|
if (result) |
|
desc->result = result; |
|
pq->ctl_f.fence = !!(flags & DMA_PREP_FENCE); |
|
|
|
/* with cb3.3 we should be able to do completion w/o a null desc */ |
|
pq->ctl_f.int_en = !!(flags & DMA_PREP_INTERRUPT); |
|
pq->ctl_f.compl_write = 1; |
|
|
|
dump_pq16_desc_dbg(ioat_chan, desc); |
|
|
|
/* we leave the channel locked to ensure in order submission */ |
|
return &desc->txd; |
|
} |
|
|
|
static int src_cnt_flags(unsigned int src_cnt, unsigned long flags) |
|
{ |
|
if (dmaf_p_disabled_continue(flags)) |
|
return src_cnt + 1; |
|
else if (dmaf_continue(flags)) |
|
return src_cnt + 3; |
|
else |
|
return src_cnt; |
|
} |
|
|
|
struct dma_async_tx_descriptor * |
|
ioat_prep_pq(struct dma_chan *chan, dma_addr_t *dst, dma_addr_t *src, |
|
unsigned int src_cnt, const unsigned char *scf, size_t len, |
|
unsigned long flags) |
|
{ |
|
struct ioatdma_chan *ioat_chan = to_ioat_chan(chan); |
|
|
|
if (test_bit(IOAT_CHAN_DOWN, &ioat_chan->state)) |
|
return NULL; |
|
|
|
/* specify valid address for disabled result */ |
|
if (flags & DMA_PREP_PQ_DISABLE_P) |
|
dst[0] = dst[1]; |
|
if (flags & DMA_PREP_PQ_DISABLE_Q) |
|
dst[1] = dst[0]; |
|
|
|
/* handle the single source multiply case from the raid6 |
|
* recovery path |
|
*/ |
|
if ((flags & DMA_PREP_PQ_DISABLE_P) && src_cnt == 1) { |
|
dma_addr_t single_source[2]; |
|
unsigned char single_source_coef[2]; |
|
|
|
BUG_ON(flags & DMA_PREP_PQ_DISABLE_Q); |
|
single_source[0] = src[0]; |
|
single_source[1] = src[0]; |
|
single_source_coef[0] = scf[0]; |
|
single_source_coef[1] = 0; |
|
|
|
return src_cnt_flags(src_cnt, flags) > 8 ? |
|
__ioat_prep_pq16_lock(chan, NULL, dst, single_source, |
|
2, single_source_coef, len, |
|
flags) : |
|
__ioat_prep_pq_lock(chan, NULL, dst, single_source, 2, |
|
single_source_coef, len, flags); |
|
|
|
} else { |
|
return src_cnt_flags(src_cnt, flags) > 8 ? |
|
__ioat_prep_pq16_lock(chan, NULL, dst, src, src_cnt, |
|
scf, len, flags) : |
|
__ioat_prep_pq_lock(chan, NULL, dst, src, src_cnt, |
|
scf, len, flags); |
|
} |
|
} |
|
|
|
struct dma_async_tx_descriptor * |
|
ioat_prep_pq_val(struct dma_chan *chan, dma_addr_t *pq, dma_addr_t *src, |
|
unsigned int src_cnt, const unsigned char *scf, size_t len, |
|
enum sum_check_flags *pqres, unsigned long flags) |
|
{ |
|
struct ioatdma_chan *ioat_chan = to_ioat_chan(chan); |
|
|
|
if (test_bit(IOAT_CHAN_DOWN, &ioat_chan->state)) |
|
return NULL; |
|
|
|
/* specify valid address for disabled result */ |
|
if (flags & DMA_PREP_PQ_DISABLE_P) |
|
pq[0] = pq[1]; |
|
if (flags & DMA_PREP_PQ_DISABLE_Q) |
|
pq[1] = pq[0]; |
|
|
|
/* the cleanup routine only sets bits on validate failure, it |
|
* does not clear bits on validate success... so clear it here |
|
*/ |
|
*pqres = 0; |
|
|
|
return src_cnt_flags(src_cnt, flags) > 8 ? |
|
__ioat_prep_pq16_lock(chan, pqres, pq, src, src_cnt, scf, len, |
|
flags) : |
|
__ioat_prep_pq_lock(chan, pqres, pq, src, src_cnt, scf, len, |
|
flags); |
|
} |
|
|
|
struct dma_async_tx_descriptor * |
|
ioat_prep_pqxor(struct dma_chan *chan, dma_addr_t dst, dma_addr_t *src, |
|
unsigned int src_cnt, size_t len, unsigned long flags) |
|
{ |
|
unsigned char scf[MAX_SCF]; |
|
dma_addr_t pq[2]; |
|
struct ioatdma_chan *ioat_chan = to_ioat_chan(chan); |
|
|
|
if (test_bit(IOAT_CHAN_DOWN, &ioat_chan->state)) |
|
return NULL; |
|
|
|
if (src_cnt > MAX_SCF) |
|
return NULL; |
|
|
|
memset(scf, 0, src_cnt); |
|
pq[0] = dst; |
|
flags |= DMA_PREP_PQ_DISABLE_Q; |
|
pq[1] = dst; /* specify valid address for disabled result */ |
|
|
|
return src_cnt_flags(src_cnt, flags) > 8 ? |
|
__ioat_prep_pq16_lock(chan, NULL, pq, src, src_cnt, scf, len, |
|
flags) : |
|
__ioat_prep_pq_lock(chan, NULL, pq, src, src_cnt, scf, len, |
|
flags); |
|
} |
|
|
|
struct dma_async_tx_descriptor * |
|
ioat_prep_pqxor_val(struct dma_chan *chan, dma_addr_t *src, |
|
unsigned int src_cnt, size_t len, |
|
enum sum_check_flags *result, unsigned long flags) |
|
{ |
|
unsigned char scf[MAX_SCF]; |
|
dma_addr_t pq[2]; |
|
struct ioatdma_chan *ioat_chan = to_ioat_chan(chan); |
|
|
|
if (test_bit(IOAT_CHAN_DOWN, &ioat_chan->state)) |
|
return NULL; |
|
|
|
if (src_cnt > MAX_SCF) |
|
return NULL; |
|
|
|
/* the cleanup routine only sets bits on validate failure, it |
|
* does not clear bits on validate success... so clear it here |
|
*/ |
|
*result = 0; |
|
|
|
memset(scf, 0, src_cnt); |
|
pq[0] = src[0]; |
|
flags |= DMA_PREP_PQ_DISABLE_Q; |
|
pq[1] = pq[0]; /* specify valid address for disabled result */ |
|
|
|
return src_cnt_flags(src_cnt, flags) > 8 ? |
|
__ioat_prep_pq16_lock(chan, result, pq, &src[1], src_cnt - 1, |
|
scf, len, flags) : |
|
__ioat_prep_pq_lock(chan, result, pq, &src[1], src_cnt - 1, |
|
scf, len, flags); |
|
} |
|
|
|
struct dma_async_tx_descriptor * |
|
ioat_prep_interrupt_lock(struct dma_chan *c, unsigned long flags) |
|
{ |
|
struct ioatdma_chan *ioat_chan = to_ioat_chan(c); |
|
struct ioat_ring_ent *desc; |
|
struct ioat_dma_descriptor *hw; |
|
|
|
if (test_bit(IOAT_CHAN_DOWN, &ioat_chan->state)) |
|
return NULL; |
|
|
|
if (ioat_check_space_lock(ioat_chan, 1) == 0) |
|
desc = ioat_get_ring_ent(ioat_chan, ioat_chan->head); |
|
else |
|
return NULL; |
|
|
|
hw = desc->hw; |
|
hw->ctl = 0; |
|
hw->ctl_f.null = 1; |
|
hw->ctl_f.int_en = 1; |
|
hw->ctl_f.fence = !!(flags & DMA_PREP_FENCE); |
|
hw->ctl_f.compl_write = 1; |
|
hw->size = NULL_DESC_BUFFER_SIZE; |
|
hw->src_addr = 0; |
|
hw->dst_addr = 0; |
|
|
|
desc->txd.flags = flags; |
|
desc->len = 1; |
|
|
|
dump_desc_dbg(ioat_chan, desc); |
|
|
|
/* we leave the channel locked to ensure in order submission */ |
|
return &desc->txd; |
|
} |
|
|
|
|