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979 lines
24 KiB
979 lines
24 KiB
// SPDX-License-Identifier: GPL-2.0 |
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/* Marvell OcteonTX CPT driver |
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* |
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* Copyright (C) 2019 Marvell International Ltd. |
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* |
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* This program is free software; you can redistribute it and/or modify |
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* it under the terms of the GNU General Public License version 2 as |
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* published by the Free Software Foundation. |
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*/ |
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|
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#include <linux/interrupt.h> |
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#include <linux/module.h> |
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#include "otx_cptvf.h" |
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#include "otx_cptvf_algs.h" |
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#include "otx_cptvf_reqmgr.h" |
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|
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#define DRV_NAME "octeontx-cptvf" |
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#define DRV_VERSION "1.0" |
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|
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static void vq_work_handler(unsigned long data) |
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{ |
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struct otx_cptvf_wqe_info *cwqe_info = |
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(struct otx_cptvf_wqe_info *) data; |
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otx_cpt_post_process(&cwqe_info->vq_wqe[0]); |
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} |
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static int init_worker_threads(struct otx_cptvf *cptvf) |
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{ |
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struct pci_dev *pdev = cptvf->pdev; |
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struct otx_cptvf_wqe_info *cwqe_info; |
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int i; |
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cwqe_info = kzalloc(sizeof(*cwqe_info), GFP_KERNEL); |
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if (!cwqe_info) |
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return -ENOMEM; |
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|
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if (cptvf->num_queues) { |
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dev_dbg(&pdev->dev, "Creating VQ worker threads (%d)\n", |
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cptvf->num_queues); |
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} |
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|
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for (i = 0; i < cptvf->num_queues; i++) { |
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tasklet_init(&cwqe_info->vq_wqe[i].twork, vq_work_handler, |
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(u64)cwqe_info); |
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cwqe_info->vq_wqe[i].cptvf = cptvf; |
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} |
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cptvf->wqe_info = cwqe_info; |
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|
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return 0; |
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} |
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|
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static void cleanup_worker_threads(struct otx_cptvf *cptvf) |
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{ |
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struct pci_dev *pdev = cptvf->pdev; |
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struct otx_cptvf_wqe_info *cwqe_info; |
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int i; |
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|
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cwqe_info = (struct otx_cptvf_wqe_info *)cptvf->wqe_info; |
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if (!cwqe_info) |
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return; |
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|
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if (cptvf->num_queues) { |
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dev_dbg(&pdev->dev, "Cleaning VQ worker threads (%u)\n", |
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cptvf->num_queues); |
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} |
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|
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for (i = 0; i < cptvf->num_queues; i++) |
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tasklet_kill(&cwqe_info->vq_wqe[i].twork); |
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|
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kfree_sensitive(cwqe_info); |
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cptvf->wqe_info = NULL; |
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} |
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static void free_pending_queues(struct otx_cpt_pending_qinfo *pqinfo) |
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{ |
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struct otx_cpt_pending_queue *queue; |
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int i; |
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|
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for_each_pending_queue(pqinfo, queue, i) { |
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if (!queue->head) |
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continue; |
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|
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/* free single queue */ |
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kfree_sensitive((queue->head)); |
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queue->front = 0; |
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queue->rear = 0; |
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queue->qlen = 0; |
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} |
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pqinfo->num_queues = 0; |
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} |
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|
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static int alloc_pending_queues(struct otx_cpt_pending_qinfo *pqinfo, u32 qlen, |
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u32 num_queues) |
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{ |
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struct otx_cpt_pending_queue *queue = NULL; |
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size_t size; |
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int ret; |
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u32 i; |
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pqinfo->num_queues = num_queues; |
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size = (qlen * sizeof(struct otx_cpt_pending_entry)); |
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for_each_pending_queue(pqinfo, queue, i) { |
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queue->head = kzalloc((size), GFP_KERNEL); |
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if (!queue->head) { |
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ret = -ENOMEM; |
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goto pending_qfail; |
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} |
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|
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queue->pending_count = 0; |
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queue->front = 0; |
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queue->rear = 0; |
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queue->qlen = qlen; |
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|
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/* init queue spin lock */ |
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spin_lock_init(&queue->lock); |
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} |
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return 0; |
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|
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pending_qfail: |
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free_pending_queues(pqinfo); |
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|
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return ret; |
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} |
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static int init_pending_queues(struct otx_cptvf *cptvf, u32 qlen, |
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u32 num_queues) |
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{ |
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struct pci_dev *pdev = cptvf->pdev; |
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int ret; |
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|
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if (!num_queues) |
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return 0; |
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ret = alloc_pending_queues(&cptvf->pqinfo, qlen, num_queues); |
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if (ret) { |
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dev_err(&pdev->dev, "Failed to setup pending queues (%u)\n", |
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num_queues); |
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return ret; |
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} |
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return 0; |
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} |
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|
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static void cleanup_pending_queues(struct otx_cptvf *cptvf) |
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{ |
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struct pci_dev *pdev = cptvf->pdev; |
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|
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if (!cptvf->num_queues) |
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return; |
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dev_dbg(&pdev->dev, "Cleaning VQ pending queue (%u)\n", |
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cptvf->num_queues); |
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free_pending_queues(&cptvf->pqinfo); |
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} |
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static void free_command_queues(struct otx_cptvf *cptvf, |
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struct otx_cpt_cmd_qinfo *cqinfo) |
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{ |
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struct otx_cpt_cmd_queue *queue = NULL; |
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struct otx_cpt_cmd_chunk *chunk = NULL; |
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struct pci_dev *pdev = cptvf->pdev; |
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int i; |
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|
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/* clean up for each queue */ |
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for (i = 0; i < cptvf->num_queues; i++) { |
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queue = &cqinfo->queue[i]; |
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|
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while (!list_empty(&cqinfo->queue[i].chead)) { |
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chunk = list_first_entry(&cqinfo->queue[i].chead, |
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struct otx_cpt_cmd_chunk, nextchunk); |
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|
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dma_free_coherent(&pdev->dev, chunk->size, |
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chunk->head, |
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chunk->dma_addr); |
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chunk->head = NULL; |
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chunk->dma_addr = 0; |
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list_del(&chunk->nextchunk); |
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kfree_sensitive(chunk); |
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} |
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queue->num_chunks = 0; |
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queue->idx = 0; |
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|
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} |
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} |
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static int alloc_command_queues(struct otx_cptvf *cptvf, |
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struct otx_cpt_cmd_qinfo *cqinfo, |
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u32 qlen) |
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{ |
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struct otx_cpt_cmd_chunk *curr, *first, *last; |
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struct otx_cpt_cmd_queue *queue = NULL; |
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struct pci_dev *pdev = cptvf->pdev; |
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size_t q_size, c_size, rem_q_size; |
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u32 qcsize_bytes; |
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int i; |
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/* Qsize in dwords, needed for SADDR config, 1-next chunk pointer */ |
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cptvf->qsize = min(qlen, cqinfo->qchunksize) * |
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OTX_CPT_NEXT_CHUNK_PTR_SIZE + 1; |
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/* Qsize in bytes to create space for alignment */ |
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q_size = qlen * OTX_CPT_INST_SIZE; |
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qcsize_bytes = cqinfo->qchunksize * OTX_CPT_INST_SIZE; |
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/* per queue initialization */ |
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for (i = 0; i < cptvf->num_queues; i++) { |
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c_size = 0; |
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rem_q_size = q_size; |
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first = NULL; |
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last = NULL; |
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queue = &cqinfo->queue[i]; |
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INIT_LIST_HEAD(&queue->chead); |
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do { |
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curr = kzalloc(sizeof(*curr), GFP_KERNEL); |
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if (!curr) |
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goto cmd_qfail; |
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c_size = (rem_q_size > qcsize_bytes) ? qcsize_bytes : |
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rem_q_size; |
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curr->head = dma_alloc_coherent(&pdev->dev, |
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c_size + OTX_CPT_NEXT_CHUNK_PTR_SIZE, |
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&curr->dma_addr, GFP_KERNEL); |
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if (!curr->head) { |
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dev_err(&pdev->dev, |
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"Command Q (%d) chunk (%d) allocation failed\n", |
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i, queue->num_chunks); |
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goto free_curr; |
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} |
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curr->size = c_size; |
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|
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if (queue->num_chunks == 0) { |
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first = curr; |
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queue->base = first; |
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} |
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list_add_tail(&curr->nextchunk, |
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&cqinfo->queue[i].chead); |
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queue->num_chunks++; |
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rem_q_size -= c_size; |
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if (last) |
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*((u64 *)(&last->head[last->size])) = |
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(u64)curr->dma_addr; |
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|
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last = curr; |
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} while (rem_q_size); |
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|
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/* |
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* Make the queue circular, tie back last chunk entry to head |
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*/ |
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curr = first; |
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*((u64 *)(&last->head[last->size])) = (u64)curr->dma_addr; |
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queue->qhead = curr; |
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} |
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return 0; |
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free_curr: |
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kfree(curr); |
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cmd_qfail: |
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free_command_queues(cptvf, cqinfo); |
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return -ENOMEM; |
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} |
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static int init_command_queues(struct otx_cptvf *cptvf, u32 qlen) |
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{ |
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struct pci_dev *pdev = cptvf->pdev; |
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int ret; |
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/* setup command queues */ |
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ret = alloc_command_queues(cptvf, &cptvf->cqinfo, qlen); |
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if (ret) { |
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dev_err(&pdev->dev, "Failed to allocate command queues (%u)\n", |
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cptvf->num_queues); |
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return ret; |
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} |
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return ret; |
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} |
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static void cleanup_command_queues(struct otx_cptvf *cptvf) |
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{ |
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struct pci_dev *pdev = cptvf->pdev; |
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if (!cptvf->num_queues) |
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return; |
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dev_dbg(&pdev->dev, "Cleaning VQ command queue (%u)\n", |
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cptvf->num_queues); |
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free_command_queues(cptvf, &cptvf->cqinfo); |
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} |
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static void cptvf_sw_cleanup(struct otx_cptvf *cptvf) |
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{ |
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cleanup_worker_threads(cptvf); |
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cleanup_pending_queues(cptvf); |
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cleanup_command_queues(cptvf); |
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} |
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static int cptvf_sw_init(struct otx_cptvf *cptvf, u32 qlen, u32 num_queues) |
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{ |
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struct pci_dev *pdev = cptvf->pdev; |
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u32 max_dev_queues = 0; |
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int ret; |
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max_dev_queues = OTX_CPT_NUM_QS_PER_VF; |
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/* possible cpus */ |
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num_queues = min_t(u32, num_queues, max_dev_queues); |
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cptvf->num_queues = num_queues; |
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ret = init_command_queues(cptvf, qlen); |
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if (ret) { |
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dev_err(&pdev->dev, "Failed to setup command queues (%u)\n", |
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num_queues); |
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return ret; |
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} |
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ret = init_pending_queues(cptvf, qlen, num_queues); |
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if (ret) { |
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dev_err(&pdev->dev, "Failed to setup pending queues (%u)\n", |
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num_queues); |
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goto setup_pqfail; |
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} |
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/* Create worker threads for BH processing */ |
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ret = init_worker_threads(cptvf); |
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if (ret) { |
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dev_err(&pdev->dev, "Failed to setup worker threads\n"); |
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goto init_work_fail; |
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} |
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return 0; |
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init_work_fail: |
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cleanup_worker_threads(cptvf); |
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cleanup_pending_queues(cptvf); |
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setup_pqfail: |
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cleanup_command_queues(cptvf); |
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return ret; |
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} |
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static void cptvf_free_irq_affinity(struct otx_cptvf *cptvf, int vec) |
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{ |
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irq_set_affinity_hint(pci_irq_vector(cptvf->pdev, vec), NULL); |
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free_cpumask_var(cptvf->affinity_mask[vec]); |
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} |
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static void cptvf_write_vq_ctl(struct otx_cptvf *cptvf, bool val) |
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{ |
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union otx_cptx_vqx_ctl vqx_ctl; |
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vqx_ctl.u = readq(cptvf->reg_base + OTX_CPT_VQX_CTL(0)); |
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vqx_ctl.s.ena = val; |
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writeq(vqx_ctl.u, cptvf->reg_base + OTX_CPT_VQX_CTL(0)); |
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} |
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void otx_cptvf_write_vq_doorbell(struct otx_cptvf *cptvf, u32 val) |
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{ |
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union otx_cptx_vqx_doorbell vqx_dbell; |
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vqx_dbell.u = readq(cptvf->reg_base + OTX_CPT_VQX_DOORBELL(0)); |
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vqx_dbell.s.dbell_cnt = val * 8; /* Num of Instructions * 8 words */ |
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writeq(vqx_dbell.u, cptvf->reg_base + OTX_CPT_VQX_DOORBELL(0)); |
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} |
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static void cptvf_write_vq_inprog(struct otx_cptvf *cptvf, u8 val) |
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{ |
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union otx_cptx_vqx_inprog vqx_inprg; |
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vqx_inprg.u = readq(cptvf->reg_base + OTX_CPT_VQX_INPROG(0)); |
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vqx_inprg.s.inflight = val; |
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writeq(vqx_inprg.u, cptvf->reg_base + OTX_CPT_VQX_INPROG(0)); |
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} |
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static void cptvf_write_vq_done_numwait(struct otx_cptvf *cptvf, u32 val) |
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{ |
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union otx_cptx_vqx_done_wait vqx_dwait; |
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vqx_dwait.u = readq(cptvf->reg_base + OTX_CPT_VQX_DONE_WAIT(0)); |
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vqx_dwait.s.num_wait = val; |
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writeq(vqx_dwait.u, cptvf->reg_base + OTX_CPT_VQX_DONE_WAIT(0)); |
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} |
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static u32 cptvf_read_vq_done_numwait(struct otx_cptvf *cptvf) |
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{ |
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union otx_cptx_vqx_done_wait vqx_dwait; |
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vqx_dwait.u = readq(cptvf->reg_base + OTX_CPT_VQX_DONE_WAIT(0)); |
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return vqx_dwait.s.num_wait; |
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} |
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static void cptvf_write_vq_done_timewait(struct otx_cptvf *cptvf, u16 time) |
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{ |
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union otx_cptx_vqx_done_wait vqx_dwait; |
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vqx_dwait.u = readq(cptvf->reg_base + OTX_CPT_VQX_DONE_WAIT(0)); |
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vqx_dwait.s.time_wait = time; |
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writeq(vqx_dwait.u, cptvf->reg_base + OTX_CPT_VQX_DONE_WAIT(0)); |
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} |
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static u16 cptvf_read_vq_done_timewait(struct otx_cptvf *cptvf) |
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{ |
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union otx_cptx_vqx_done_wait vqx_dwait; |
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vqx_dwait.u = readq(cptvf->reg_base + OTX_CPT_VQX_DONE_WAIT(0)); |
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return vqx_dwait.s.time_wait; |
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} |
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static void cptvf_enable_swerr_interrupts(struct otx_cptvf *cptvf) |
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{ |
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union otx_cptx_vqx_misc_ena_w1s vqx_misc_ena; |
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vqx_misc_ena.u = readq(cptvf->reg_base + OTX_CPT_VQX_MISC_ENA_W1S(0)); |
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/* Enable SWERR interrupts for the requested VF */ |
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vqx_misc_ena.s.swerr = 1; |
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writeq(vqx_misc_ena.u, cptvf->reg_base + OTX_CPT_VQX_MISC_ENA_W1S(0)); |
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} |
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static void cptvf_enable_mbox_interrupts(struct otx_cptvf *cptvf) |
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{ |
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union otx_cptx_vqx_misc_ena_w1s vqx_misc_ena; |
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vqx_misc_ena.u = readq(cptvf->reg_base + OTX_CPT_VQX_MISC_ENA_W1S(0)); |
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/* Enable MBOX interrupt for the requested VF */ |
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vqx_misc_ena.s.mbox = 1; |
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writeq(vqx_misc_ena.u, cptvf->reg_base + OTX_CPT_VQX_MISC_ENA_W1S(0)); |
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} |
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static void cptvf_enable_done_interrupts(struct otx_cptvf *cptvf) |
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{ |
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union otx_cptx_vqx_done_ena_w1s vqx_done_ena; |
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|
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vqx_done_ena.u = readq(cptvf->reg_base + OTX_CPT_VQX_DONE_ENA_W1S(0)); |
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/* Enable DONE interrupt for the requested VF */ |
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vqx_done_ena.s.done = 1; |
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writeq(vqx_done_ena.u, cptvf->reg_base + OTX_CPT_VQX_DONE_ENA_W1S(0)); |
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} |
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static void cptvf_clear_dovf_intr(struct otx_cptvf *cptvf) |
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{ |
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union otx_cptx_vqx_misc_int vqx_misc_int; |
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|
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vqx_misc_int.u = readq(cptvf->reg_base + OTX_CPT_VQX_MISC_INT(0)); |
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/* W1C for the VF */ |
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vqx_misc_int.s.dovf = 1; |
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writeq(vqx_misc_int.u, cptvf->reg_base + OTX_CPT_VQX_MISC_INT(0)); |
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} |
|
|
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static void cptvf_clear_irde_intr(struct otx_cptvf *cptvf) |
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{ |
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union otx_cptx_vqx_misc_int vqx_misc_int; |
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|
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vqx_misc_int.u = readq(cptvf->reg_base + OTX_CPT_VQX_MISC_INT(0)); |
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/* W1C for the VF */ |
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vqx_misc_int.s.irde = 1; |
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writeq(vqx_misc_int.u, cptvf->reg_base + OTX_CPT_VQX_MISC_INT(0)); |
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} |
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|
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static void cptvf_clear_nwrp_intr(struct otx_cptvf *cptvf) |
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{ |
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union otx_cptx_vqx_misc_int vqx_misc_int; |
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|
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vqx_misc_int.u = readq(cptvf->reg_base + OTX_CPT_VQX_MISC_INT(0)); |
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/* W1C for the VF */ |
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vqx_misc_int.s.nwrp = 1; |
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writeq(vqx_misc_int.u, cptvf->reg_base + OTX_CPT_VQX_MISC_INT(0)); |
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} |
|
|
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static void cptvf_clear_mbox_intr(struct otx_cptvf *cptvf) |
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{ |
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union otx_cptx_vqx_misc_int vqx_misc_int; |
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|
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vqx_misc_int.u = readq(cptvf->reg_base + OTX_CPT_VQX_MISC_INT(0)); |
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/* W1C for the VF */ |
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vqx_misc_int.s.mbox = 1; |
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writeq(vqx_misc_int.u, cptvf->reg_base + OTX_CPT_VQX_MISC_INT(0)); |
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} |
|
|
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static void cptvf_clear_swerr_intr(struct otx_cptvf *cptvf) |
|
{ |
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union otx_cptx_vqx_misc_int vqx_misc_int; |
|
|
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vqx_misc_int.u = readq(cptvf->reg_base + OTX_CPT_VQX_MISC_INT(0)); |
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/* W1C for the VF */ |
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vqx_misc_int.s.swerr = 1; |
|
writeq(vqx_misc_int.u, cptvf->reg_base + OTX_CPT_VQX_MISC_INT(0)); |
|
} |
|
|
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static u64 cptvf_read_vf_misc_intr_status(struct otx_cptvf *cptvf) |
|
{ |
|
return readq(cptvf->reg_base + OTX_CPT_VQX_MISC_INT(0)); |
|
} |
|
|
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static irqreturn_t cptvf_misc_intr_handler(int __always_unused irq, |
|
void *arg) |
|
{ |
|
struct otx_cptvf *cptvf = arg; |
|
struct pci_dev *pdev = cptvf->pdev; |
|
u64 intr; |
|
|
|
intr = cptvf_read_vf_misc_intr_status(cptvf); |
|
/* Check for MISC interrupt types */ |
|
if (likely(intr & OTX_CPT_VF_INTR_MBOX_MASK)) { |
|
dev_dbg(&pdev->dev, "Mailbox interrupt 0x%llx on CPT VF %d\n", |
|
intr, cptvf->vfid); |
|
otx_cptvf_handle_mbox_intr(cptvf); |
|
cptvf_clear_mbox_intr(cptvf); |
|
} else if (unlikely(intr & OTX_CPT_VF_INTR_DOVF_MASK)) { |
|
cptvf_clear_dovf_intr(cptvf); |
|
/* Clear doorbell count */ |
|
otx_cptvf_write_vq_doorbell(cptvf, 0); |
|
dev_err(&pdev->dev, |
|
"Doorbell overflow error interrupt 0x%llx on CPT VF %d\n", |
|
intr, cptvf->vfid); |
|
} else if (unlikely(intr & OTX_CPT_VF_INTR_IRDE_MASK)) { |
|
cptvf_clear_irde_intr(cptvf); |
|
dev_err(&pdev->dev, |
|
"Instruction NCB read error interrupt 0x%llx on CPT VF %d\n", |
|
intr, cptvf->vfid); |
|
} else if (unlikely(intr & OTX_CPT_VF_INTR_NWRP_MASK)) { |
|
cptvf_clear_nwrp_intr(cptvf); |
|
dev_err(&pdev->dev, |
|
"NCB response write error interrupt 0x%llx on CPT VF %d\n", |
|
intr, cptvf->vfid); |
|
} else if (unlikely(intr & OTX_CPT_VF_INTR_SERR_MASK)) { |
|
cptvf_clear_swerr_intr(cptvf); |
|
dev_err(&pdev->dev, |
|
"Software error interrupt 0x%llx on CPT VF %d\n", |
|
intr, cptvf->vfid); |
|
} else { |
|
dev_err(&pdev->dev, "Unhandled interrupt in OTX_CPT VF %d\n", |
|
cptvf->vfid); |
|
} |
|
|
|
return IRQ_HANDLED; |
|
} |
|
|
|
static inline struct otx_cptvf_wqe *get_cptvf_vq_wqe(struct otx_cptvf *cptvf, |
|
int qno) |
|
{ |
|
struct otx_cptvf_wqe_info *nwqe_info; |
|
|
|
if (unlikely(qno >= cptvf->num_queues)) |
|
return NULL; |
|
nwqe_info = (struct otx_cptvf_wqe_info *)cptvf->wqe_info; |
|
|
|
return &nwqe_info->vq_wqe[qno]; |
|
} |
|
|
|
static inline u32 cptvf_read_vq_done_count(struct otx_cptvf *cptvf) |
|
{ |
|
union otx_cptx_vqx_done vqx_done; |
|
|
|
vqx_done.u = readq(cptvf->reg_base + OTX_CPT_VQX_DONE(0)); |
|
return vqx_done.s.done; |
|
} |
|
|
|
static inline void cptvf_write_vq_done_ack(struct otx_cptvf *cptvf, |
|
u32 ackcnt) |
|
{ |
|
union otx_cptx_vqx_done_ack vqx_dack_cnt; |
|
|
|
vqx_dack_cnt.u = readq(cptvf->reg_base + OTX_CPT_VQX_DONE_ACK(0)); |
|
vqx_dack_cnt.s.done_ack = ackcnt; |
|
writeq(vqx_dack_cnt.u, cptvf->reg_base + OTX_CPT_VQX_DONE_ACK(0)); |
|
} |
|
|
|
static irqreturn_t cptvf_done_intr_handler(int __always_unused irq, |
|
void *cptvf_dev) |
|
{ |
|
struct otx_cptvf *cptvf = (struct otx_cptvf *)cptvf_dev; |
|
struct pci_dev *pdev = cptvf->pdev; |
|
/* Read the number of completions */ |
|
u32 intr = cptvf_read_vq_done_count(cptvf); |
|
|
|
if (intr) { |
|
struct otx_cptvf_wqe *wqe; |
|
|
|
/* |
|
* Acknowledge the number of scheduled completions for |
|
* processing |
|
*/ |
|
cptvf_write_vq_done_ack(cptvf, intr); |
|
wqe = get_cptvf_vq_wqe(cptvf, 0); |
|
if (unlikely(!wqe)) { |
|
dev_err(&pdev->dev, "No work to schedule for VF (%d)\n", |
|
cptvf->vfid); |
|
return IRQ_NONE; |
|
} |
|
tasklet_hi_schedule(&wqe->twork); |
|
} |
|
|
|
return IRQ_HANDLED; |
|
} |
|
|
|
static void cptvf_set_irq_affinity(struct otx_cptvf *cptvf, int vec) |
|
{ |
|
struct pci_dev *pdev = cptvf->pdev; |
|
int cpu; |
|
|
|
if (!zalloc_cpumask_var(&cptvf->affinity_mask[vec], |
|
GFP_KERNEL)) { |
|
dev_err(&pdev->dev, |
|
"Allocation failed for affinity_mask for VF %d\n", |
|
cptvf->vfid); |
|
return; |
|
} |
|
|
|
cpu = cptvf->vfid % num_online_cpus(); |
|
cpumask_set_cpu(cpumask_local_spread(cpu, cptvf->node), |
|
cptvf->affinity_mask[vec]); |
|
irq_set_affinity_hint(pci_irq_vector(pdev, vec), |
|
cptvf->affinity_mask[vec]); |
|
} |
|
|
|
static void cptvf_write_vq_saddr(struct otx_cptvf *cptvf, u64 val) |
|
{ |
|
union otx_cptx_vqx_saddr vqx_saddr; |
|
|
|
vqx_saddr.u = val; |
|
writeq(vqx_saddr.u, cptvf->reg_base + OTX_CPT_VQX_SADDR(0)); |
|
} |
|
|
|
static void cptvf_device_init(struct otx_cptvf *cptvf) |
|
{ |
|
u64 base_addr = 0; |
|
|
|
/* Disable the VQ */ |
|
cptvf_write_vq_ctl(cptvf, 0); |
|
/* Reset the doorbell */ |
|
otx_cptvf_write_vq_doorbell(cptvf, 0); |
|
/* Clear inflight */ |
|
cptvf_write_vq_inprog(cptvf, 0); |
|
/* Write VQ SADDR */ |
|
base_addr = (u64)(cptvf->cqinfo.queue[0].qhead->dma_addr); |
|
cptvf_write_vq_saddr(cptvf, base_addr); |
|
/* Configure timerhold / coalescence */ |
|
cptvf_write_vq_done_timewait(cptvf, OTX_CPT_TIMER_HOLD); |
|
cptvf_write_vq_done_numwait(cptvf, OTX_CPT_COUNT_HOLD); |
|
/* Enable the VQ */ |
|
cptvf_write_vq_ctl(cptvf, 1); |
|
/* Flag the VF ready */ |
|
cptvf->flags |= OTX_CPT_FLAG_DEVICE_READY; |
|
} |
|
|
|
static ssize_t vf_type_show(struct device *dev, |
|
struct device_attribute *attr, |
|
char *buf) |
|
{ |
|
struct otx_cptvf *cptvf = dev_get_drvdata(dev); |
|
char *msg; |
|
|
|
switch (cptvf->vftype) { |
|
case OTX_CPT_AE_TYPES: |
|
msg = "AE"; |
|
break; |
|
|
|
case OTX_CPT_SE_TYPES: |
|
msg = "SE"; |
|
break; |
|
|
|
default: |
|
msg = "Invalid"; |
|
} |
|
|
|
return scnprintf(buf, PAGE_SIZE, "%s\n", msg); |
|
} |
|
|
|
static ssize_t vf_engine_group_show(struct device *dev, |
|
struct device_attribute *attr, |
|
char *buf) |
|
{ |
|
struct otx_cptvf *cptvf = dev_get_drvdata(dev); |
|
|
|
return scnprintf(buf, PAGE_SIZE, "%d\n", cptvf->vfgrp); |
|
} |
|
|
|
static ssize_t vf_engine_group_store(struct device *dev, |
|
struct device_attribute *attr, |
|
const char *buf, size_t count) |
|
{ |
|
struct otx_cptvf *cptvf = dev_get_drvdata(dev); |
|
int val, ret; |
|
|
|
ret = kstrtoint(buf, 10, &val); |
|
if (ret) |
|
return ret; |
|
|
|
if (val < 0) |
|
return -EINVAL; |
|
|
|
if (val >= OTX_CPT_MAX_ENGINE_GROUPS) { |
|
dev_err(dev, "Engine group >= than max available groups %d\n", |
|
OTX_CPT_MAX_ENGINE_GROUPS); |
|
return -EINVAL; |
|
} |
|
|
|
ret = otx_cptvf_send_vf_to_grp_msg(cptvf, val); |
|
if (ret) |
|
return ret; |
|
|
|
return count; |
|
} |
|
|
|
static ssize_t vf_coalesc_time_wait_show(struct device *dev, |
|
struct device_attribute *attr, |
|
char *buf) |
|
{ |
|
struct otx_cptvf *cptvf = dev_get_drvdata(dev); |
|
|
|
return scnprintf(buf, PAGE_SIZE, "%d\n", |
|
cptvf_read_vq_done_timewait(cptvf)); |
|
} |
|
|
|
static ssize_t vf_coalesc_num_wait_show(struct device *dev, |
|
struct device_attribute *attr, |
|
char *buf) |
|
{ |
|
struct otx_cptvf *cptvf = dev_get_drvdata(dev); |
|
|
|
return scnprintf(buf, PAGE_SIZE, "%d\n", |
|
cptvf_read_vq_done_numwait(cptvf)); |
|
} |
|
|
|
static ssize_t vf_coalesc_time_wait_store(struct device *dev, |
|
struct device_attribute *attr, |
|
const char *buf, size_t count) |
|
{ |
|
struct otx_cptvf *cptvf = dev_get_drvdata(dev); |
|
long val; |
|
int ret; |
|
|
|
ret = kstrtol(buf, 10, &val); |
|
if (ret != 0) |
|
return ret; |
|
|
|
if (val < OTX_CPT_COALESC_MIN_TIME_WAIT || |
|
val > OTX_CPT_COALESC_MAX_TIME_WAIT) |
|
return -EINVAL; |
|
|
|
cptvf_write_vq_done_timewait(cptvf, val); |
|
return count; |
|
} |
|
|
|
static ssize_t vf_coalesc_num_wait_store(struct device *dev, |
|
struct device_attribute *attr, |
|
const char *buf, size_t count) |
|
{ |
|
struct otx_cptvf *cptvf = dev_get_drvdata(dev); |
|
long val; |
|
int ret; |
|
|
|
ret = kstrtol(buf, 10, &val); |
|
if (ret != 0) |
|
return ret; |
|
|
|
if (val < OTX_CPT_COALESC_MIN_NUM_WAIT || |
|
val > OTX_CPT_COALESC_MAX_NUM_WAIT) |
|
return -EINVAL; |
|
|
|
cptvf_write_vq_done_numwait(cptvf, val); |
|
return count; |
|
} |
|
|
|
static DEVICE_ATTR_RO(vf_type); |
|
static DEVICE_ATTR_RW(vf_engine_group); |
|
static DEVICE_ATTR_RW(vf_coalesc_time_wait); |
|
static DEVICE_ATTR_RW(vf_coalesc_num_wait); |
|
|
|
static struct attribute *otx_cptvf_attrs[] = { |
|
&dev_attr_vf_type.attr, |
|
&dev_attr_vf_engine_group.attr, |
|
&dev_attr_vf_coalesc_time_wait.attr, |
|
&dev_attr_vf_coalesc_num_wait.attr, |
|
NULL |
|
}; |
|
|
|
static const struct attribute_group otx_cptvf_sysfs_group = { |
|
.attrs = otx_cptvf_attrs, |
|
}; |
|
|
|
static int otx_cptvf_probe(struct pci_dev *pdev, |
|
const struct pci_device_id *ent) |
|
{ |
|
struct device *dev = &pdev->dev; |
|
struct otx_cptvf *cptvf; |
|
int err; |
|
|
|
cptvf = devm_kzalloc(dev, sizeof(*cptvf), GFP_KERNEL); |
|
if (!cptvf) |
|
return -ENOMEM; |
|
|
|
pci_set_drvdata(pdev, cptvf); |
|
cptvf->pdev = pdev; |
|
|
|
err = pci_enable_device(pdev); |
|
if (err) { |
|
dev_err(dev, "Failed to enable PCI device\n"); |
|
goto clear_drvdata; |
|
} |
|
err = pci_request_regions(pdev, DRV_NAME); |
|
if (err) { |
|
dev_err(dev, "PCI request regions failed 0x%x\n", err); |
|
goto disable_device; |
|
} |
|
err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(48)); |
|
if (err) { |
|
dev_err(dev, "Unable to get usable 48-bit DMA configuration\n"); |
|
goto release_regions; |
|
} |
|
|
|
/* MAP PF's configuration registers */ |
|
cptvf->reg_base = pci_iomap(pdev, OTX_CPT_VF_PCI_CFG_BAR, 0); |
|
if (!cptvf->reg_base) { |
|
dev_err(dev, "Cannot map config register space, aborting\n"); |
|
err = -ENOMEM; |
|
goto release_regions; |
|
} |
|
|
|
cptvf->node = dev_to_node(&pdev->dev); |
|
err = pci_alloc_irq_vectors(pdev, OTX_CPT_VF_MSIX_VECTORS, |
|
OTX_CPT_VF_MSIX_VECTORS, PCI_IRQ_MSIX); |
|
if (err < 0) { |
|
dev_err(dev, "Request for #%d msix vectors failed\n", |
|
OTX_CPT_VF_MSIX_VECTORS); |
|
goto unmap_region; |
|
} |
|
|
|
err = request_irq(pci_irq_vector(pdev, CPT_VF_INT_VEC_E_MISC), |
|
cptvf_misc_intr_handler, 0, "CPT VF misc intr", |
|
cptvf); |
|
if (err) { |
|
dev_err(dev, "Failed to request misc irq\n"); |
|
goto free_vectors; |
|
} |
|
|
|
/* Enable mailbox interrupt */ |
|
cptvf_enable_mbox_interrupts(cptvf); |
|
cptvf_enable_swerr_interrupts(cptvf); |
|
|
|
/* Check cpt pf status, gets chip ID / device Id from PF if ready */ |
|
err = otx_cptvf_check_pf_ready(cptvf); |
|
if (err) |
|
goto free_misc_irq; |
|
|
|
/* CPT VF software resources initialization */ |
|
cptvf->cqinfo.qchunksize = OTX_CPT_CMD_QCHUNK_SIZE; |
|
err = cptvf_sw_init(cptvf, OTX_CPT_CMD_QLEN, OTX_CPT_NUM_QS_PER_VF); |
|
if (err) { |
|
dev_err(dev, "cptvf_sw_init() failed\n"); |
|
goto free_misc_irq; |
|
} |
|
/* Convey VQ LEN to PF */ |
|
err = otx_cptvf_send_vq_size_msg(cptvf); |
|
if (err) |
|
goto sw_cleanup; |
|
|
|
/* CPT VF device initialization */ |
|
cptvf_device_init(cptvf); |
|
/* Send msg to PF to assign currnet Q to required group */ |
|
err = otx_cptvf_send_vf_to_grp_msg(cptvf, cptvf->vfgrp); |
|
if (err) |
|
goto sw_cleanup; |
|
|
|
cptvf->priority = 1; |
|
err = otx_cptvf_send_vf_priority_msg(cptvf); |
|
if (err) |
|
goto sw_cleanup; |
|
|
|
err = request_irq(pci_irq_vector(pdev, CPT_VF_INT_VEC_E_DONE), |
|
cptvf_done_intr_handler, 0, "CPT VF done intr", |
|
cptvf); |
|
if (err) { |
|
dev_err(dev, "Failed to request done irq\n"); |
|
goto free_done_irq; |
|
} |
|
|
|
/* Enable done interrupt */ |
|
cptvf_enable_done_interrupts(cptvf); |
|
|
|
/* Set irq affinity masks */ |
|
cptvf_set_irq_affinity(cptvf, CPT_VF_INT_VEC_E_MISC); |
|
cptvf_set_irq_affinity(cptvf, CPT_VF_INT_VEC_E_DONE); |
|
|
|
err = otx_cptvf_send_vf_up(cptvf); |
|
if (err) |
|
goto free_irq_affinity; |
|
|
|
/* Initialize algorithms and set ops */ |
|
err = otx_cpt_crypto_init(pdev, THIS_MODULE, |
|
cptvf->vftype == OTX_CPT_SE_TYPES ? OTX_CPT_SE : OTX_CPT_AE, |
|
cptvf->vftype, 1, cptvf->num_vfs); |
|
if (err) { |
|
dev_err(dev, "Failed to register crypto algs\n"); |
|
goto free_irq_affinity; |
|
} |
|
|
|
err = sysfs_create_group(&dev->kobj, &otx_cptvf_sysfs_group); |
|
if (err) { |
|
dev_err(dev, "Creating sysfs entries failed\n"); |
|
goto crypto_exit; |
|
} |
|
|
|
return 0; |
|
|
|
crypto_exit: |
|
otx_cpt_crypto_exit(pdev, THIS_MODULE, cptvf->vftype); |
|
free_irq_affinity: |
|
cptvf_free_irq_affinity(cptvf, CPT_VF_INT_VEC_E_DONE); |
|
cptvf_free_irq_affinity(cptvf, CPT_VF_INT_VEC_E_MISC); |
|
free_done_irq: |
|
free_irq(pci_irq_vector(pdev, CPT_VF_INT_VEC_E_DONE), cptvf); |
|
sw_cleanup: |
|
cptvf_sw_cleanup(cptvf); |
|
free_misc_irq: |
|
free_irq(pci_irq_vector(pdev, CPT_VF_INT_VEC_E_MISC), cptvf); |
|
free_vectors: |
|
pci_free_irq_vectors(cptvf->pdev); |
|
unmap_region: |
|
pci_iounmap(pdev, cptvf->reg_base); |
|
release_regions: |
|
pci_release_regions(pdev); |
|
disable_device: |
|
pci_disable_device(pdev); |
|
clear_drvdata: |
|
pci_set_drvdata(pdev, NULL); |
|
|
|
return err; |
|
} |
|
|
|
static void otx_cptvf_remove(struct pci_dev *pdev) |
|
{ |
|
struct otx_cptvf *cptvf = pci_get_drvdata(pdev); |
|
|
|
if (!cptvf) { |
|
dev_err(&pdev->dev, "Invalid CPT-VF device\n"); |
|
return; |
|
} |
|
|
|
/* Convey DOWN to PF */ |
|
if (otx_cptvf_send_vf_down(cptvf)) { |
|
dev_err(&pdev->dev, "PF not responding to DOWN msg\n"); |
|
} else { |
|
sysfs_remove_group(&pdev->dev.kobj, &otx_cptvf_sysfs_group); |
|
otx_cpt_crypto_exit(pdev, THIS_MODULE, cptvf->vftype); |
|
cptvf_free_irq_affinity(cptvf, CPT_VF_INT_VEC_E_DONE); |
|
cptvf_free_irq_affinity(cptvf, CPT_VF_INT_VEC_E_MISC); |
|
free_irq(pci_irq_vector(pdev, CPT_VF_INT_VEC_E_DONE), cptvf); |
|
free_irq(pci_irq_vector(pdev, CPT_VF_INT_VEC_E_MISC), cptvf); |
|
cptvf_sw_cleanup(cptvf); |
|
pci_free_irq_vectors(cptvf->pdev); |
|
pci_iounmap(pdev, cptvf->reg_base); |
|
pci_release_regions(pdev); |
|
pci_disable_device(pdev); |
|
pci_set_drvdata(pdev, NULL); |
|
} |
|
} |
|
|
|
/* Supported devices */ |
|
static const struct pci_device_id otx_cptvf_id_table[] = { |
|
{PCI_VDEVICE(CAVIUM, OTX_CPT_PCI_VF_DEVICE_ID), 0}, |
|
{ 0, } /* end of table */ |
|
}; |
|
|
|
static struct pci_driver otx_cptvf_pci_driver = { |
|
.name = DRV_NAME, |
|
.id_table = otx_cptvf_id_table, |
|
.probe = otx_cptvf_probe, |
|
.remove = otx_cptvf_remove, |
|
}; |
|
|
|
module_pci_driver(otx_cptvf_pci_driver); |
|
|
|
MODULE_AUTHOR("Marvell International Ltd."); |
|
MODULE_DESCRIPTION("Marvell OcteonTX CPT Virtual Function Driver"); |
|
MODULE_LICENSE("GPL v2"); |
|
MODULE_VERSION(DRV_VERSION); |
|
MODULE_DEVICE_TABLE(pci, otx_cptvf_id_table);
|
|
|