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180 lines
5.4 KiB
180 lines
5.4 KiB
/* SPDX-License-Identifier: GPL-2.0 |
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* Marvell OcteonTX CPT driver |
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* |
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* Copyright (C) 2019 Marvell International Ltd. |
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* |
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* This program is free software; you can redistribute it and/or modify |
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* it under the terms of the GNU General Public License version 2 as |
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* published by the Free Software Foundation. |
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*/ |
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#ifndef __OTX_CPTPF_UCODE_H |
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#define __OTX_CPTPF_UCODE_H |
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#include <linux/pci.h> |
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#include <linux/types.h> |
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#include <linux/module.h> |
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#include "otx_cpt_hw_types.h" |
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/* CPT ucode name maximum length */ |
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#define OTX_CPT_UCODE_NAME_LENGTH 64 |
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/* |
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* On OcteonTX 83xx platform, only one type of engines is allowed to be |
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* attached to an engine group. |
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*/ |
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#define OTX_CPT_MAX_ETYPES_PER_GRP 1 |
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/* Default tar archive file names */ |
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#define OTX_CPT_UCODE_TAR_FILE_NAME "cpt8x-mc.tar" |
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/* CPT ucode alignment */ |
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#define OTX_CPT_UCODE_ALIGNMENT 128 |
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/* CPT ucode signature size */ |
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#define OTX_CPT_UCODE_SIGN_LEN 256 |
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/* Microcode version string length */ |
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#define OTX_CPT_UCODE_VER_STR_SZ 44 |
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/* Maximum number of supported engines/cores on OcteonTX 83XX platform */ |
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#define OTX_CPT_MAX_ENGINES 64 |
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#define OTX_CPT_ENGS_BITMASK_LEN (OTX_CPT_MAX_ENGINES/(BITS_PER_BYTE * \ |
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sizeof(unsigned long))) |
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/* Microcode types */ |
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enum otx_cpt_ucode_type { |
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OTX_CPT_AE_UC_TYPE = 1, /* AE-MAIN */ |
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OTX_CPT_SE_UC_TYPE1 = 20, /* SE-MAIN - combination of 21 and 22 */ |
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OTX_CPT_SE_UC_TYPE2 = 21, /* Fast Path IPSec + AirCrypto */ |
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OTX_CPT_SE_UC_TYPE3 = 22, /* |
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* Hash + HMAC + FlexiCrypto + RNG + Full |
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* Feature IPSec + AirCrypto + Kasumi |
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*/ |
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}; |
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struct otx_cpt_bitmap { |
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unsigned long bits[OTX_CPT_ENGS_BITMASK_LEN]; |
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int size; |
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}; |
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struct otx_cpt_engines { |
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int type; |
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int count; |
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}; |
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/* Microcode version number */ |
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struct otx_cpt_ucode_ver_num { |
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u8 nn; |
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u8 xx; |
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u8 yy; |
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u8 zz; |
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}; |
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struct otx_cpt_ucode_hdr { |
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struct otx_cpt_ucode_ver_num ver_num; |
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u8 ver_str[OTX_CPT_UCODE_VER_STR_SZ]; |
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__be32 code_length; |
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u32 padding[3]; |
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}; |
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struct otx_cpt_ucode { |
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u8 ver_str[OTX_CPT_UCODE_VER_STR_SZ];/* |
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* ucode version in readable format |
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*/ |
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struct otx_cpt_ucode_ver_num ver_num;/* ucode version number */ |
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char filename[OTX_CPT_UCODE_NAME_LENGTH]; /* ucode filename */ |
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dma_addr_t dma; /* phys address of ucode image */ |
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dma_addr_t align_dma; /* aligned phys address of ucode image */ |
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void *va; /* virt address of ucode image */ |
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void *align_va; /* aligned virt address of ucode image */ |
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u32 size; /* ucode image size */ |
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int type; /* ucode image type SE or AE */ |
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}; |
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struct tar_ucode_info_t { |
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struct list_head list; |
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struct otx_cpt_ucode ucode;/* microcode information */ |
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const u8 *ucode_ptr; /* pointer to microcode in tar archive */ |
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}; |
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/* Maximum and current number of engines available for all engine groups */ |
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struct otx_cpt_engs_available { |
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int max_se_cnt; |
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int max_ae_cnt; |
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int se_cnt; |
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int ae_cnt; |
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}; |
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/* Engines reserved to an engine group */ |
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struct otx_cpt_engs_rsvd { |
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int type; /* engine type */ |
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int count; /* number of engines attached */ |
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int offset; /* constant offset of engine type in the bitmap */ |
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unsigned long *bmap; /* attached engines bitmap */ |
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struct otx_cpt_ucode *ucode; /* ucode used by these engines */ |
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}; |
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struct otx_cpt_mirror_info { |
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int is_ena; /* |
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* is mirroring enabled, it is set only for engine |
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* group which mirrors another engine group |
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*/ |
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int idx; /* |
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* index of engine group which is mirrored by this |
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* group, set only for engine group which mirrors |
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* another group |
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*/ |
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int ref_count; /* |
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* number of times this engine group is mirrored by |
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* other groups, this is set only for engine group |
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* which is mirrored by other group(s) |
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*/ |
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}; |
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struct otx_cpt_eng_grp_info { |
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struct otx_cpt_eng_grps *g; /* pointer to engine_groups structure */ |
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struct device_attribute info_attr; /* group info entry attr */ |
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/* engines attached */ |
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struct otx_cpt_engs_rsvd engs[OTX_CPT_MAX_ETYPES_PER_GRP]; |
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/* Microcode information */ |
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struct otx_cpt_ucode ucode[OTX_CPT_MAX_ETYPES_PER_GRP]; |
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/* sysfs info entry name */ |
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char sysfs_info_name[OTX_CPT_UCODE_NAME_LENGTH]; |
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/* engine group mirroring information */ |
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struct otx_cpt_mirror_info mirror; |
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int idx; /* engine group index */ |
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bool is_enabled; /* |
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* is engine group enabled, engine group is enabled |
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* when it has engines attached and ucode loaded |
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*/ |
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}; |
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struct otx_cpt_eng_grps { |
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struct otx_cpt_eng_grp_info grp[OTX_CPT_MAX_ENGINE_GROUPS]; |
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struct device_attribute ucode_load_attr;/* ucode load attr */ |
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struct otx_cpt_engs_available avail; |
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struct mutex lock; |
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void *obj; |
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int engs_num; /* total number of engines supported */ |
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int eng_types_supported; /* engine types supported SE, AE */ |
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u8 eng_ref_cnt[OTX_CPT_MAX_ENGINES];/* engines reference count */ |
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bool is_ucode_load_created; /* is ucode_load sysfs entry created */ |
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bool is_first_try; /* is this first try to create kcrypto engine grp */ |
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bool is_rdonly; /* do engine groups configuration can be modified */ |
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}; |
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int otx_cpt_init_eng_grps(struct pci_dev *pdev, |
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struct otx_cpt_eng_grps *eng_grps, int pf_type); |
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void otx_cpt_cleanup_eng_grps(struct pci_dev *pdev, |
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struct otx_cpt_eng_grps *eng_grps); |
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int otx_cpt_try_create_default_eng_grps(struct pci_dev *pdev, |
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struct otx_cpt_eng_grps *eng_grps, |
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int pf_type); |
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void otx_cpt_set_eng_grps_is_rdonly(struct otx_cpt_eng_grps *eng_grps, |
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bool is_rdonly); |
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int otx_cpt_uc_supports_eng_type(struct otx_cpt_ucode *ucode, int eng_type); |
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int otx_cpt_eng_grp_has_eng_type(struct otx_cpt_eng_grp_info *eng_grp, |
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int eng_type); |
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#endif /* __OTX_CPTPF_UCODE_H */
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