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915 lines
25 KiB
/* SPDX-License-Identifier: GPL-2.0 */ |
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#ifndef __MARVELL_CESA_H__ |
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#define __MARVELL_CESA_H__ |
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#include <crypto/internal/hash.h> |
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#include <crypto/internal/skcipher.h> |
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#include <linux/dma-direction.h> |
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#include <linux/dmapool.h> |
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#define CESA_ENGINE_OFF(i) (((i) * 0x2000)) |
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#define CESA_TDMA_BYTE_CNT 0x800 |
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#define CESA_TDMA_SRC_ADDR 0x810 |
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#define CESA_TDMA_DST_ADDR 0x820 |
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#define CESA_TDMA_NEXT_ADDR 0x830 |
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#define CESA_TDMA_CONTROL 0x840 |
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#define CESA_TDMA_DST_BURST GENMASK(2, 0) |
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#define CESA_TDMA_DST_BURST_32B 3 |
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#define CESA_TDMA_DST_BURST_128B 4 |
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#define CESA_TDMA_OUT_RD_EN BIT(4) |
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#define CESA_TDMA_SRC_BURST GENMASK(8, 6) |
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#define CESA_TDMA_SRC_BURST_32B (3 << 6) |
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#define CESA_TDMA_SRC_BURST_128B (4 << 6) |
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#define CESA_TDMA_CHAIN BIT(9) |
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#define CESA_TDMA_BYTE_SWAP BIT(11) |
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#define CESA_TDMA_NO_BYTE_SWAP BIT(11) |
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#define CESA_TDMA_EN BIT(12) |
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#define CESA_TDMA_FETCH_ND BIT(13) |
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#define CESA_TDMA_ACT BIT(14) |
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#define CESA_TDMA_CUR 0x870 |
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#define CESA_TDMA_ERROR_CAUSE 0x8c8 |
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#define CESA_TDMA_ERROR_MSK 0x8cc |
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#define CESA_TDMA_WINDOW_BASE(x) (((x) * 0x8) + 0xa00) |
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#define CESA_TDMA_WINDOW_CTRL(x) (((x) * 0x8) + 0xa04) |
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#define CESA_IVDIG(x) (0xdd00 + ((x) * 4) + \ |
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(((x) < 5) ? 0 : 0x14)) |
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#define CESA_SA_CMD 0xde00 |
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#define CESA_SA_CMD_EN_CESA_SA_ACCL0 BIT(0) |
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#define CESA_SA_CMD_EN_CESA_SA_ACCL1 BIT(1) |
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#define CESA_SA_CMD_DISABLE_SEC BIT(2) |
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#define CESA_SA_DESC_P0 0xde04 |
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#define CESA_SA_DESC_P1 0xde14 |
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#define CESA_SA_CFG 0xde08 |
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#define CESA_SA_CFG_STOP_DIG_ERR GENMASK(1, 0) |
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#define CESA_SA_CFG_DIG_ERR_CONT 0 |
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#define CESA_SA_CFG_DIG_ERR_SKIP 1 |
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#define CESA_SA_CFG_DIG_ERR_STOP 3 |
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#define CESA_SA_CFG_CH0_W_IDMA BIT(7) |
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#define CESA_SA_CFG_CH1_W_IDMA BIT(8) |
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#define CESA_SA_CFG_ACT_CH0_IDMA BIT(9) |
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#define CESA_SA_CFG_ACT_CH1_IDMA BIT(10) |
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#define CESA_SA_CFG_MULTI_PKT BIT(11) |
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#define CESA_SA_CFG_PARA_DIS BIT(13) |
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#define CESA_SA_ACCEL_STATUS 0xde0c |
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#define CESA_SA_ST_ACT_0 BIT(0) |
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#define CESA_SA_ST_ACT_1 BIT(1) |
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/* |
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* CESA_SA_FPGA_INT_STATUS looks like an FPGA leftover and is documented only |
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* in Errata 4.12. It looks like that it was part of an IRQ-controller in FPGA |
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* and someone forgot to remove it while switching to the core and moving to |
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* CESA_SA_INT_STATUS. |
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*/ |
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#define CESA_SA_FPGA_INT_STATUS 0xdd68 |
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#define CESA_SA_INT_STATUS 0xde20 |
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#define CESA_SA_INT_AUTH_DONE BIT(0) |
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#define CESA_SA_INT_DES_E_DONE BIT(1) |
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#define CESA_SA_INT_AES_E_DONE BIT(2) |
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#define CESA_SA_INT_AES_D_DONE BIT(3) |
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#define CESA_SA_INT_ENC_DONE BIT(4) |
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#define CESA_SA_INT_ACCEL0_DONE BIT(5) |
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#define CESA_SA_INT_ACCEL1_DONE BIT(6) |
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#define CESA_SA_INT_ACC0_IDMA_DONE BIT(7) |
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#define CESA_SA_INT_ACC1_IDMA_DONE BIT(8) |
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#define CESA_SA_INT_IDMA_DONE BIT(9) |
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#define CESA_SA_INT_IDMA_OWN_ERR BIT(10) |
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#define CESA_SA_INT_MSK 0xde24 |
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#define CESA_SA_DESC_CFG_OP_MAC_ONLY 0 |
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#define CESA_SA_DESC_CFG_OP_CRYPT_ONLY 1 |
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#define CESA_SA_DESC_CFG_OP_MAC_CRYPT 2 |
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#define CESA_SA_DESC_CFG_OP_CRYPT_MAC 3 |
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#define CESA_SA_DESC_CFG_OP_MSK GENMASK(1, 0) |
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#define CESA_SA_DESC_CFG_MACM_SHA256 (1 << 4) |
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#define CESA_SA_DESC_CFG_MACM_HMAC_SHA256 (3 << 4) |
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#define CESA_SA_DESC_CFG_MACM_MD5 (4 << 4) |
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#define CESA_SA_DESC_CFG_MACM_SHA1 (5 << 4) |
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#define CESA_SA_DESC_CFG_MACM_HMAC_MD5 (6 << 4) |
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#define CESA_SA_DESC_CFG_MACM_HMAC_SHA1 (7 << 4) |
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#define CESA_SA_DESC_CFG_MACM_MSK GENMASK(6, 4) |
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#define CESA_SA_DESC_CFG_CRYPTM_DES (1 << 8) |
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#define CESA_SA_DESC_CFG_CRYPTM_3DES (2 << 8) |
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#define CESA_SA_DESC_CFG_CRYPTM_AES (3 << 8) |
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#define CESA_SA_DESC_CFG_CRYPTM_MSK GENMASK(9, 8) |
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#define CESA_SA_DESC_CFG_DIR_ENC (0 << 12) |
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#define CESA_SA_DESC_CFG_DIR_DEC (1 << 12) |
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#define CESA_SA_DESC_CFG_CRYPTCM_ECB (0 << 16) |
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#define CESA_SA_DESC_CFG_CRYPTCM_CBC (1 << 16) |
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#define CESA_SA_DESC_CFG_CRYPTCM_MSK BIT(16) |
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#define CESA_SA_DESC_CFG_3DES_EEE (0 << 20) |
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#define CESA_SA_DESC_CFG_3DES_EDE (1 << 20) |
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#define CESA_SA_DESC_CFG_AES_LEN_128 (0 << 24) |
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#define CESA_SA_DESC_CFG_AES_LEN_192 (1 << 24) |
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#define CESA_SA_DESC_CFG_AES_LEN_256 (2 << 24) |
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#define CESA_SA_DESC_CFG_AES_LEN_MSK GENMASK(25, 24) |
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#define CESA_SA_DESC_CFG_NOT_FRAG (0 << 30) |
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#define CESA_SA_DESC_CFG_FIRST_FRAG (1 << 30) |
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#define CESA_SA_DESC_CFG_LAST_FRAG (2 << 30) |
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#define CESA_SA_DESC_CFG_MID_FRAG (3 << 30) |
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#define CESA_SA_DESC_CFG_FRAG_MSK GENMASK(31, 30) |
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/* |
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* /-----------\ 0 |
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* | ACCEL CFG | 4 * 8 |
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* |-----------| 0x20 |
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* | CRYPT KEY | 8 * 4 |
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* |-----------| 0x40 |
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* | IV IN | 4 * 4 |
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* |-----------| 0x40 (inplace) |
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* | IV BUF | 4 * 4 |
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* |-----------| 0x80 |
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* | DATA IN | 16 * x (max ->max_req_size) |
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* |-----------| 0x80 (inplace operation) |
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* | DATA OUT | 16 * x (max ->max_req_size) |
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* \-----------/ SRAM size |
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*/ |
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/* |
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* Hashing memory map: |
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* /-----------\ 0 |
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* | ACCEL CFG | 4 * 8 |
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* |-----------| 0x20 |
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* | Inner IV | 8 * 4 |
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* |-----------| 0x40 |
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* | Outer IV | 8 * 4 |
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* |-----------| 0x60 |
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* | Output BUF| 8 * 4 |
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* |-----------| 0x80 |
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* | DATA IN | 64 * x (max ->max_req_size) |
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* \-----------/ SRAM size |
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*/ |
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#define CESA_SA_CFG_SRAM_OFFSET 0x00 |
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#define CESA_SA_DATA_SRAM_OFFSET 0x80 |
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#define CESA_SA_CRYPT_KEY_SRAM_OFFSET 0x20 |
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#define CESA_SA_CRYPT_IV_SRAM_OFFSET 0x40 |
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#define CESA_SA_MAC_IIV_SRAM_OFFSET 0x20 |
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#define CESA_SA_MAC_OIV_SRAM_OFFSET 0x40 |
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#define CESA_SA_MAC_DIG_SRAM_OFFSET 0x60 |
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#define CESA_SA_DESC_CRYPT_DATA(offset) \ |
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cpu_to_le32((CESA_SA_DATA_SRAM_OFFSET + (offset)) | \ |
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((CESA_SA_DATA_SRAM_OFFSET + (offset)) << 16)) |
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#define CESA_SA_DESC_CRYPT_IV(offset) \ |
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cpu_to_le32((CESA_SA_CRYPT_IV_SRAM_OFFSET + (offset)) | \ |
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((CESA_SA_CRYPT_IV_SRAM_OFFSET + (offset)) << 16)) |
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#define CESA_SA_DESC_CRYPT_KEY(offset) \ |
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cpu_to_le32(CESA_SA_CRYPT_KEY_SRAM_OFFSET + (offset)) |
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#define CESA_SA_DESC_MAC_DATA(offset) \ |
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cpu_to_le32(CESA_SA_DATA_SRAM_OFFSET + (offset)) |
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#define CESA_SA_DESC_MAC_DATA_MSK cpu_to_le32(GENMASK(15, 0)) |
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#define CESA_SA_DESC_MAC_TOTAL_LEN(total_len) cpu_to_le32((total_len) << 16) |
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#define CESA_SA_DESC_MAC_TOTAL_LEN_MSK cpu_to_le32(GENMASK(31, 16)) |
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#define CESA_SA_DESC_MAC_SRC_TOTAL_LEN_MAX 0xffff |
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#define CESA_SA_DESC_MAC_DIGEST(offset) \ |
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cpu_to_le32(CESA_SA_MAC_DIG_SRAM_OFFSET + (offset)) |
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#define CESA_SA_DESC_MAC_DIGEST_MSK cpu_to_le32(GENMASK(15, 0)) |
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#define CESA_SA_DESC_MAC_FRAG_LEN(frag_len) cpu_to_le32((frag_len) << 16) |
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#define CESA_SA_DESC_MAC_FRAG_LEN_MSK cpu_to_le32(GENMASK(31, 16)) |
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#define CESA_SA_DESC_MAC_IV(offset) \ |
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cpu_to_le32((CESA_SA_MAC_IIV_SRAM_OFFSET + (offset)) | \ |
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((CESA_SA_MAC_OIV_SRAM_OFFSET + (offset)) << 16)) |
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#define CESA_SA_SRAM_SIZE 2048 |
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#define CESA_SA_SRAM_PAYLOAD_SIZE (cesa_dev->sram_size - \ |
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CESA_SA_DATA_SRAM_OFFSET) |
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#define CESA_SA_DEFAULT_SRAM_SIZE 2048 |
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#define CESA_SA_MIN_SRAM_SIZE 1024 |
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#define CESA_SA_SRAM_MSK (2048 - 1) |
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#define CESA_MAX_HASH_BLOCK_SIZE 64 |
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#define CESA_HASH_BLOCK_SIZE_MSK (CESA_MAX_HASH_BLOCK_SIZE - 1) |
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/** |
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* struct mv_cesa_sec_accel_desc - security accelerator descriptor |
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* @config: engine config |
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* @enc_p: input and output data pointers for a cipher operation |
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* @enc_len: cipher operation length |
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* @enc_key_p: cipher key pointer |
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* @enc_iv: cipher IV pointers |
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* @mac_src_p: input pointer and total hash length |
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* @mac_digest: digest pointer and hash operation length |
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* @mac_iv: hmac IV pointers |
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* |
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* Structure passed to the CESA engine to describe the crypto operation |
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* to be executed. |
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*/ |
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struct mv_cesa_sec_accel_desc { |
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__le32 config; |
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__le32 enc_p; |
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__le32 enc_len; |
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__le32 enc_key_p; |
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__le32 enc_iv; |
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__le32 mac_src_p; |
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__le32 mac_digest; |
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__le32 mac_iv; |
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}; |
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/** |
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* struct mv_cesa_skcipher_op_ctx - cipher operation context |
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* @key: cipher key |
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* @iv: cipher IV |
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* |
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* Context associated to a cipher operation. |
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*/ |
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struct mv_cesa_skcipher_op_ctx { |
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__le32 key[8]; |
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u32 iv[4]; |
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}; |
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/** |
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* struct mv_cesa_hash_op_ctx - hash or hmac operation context |
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* @key: cipher key |
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* @iv: cipher IV |
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* |
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* Context associated to an hash or hmac operation. |
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*/ |
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struct mv_cesa_hash_op_ctx { |
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u32 iv[16]; |
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__le32 hash[8]; |
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}; |
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/** |
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* struct mv_cesa_op_ctx - crypto operation context |
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* @desc: CESA descriptor |
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* @ctx: context associated to the crypto operation |
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* |
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* Context associated to a crypto operation. |
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*/ |
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struct mv_cesa_op_ctx { |
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struct mv_cesa_sec_accel_desc desc; |
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union { |
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struct mv_cesa_skcipher_op_ctx skcipher; |
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struct mv_cesa_hash_op_ctx hash; |
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} ctx; |
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}; |
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/* TDMA descriptor flags */ |
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#define CESA_TDMA_DST_IN_SRAM BIT(31) |
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#define CESA_TDMA_SRC_IN_SRAM BIT(30) |
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#define CESA_TDMA_END_OF_REQ BIT(29) |
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#define CESA_TDMA_BREAK_CHAIN BIT(28) |
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#define CESA_TDMA_SET_STATE BIT(27) |
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#define CESA_TDMA_TYPE_MSK GENMASK(26, 0) |
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#define CESA_TDMA_DUMMY 0 |
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#define CESA_TDMA_DATA 1 |
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#define CESA_TDMA_OP 2 |
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#define CESA_TDMA_RESULT 3 |
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/** |
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* struct mv_cesa_tdma_desc - TDMA descriptor |
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* @byte_cnt: number of bytes to transfer |
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* @src: DMA address of the source |
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* @dst: DMA address of the destination |
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* @next_dma: DMA address of the next TDMA descriptor |
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* @cur_dma: DMA address of this TDMA descriptor |
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* @next: pointer to the next TDMA descriptor |
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* @op: CESA operation attached to this TDMA descriptor |
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* @data: raw data attached to this TDMA descriptor |
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* @flags: flags describing the TDMA transfer. See the |
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* "TDMA descriptor flags" section above |
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* |
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* TDMA descriptor used to create a transfer chain describing a crypto |
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* operation. |
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*/ |
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struct mv_cesa_tdma_desc { |
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__le32 byte_cnt; |
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union { |
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__le32 src; |
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u32 src_dma; |
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}; |
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union { |
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__le32 dst; |
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u32 dst_dma; |
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}; |
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__le32 next_dma; |
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/* Software state */ |
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dma_addr_t cur_dma; |
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struct mv_cesa_tdma_desc *next; |
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union { |
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struct mv_cesa_op_ctx *op; |
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void *data; |
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}; |
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u32 flags; |
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}; |
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/** |
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* struct mv_cesa_sg_dma_iter - scatter-gather iterator |
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* @dir: transfer direction |
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* @sg: scatter list |
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* @offset: current position in the scatter list |
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* @op_offset: current position in the crypto operation |
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* |
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* Iterator used to iterate over a scatterlist while creating a TDMA chain for |
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* a crypto operation. |
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*/ |
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struct mv_cesa_sg_dma_iter { |
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enum dma_data_direction dir; |
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struct scatterlist *sg; |
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unsigned int offset; |
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unsigned int op_offset; |
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}; |
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/** |
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* struct mv_cesa_dma_iter - crypto operation iterator |
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* @len: the crypto operation length |
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* @offset: current position in the crypto operation |
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* @op_len: sub-operation length (the crypto engine can only act on 2kb |
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* chunks) |
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* |
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* Iterator used to create a TDMA chain for a given crypto operation. |
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*/ |
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struct mv_cesa_dma_iter { |
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unsigned int len; |
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unsigned int offset; |
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unsigned int op_len; |
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}; |
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/** |
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* struct mv_cesa_tdma_chain - TDMA chain |
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* @first: first entry in the TDMA chain |
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* @last: last entry in the TDMA chain |
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* |
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* Stores a TDMA chain for a specific crypto operation. |
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*/ |
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struct mv_cesa_tdma_chain { |
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struct mv_cesa_tdma_desc *first; |
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struct mv_cesa_tdma_desc *last; |
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}; |
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struct mv_cesa_engine; |
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/** |
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* struct mv_cesa_caps - CESA device capabilities |
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* @engines: number of engines |
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* @has_tdma: whether this device has a TDMA block |
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* @cipher_algs: supported cipher algorithms |
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* @ncipher_algs: number of supported cipher algorithms |
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* @ahash_algs: supported hash algorithms |
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* @nahash_algs: number of supported hash algorithms |
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* |
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* Structure used to describe CESA device capabilities. |
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*/ |
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struct mv_cesa_caps { |
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int nengines; |
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bool has_tdma; |
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struct skcipher_alg **cipher_algs; |
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int ncipher_algs; |
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struct ahash_alg **ahash_algs; |
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int nahash_algs; |
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}; |
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/** |
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* struct mv_cesa_dev_dma - DMA pools |
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* @tdma_desc_pool: TDMA desc pool |
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* @op_pool: crypto operation pool |
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* @cache_pool: data cache pool (used by hash implementation when the |
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* hash request is smaller than the hash block size) |
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* @padding_pool: padding pool (used by hash implementation when hardware |
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* padding cannot be used) |
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* |
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* Structure containing the different DMA pools used by this driver. |
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*/ |
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struct mv_cesa_dev_dma { |
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struct dma_pool *tdma_desc_pool; |
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struct dma_pool *op_pool; |
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struct dma_pool *cache_pool; |
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struct dma_pool *padding_pool; |
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}; |
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/** |
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* struct mv_cesa_dev - CESA device |
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* @caps: device capabilities |
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* @regs: device registers |
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* @sram_size: usable SRAM size |
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* @lock: device lock |
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* @engines: array of engines |
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* @dma: dma pools |
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* |
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* Structure storing CESA device information. |
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*/ |
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struct mv_cesa_dev { |
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const struct mv_cesa_caps *caps; |
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void __iomem *regs; |
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struct device *dev; |
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unsigned int sram_size; |
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spinlock_t lock; |
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struct mv_cesa_engine *engines; |
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struct mv_cesa_dev_dma *dma; |
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}; |
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/** |
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* struct mv_cesa_engine - CESA engine |
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* @id: engine id |
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* @regs: engine registers |
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* @sram: SRAM memory region |
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* @sram_pool: SRAM memory region from pool |
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* @sram_dma: DMA address of the SRAM memory region |
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* @lock: engine lock |
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* @req: current crypto request |
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* @clk: engine clk |
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* @zclk: engine zclk |
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* @max_req_len: maximum chunk length (useful to create the TDMA chain) |
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* @int_mask: interrupt mask cache |
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* @pool: memory pool pointing to the memory region reserved in |
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* SRAM |
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* @queue: fifo of the pending crypto requests |
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* @load: engine load counter, useful for load balancing |
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* @chain: list of the current tdma descriptors being processed |
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* by this engine. |
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* @complete_queue: fifo of the processed requests by the engine |
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* |
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* Structure storing CESA engine information. |
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*/ |
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struct mv_cesa_engine { |
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int id; |
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void __iomem *regs; |
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union { |
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void __iomem *sram; |
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void *sram_pool; |
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}; |
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dma_addr_t sram_dma; |
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spinlock_t lock; |
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struct crypto_async_request *req; |
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struct clk *clk; |
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struct clk *zclk; |
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size_t max_req_len; |
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u32 int_mask; |
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struct gen_pool *pool; |
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struct crypto_queue queue; |
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atomic_t load; |
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struct mv_cesa_tdma_chain chain; |
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struct list_head complete_queue; |
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int irq; |
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}; |
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/** |
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* struct mv_cesa_req_ops - CESA request operations |
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* @process: process a request chunk result (should return 0 if the |
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* operation, -EINPROGRESS if it needs more steps or an error |
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* code) |
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* @step: launch the crypto operation on the next chunk |
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* @cleanup: cleanup the crypto request (release associated data) |
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* @complete: complete the request, i.e copy result or context from sram when |
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* needed. |
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*/ |
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struct mv_cesa_req_ops { |
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int (*process)(struct crypto_async_request *req, u32 status); |
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void (*step)(struct crypto_async_request *req); |
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void (*cleanup)(struct crypto_async_request *req); |
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void (*complete)(struct crypto_async_request *req); |
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}; |
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/** |
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* struct mv_cesa_ctx - CESA operation context |
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* @ops: crypto operations |
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* |
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* Base context structure inherited by operation specific ones. |
|
*/ |
|
struct mv_cesa_ctx { |
|
const struct mv_cesa_req_ops *ops; |
|
}; |
|
|
|
/** |
|
* struct mv_cesa_hash_ctx - CESA hash operation context |
|
* @base: base context structure |
|
* |
|
* Hash context structure. |
|
*/ |
|
struct mv_cesa_hash_ctx { |
|
struct mv_cesa_ctx base; |
|
}; |
|
|
|
/** |
|
* struct mv_cesa_hash_ctx - CESA hmac operation context |
|
* @base: base context structure |
|
* @iv: initialization vectors |
|
* |
|
* HMAC context structure. |
|
*/ |
|
struct mv_cesa_hmac_ctx { |
|
struct mv_cesa_ctx base; |
|
__be32 iv[16]; |
|
}; |
|
|
|
/** |
|
* enum mv_cesa_req_type - request type definitions |
|
* @CESA_STD_REQ: standard request |
|
* @CESA_DMA_REQ: DMA request |
|
*/ |
|
enum mv_cesa_req_type { |
|
CESA_STD_REQ, |
|
CESA_DMA_REQ, |
|
}; |
|
|
|
/** |
|
* struct mv_cesa_req - CESA request |
|
* @engine: engine associated with this request |
|
* @chain: list of tdma descriptors associated with this request |
|
*/ |
|
struct mv_cesa_req { |
|
struct mv_cesa_engine *engine; |
|
struct mv_cesa_tdma_chain chain; |
|
}; |
|
|
|
/** |
|
* struct mv_cesa_sg_std_iter - CESA scatter-gather iterator for standard |
|
* requests |
|
* @iter: sg mapping iterator |
|
* @offset: current offset in the SG entry mapped in memory |
|
*/ |
|
struct mv_cesa_sg_std_iter { |
|
struct sg_mapping_iter iter; |
|
unsigned int offset; |
|
}; |
|
|
|
/** |
|
* struct mv_cesa_skcipher_std_req - cipher standard request |
|
* @op: operation context |
|
* @offset: current operation offset |
|
* @size: size of the crypto operation |
|
*/ |
|
struct mv_cesa_skcipher_std_req { |
|
struct mv_cesa_op_ctx op; |
|
unsigned int offset; |
|
unsigned int size; |
|
bool skip_ctx; |
|
}; |
|
|
|
/** |
|
* struct mv_cesa_skcipher_req - cipher request |
|
* @req: type specific request information |
|
* @src_nents: number of entries in the src sg list |
|
* @dst_nents: number of entries in the dest sg list |
|
*/ |
|
struct mv_cesa_skcipher_req { |
|
struct mv_cesa_req base; |
|
struct mv_cesa_skcipher_std_req std; |
|
int src_nents; |
|
int dst_nents; |
|
}; |
|
|
|
/** |
|
* struct mv_cesa_ahash_std_req - standard hash request |
|
* @offset: current operation offset |
|
*/ |
|
struct mv_cesa_ahash_std_req { |
|
unsigned int offset; |
|
}; |
|
|
|
/** |
|
* struct mv_cesa_ahash_dma_req - DMA hash request |
|
* @padding: padding buffer |
|
* @padding_dma: DMA address of the padding buffer |
|
* @cache_dma: DMA address of the cache buffer |
|
*/ |
|
struct mv_cesa_ahash_dma_req { |
|
u8 *padding; |
|
dma_addr_t padding_dma; |
|
u8 *cache; |
|
dma_addr_t cache_dma; |
|
}; |
|
|
|
/** |
|
* struct mv_cesa_ahash_req - hash request |
|
* @req: type specific request information |
|
* @cache: cache buffer |
|
* @cache_ptr: write pointer in the cache buffer |
|
* @len: hash total length |
|
* @src_nents: number of entries in the scatterlist |
|
* @last_req: define whether the current operation is the last one |
|
* or not |
|
* @state: hash state |
|
*/ |
|
struct mv_cesa_ahash_req { |
|
struct mv_cesa_req base; |
|
union { |
|
struct mv_cesa_ahash_dma_req dma; |
|
struct mv_cesa_ahash_std_req std; |
|
} req; |
|
struct mv_cesa_op_ctx op_tmpl; |
|
u8 cache[CESA_MAX_HASH_BLOCK_SIZE]; |
|
unsigned int cache_ptr; |
|
u64 len; |
|
int src_nents; |
|
bool last_req; |
|
bool algo_le; |
|
u32 state[8]; |
|
}; |
|
|
|
/* CESA functions */ |
|
|
|
extern struct mv_cesa_dev *cesa_dev; |
|
|
|
|
|
static inline void |
|
mv_cesa_engine_enqueue_complete_request(struct mv_cesa_engine *engine, |
|
struct crypto_async_request *req) |
|
{ |
|
list_add_tail(&req->list, &engine->complete_queue); |
|
} |
|
|
|
static inline struct crypto_async_request * |
|
mv_cesa_engine_dequeue_complete_request(struct mv_cesa_engine *engine) |
|
{ |
|
struct crypto_async_request *req; |
|
|
|
req = list_first_entry_or_null(&engine->complete_queue, |
|
struct crypto_async_request, |
|
list); |
|
if (req) |
|
list_del(&req->list); |
|
|
|
return req; |
|
} |
|
|
|
|
|
static inline enum mv_cesa_req_type |
|
mv_cesa_req_get_type(struct mv_cesa_req *req) |
|
{ |
|
return req->chain.first ? CESA_DMA_REQ : CESA_STD_REQ; |
|
} |
|
|
|
static inline void mv_cesa_update_op_cfg(struct mv_cesa_op_ctx *op, |
|
u32 cfg, u32 mask) |
|
{ |
|
op->desc.config &= cpu_to_le32(~mask); |
|
op->desc.config |= cpu_to_le32(cfg); |
|
} |
|
|
|
static inline u32 mv_cesa_get_op_cfg(const struct mv_cesa_op_ctx *op) |
|
{ |
|
return le32_to_cpu(op->desc.config); |
|
} |
|
|
|
static inline void mv_cesa_set_op_cfg(struct mv_cesa_op_ctx *op, u32 cfg) |
|
{ |
|
op->desc.config = cpu_to_le32(cfg); |
|
} |
|
|
|
static inline void mv_cesa_adjust_op(struct mv_cesa_engine *engine, |
|
struct mv_cesa_op_ctx *op) |
|
{ |
|
u32 offset = engine->sram_dma & CESA_SA_SRAM_MSK; |
|
|
|
op->desc.enc_p = CESA_SA_DESC_CRYPT_DATA(offset); |
|
op->desc.enc_key_p = CESA_SA_DESC_CRYPT_KEY(offset); |
|
op->desc.enc_iv = CESA_SA_DESC_CRYPT_IV(offset); |
|
op->desc.mac_src_p &= ~CESA_SA_DESC_MAC_DATA_MSK; |
|
op->desc.mac_src_p |= CESA_SA_DESC_MAC_DATA(offset); |
|
op->desc.mac_digest &= ~CESA_SA_DESC_MAC_DIGEST_MSK; |
|
op->desc.mac_digest |= CESA_SA_DESC_MAC_DIGEST(offset); |
|
op->desc.mac_iv = CESA_SA_DESC_MAC_IV(offset); |
|
} |
|
|
|
static inline void mv_cesa_set_crypt_op_len(struct mv_cesa_op_ctx *op, int len) |
|
{ |
|
op->desc.enc_len = cpu_to_le32(len); |
|
} |
|
|
|
static inline void mv_cesa_set_mac_op_total_len(struct mv_cesa_op_ctx *op, |
|
int len) |
|
{ |
|
op->desc.mac_src_p &= ~CESA_SA_DESC_MAC_TOTAL_LEN_MSK; |
|
op->desc.mac_src_p |= CESA_SA_DESC_MAC_TOTAL_LEN(len); |
|
} |
|
|
|
static inline void mv_cesa_set_mac_op_frag_len(struct mv_cesa_op_ctx *op, |
|
int len) |
|
{ |
|
op->desc.mac_digest &= ~CESA_SA_DESC_MAC_FRAG_LEN_MSK; |
|
op->desc.mac_digest |= CESA_SA_DESC_MAC_FRAG_LEN(len); |
|
} |
|
|
|
static inline void mv_cesa_set_int_mask(struct mv_cesa_engine *engine, |
|
u32 int_mask) |
|
{ |
|
if (int_mask == engine->int_mask) |
|
return; |
|
|
|
writel_relaxed(int_mask, engine->regs + CESA_SA_INT_MSK); |
|
engine->int_mask = int_mask; |
|
} |
|
|
|
static inline u32 mv_cesa_get_int_mask(struct mv_cesa_engine *engine) |
|
{ |
|
return engine->int_mask; |
|
} |
|
|
|
static inline bool mv_cesa_mac_op_is_first_frag(const struct mv_cesa_op_ctx *op) |
|
{ |
|
return (mv_cesa_get_op_cfg(op) & CESA_SA_DESC_CFG_FRAG_MSK) == |
|
CESA_SA_DESC_CFG_FIRST_FRAG; |
|
} |
|
|
|
int mv_cesa_queue_req(struct crypto_async_request *req, |
|
struct mv_cesa_req *creq); |
|
|
|
struct crypto_async_request * |
|
mv_cesa_dequeue_req_locked(struct mv_cesa_engine *engine, |
|
struct crypto_async_request **backlog); |
|
|
|
static inline struct mv_cesa_engine *mv_cesa_select_engine(int weight) |
|
{ |
|
int i; |
|
u32 min_load = U32_MAX; |
|
struct mv_cesa_engine *selected = NULL; |
|
|
|
for (i = 0; i < cesa_dev->caps->nengines; i++) { |
|
struct mv_cesa_engine *engine = cesa_dev->engines + i; |
|
u32 load = atomic_read(&engine->load); |
|
|
|
if (load < min_load) { |
|
min_load = load; |
|
selected = engine; |
|
} |
|
} |
|
|
|
atomic_add(weight, &selected->load); |
|
|
|
return selected; |
|
} |
|
|
|
/* |
|
* Helper function that indicates whether a crypto request needs to be |
|
* cleaned up or not after being enqueued using mv_cesa_queue_req(). |
|
*/ |
|
static inline int mv_cesa_req_needs_cleanup(struct crypto_async_request *req, |
|
int ret) |
|
{ |
|
/* |
|
* The queue still had some space, the request was queued |
|
* normally, so there's no need to clean it up. |
|
*/ |
|
if (ret == -EINPROGRESS) |
|
return false; |
|
|
|
/* |
|
* The queue had not space left, but since the request is |
|
* flagged with CRYPTO_TFM_REQ_MAY_BACKLOG, it was added to |
|
* the backlog and will be processed later. There's no need to |
|
* clean it up. |
|
*/ |
|
if (ret == -EBUSY) |
|
return false; |
|
|
|
/* Request wasn't queued, we need to clean it up */ |
|
return true; |
|
} |
|
|
|
/* TDMA functions */ |
|
|
|
static inline void mv_cesa_req_dma_iter_init(struct mv_cesa_dma_iter *iter, |
|
unsigned int len) |
|
{ |
|
iter->len = len; |
|
iter->op_len = min(len, CESA_SA_SRAM_PAYLOAD_SIZE); |
|
iter->offset = 0; |
|
} |
|
|
|
static inline void mv_cesa_sg_dma_iter_init(struct mv_cesa_sg_dma_iter *iter, |
|
struct scatterlist *sg, |
|
enum dma_data_direction dir) |
|
{ |
|
iter->op_offset = 0; |
|
iter->offset = 0; |
|
iter->sg = sg; |
|
iter->dir = dir; |
|
} |
|
|
|
static inline unsigned int |
|
mv_cesa_req_dma_iter_transfer_len(struct mv_cesa_dma_iter *iter, |
|
struct mv_cesa_sg_dma_iter *sgiter) |
|
{ |
|
return min(iter->op_len - sgiter->op_offset, |
|
sg_dma_len(sgiter->sg) - sgiter->offset); |
|
} |
|
|
|
bool mv_cesa_req_dma_iter_next_transfer(struct mv_cesa_dma_iter *chain, |
|
struct mv_cesa_sg_dma_iter *sgiter, |
|
unsigned int len); |
|
|
|
static inline bool mv_cesa_req_dma_iter_next_op(struct mv_cesa_dma_iter *iter) |
|
{ |
|
iter->offset += iter->op_len; |
|
iter->op_len = min(iter->len - iter->offset, |
|
CESA_SA_SRAM_PAYLOAD_SIZE); |
|
|
|
return iter->op_len; |
|
} |
|
|
|
void mv_cesa_dma_step(struct mv_cesa_req *dreq); |
|
|
|
static inline int mv_cesa_dma_process(struct mv_cesa_req *dreq, |
|
u32 status) |
|
{ |
|
if (!(status & CESA_SA_INT_ACC0_IDMA_DONE)) |
|
return -EINPROGRESS; |
|
|
|
if (status & CESA_SA_INT_IDMA_OWN_ERR) |
|
return -EINVAL; |
|
|
|
return 0; |
|
} |
|
|
|
void mv_cesa_dma_prepare(struct mv_cesa_req *dreq, |
|
struct mv_cesa_engine *engine); |
|
void mv_cesa_dma_cleanup(struct mv_cesa_req *dreq); |
|
void mv_cesa_tdma_chain(struct mv_cesa_engine *engine, |
|
struct mv_cesa_req *dreq); |
|
int mv_cesa_tdma_process(struct mv_cesa_engine *engine, u32 status); |
|
|
|
|
|
static inline void |
|
mv_cesa_tdma_desc_iter_init(struct mv_cesa_tdma_chain *chain) |
|
{ |
|
memset(chain, 0, sizeof(*chain)); |
|
} |
|
|
|
int mv_cesa_dma_add_result_op(struct mv_cesa_tdma_chain *chain, dma_addr_t src, |
|
u32 size, u32 flags, gfp_t gfp_flags); |
|
|
|
struct mv_cesa_op_ctx *mv_cesa_dma_add_op(struct mv_cesa_tdma_chain *chain, |
|
const struct mv_cesa_op_ctx *op_templ, |
|
bool skip_ctx, |
|
gfp_t flags); |
|
|
|
int mv_cesa_dma_add_data_transfer(struct mv_cesa_tdma_chain *chain, |
|
dma_addr_t dst, dma_addr_t src, u32 size, |
|
u32 flags, gfp_t gfp_flags); |
|
|
|
int mv_cesa_dma_add_dummy_launch(struct mv_cesa_tdma_chain *chain, gfp_t flags); |
|
int mv_cesa_dma_add_dummy_end(struct mv_cesa_tdma_chain *chain, gfp_t flags); |
|
|
|
int mv_cesa_dma_add_op_transfers(struct mv_cesa_tdma_chain *chain, |
|
struct mv_cesa_dma_iter *dma_iter, |
|
struct mv_cesa_sg_dma_iter *sgiter, |
|
gfp_t gfp_flags); |
|
|
|
size_t mv_cesa_sg_copy(struct mv_cesa_engine *engine, |
|
struct scatterlist *sgl, unsigned int nents, |
|
unsigned int sram_off, size_t buflen, off_t skip, |
|
bool to_sram); |
|
|
|
static inline size_t mv_cesa_sg_copy_to_sram(struct mv_cesa_engine *engine, |
|
struct scatterlist *sgl, |
|
unsigned int nents, |
|
unsigned int sram_off, |
|
size_t buflen, off_t skip) |
|
{ |
|
return mv_cesa_sg_copy(engine, sgl, nents, sram_off, buflen, skip, |
|
true); |
|
} |
|
|
|
static inline size_t mv_cesa_sg_copy_from_sram(struct mv_cesa_engine *engine, |
|
struct scatterlist *sgl, |
|
unsigned int nents, |
|
unsigned int sram_off, |
|
size_t buflen, off_t skip) |
|
{ |
|
return mv_cesa_sg_copy(engine, sgl, nents, sram_off, buflen, skip, |
|
false); |
|
} |
|
|
|
/* Algorithm definitions */ |
|
|
|
extern struct ahash_alg mv_md5_alg; |
|
extern struct ahash_alg mv_sha1_alg; |
|
extern struct ahash_alg mv_sha256_alg; |
|
extern struct ahash_alg mv_ahmac_md5_alg; |
|
extern struct ahash_alg mv_ahmac_sha1_alg; |
|
extern struct ahash_alg mv_ahmac_sha256_alg; |
|
|
|
extern struct skcipher_alg mv_cesa_ecb_des_alg; |
|
extern struct skcipher_alg mv_cesa_cbc_des_alg; |
|
extern struct skcipher_alg mv_cesa_ecb_des3_ede_alg; |
|
extern struct skcipher_alg mv_cesa_cbc_des3_ede_alg; |
|
extern struct skcipher_alg mv_cesa_ecb_aes_alg; |
|
extern struct skcipher_alg mv_cesa_cbc_aes_alg; |
|
|
|
#endif /* __MARVELL_CESA_H__ */
|
|
|