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535 lines
13 KiB
535 lines
13 KiB
// SPDX-License-Identifier: GPL-2.0 |
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/* |
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* sl3516-ce-core.c - hardware cryptographic offloader for Storlink SL3516 SoC |
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* |
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* Copyright (C) 2021 Corentin Labbe <[email protected]> |
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* |
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* Core file which registers crypto algorithms supported by the CryptoEngine |
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*/ |
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#include <linux/clk.h> |
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#include <linux/crypto.h> |
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#include <linux/debugfs.h> |
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#include <linux/dev_printk.h> |
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#include <linux/dma-mapping.h> |
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#include <linux/interrupt.h> |
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#include <linux/io.h> |
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#include <linux/irq.h> |
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#include <linux/module.h> |
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#include <linux/of.h> |
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#include <linux/of_device.h> |
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#include <linux/platform_device.h> |
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#include <linux/pm_runtime.h> |
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#include <linux/reset.h> |
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#include <crypto/internal/rng.h> |
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#include <crypto/internal/skcipher.h> |
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#include "sl3516-ce.h" |
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static int sl3516_ce_desc_init(struct sl3516_ce_dev *ce) |
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{ |
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const size_t sz = sizeof(struct descriptor) * MAXDESC; |
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int i; |
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ce->tx = dma_alloc_coherent(ce->dev, sz, &ce->dtx, GFP_KERNEL); |
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if (!ce->tx) |
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return -ENOMEM; |
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ce->rx = dma_alloc_coherent(ce->dev, sz, &ce->drx, GFP_KERNEL); |
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if (!ce->rx) |
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goto err_rx; |
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for (i = 0; i < MAXDESC; i++) { |
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ce->tx[i].frame_ctrl.bits.own = CE_CPU; |
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ce->tx[i].next_desc.next_descriptor = ce->dtx + (i + 1) * sizeof(struct descriptor); |
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} |
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ce->tx[MAXDESC - 1].next_desc.next_descriptor = ce->dtx; |
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for (i = 0; i < MAXDESC; i++) { |
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ce->rx[i].frame_ctrl.bits.own = CE_CPU; |
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ce->rx[i].next_desc.next_descriptor = ce->drx + (i + 1) * sizeof(struct descriptor); |
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} |
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ce->rx[MAXDESC - 1].next_desc.next_descriptor = ce->drx; |
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ce->pctrl = dma_alloc_coherent(ce->dev, sizeof(struct pkt_control_ecb), |
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&ce->dctrl, GFP_KERNEL); |
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if (!ce->pctrl) |
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goto err_pctrl; |
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return 0; |
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err_pctrl: |
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dma_free_coherent(ce->dev, sz, ce->rx, ce->drx); |
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err_rx: |
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dma_free_coherent(ce->dev, sz, ce->tx, ce->dtx); |
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return -ENOMEM; |
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} |
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static void sl3516_ce_free_descs(struct sl3516_ce_dev *ce) |
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{ |
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const size_t sz = sizeof(struct descriptor) * MAXDESC; |
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dma_free_coherent(ce->dev, sz, ce->tx, ce->dtx); |
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dma_free_coherent(ce->dev, sz, ce->rx, ce->drx); |
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dma_free_coherent(ce->dev, sizeof(struct pkt_control_ecb), ce->pctrl, |
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ce->dctrl); |
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} |
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static void start_dma_tx(struct sl3516_ce_dev *ce) |
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{ |
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u32 v; |
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v = TXDMA_CTRL_START | TXDMA_CTRL_CHAIN_MODE | TXDMA_CTRL_CONTINUE | \ |
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TXDMA_CTRL_INT_FAIL | TXDMA_CTRL_INT_PERR | TXDMA_CTRL_BURST_UNK; |
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writel(v, ce->base + IPSEC_TXDMA_CTRL); |
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} |
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static void start_dma_rx(struct sl3516_ce_dev *ce) |
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{ |
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u32 v; |
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v = RXDMA_CTRL_START | RXDMA_CTRL_CHAIN_MODE | RXDMA_CTRL_CONTINUE | \ |
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RXDMA_CTRL_BURST_UNK | RXDMA_CTRL_INT_FINISH | \ |
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RXDMA_CTRL_INT_FAIL | RXDMA_CTRL_INT_PERR | \ |
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RXDMA_CTRL_INT_EOD | RXDMA_CTRL_INT_EOF; |
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writel(v, ce->base + IPSEC_RXDMA_CTRL); |
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} |
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static struct descriptor *get_desc_tx(struct sl3516_ce_dev *ce) |
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{ |
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struct descriptor *dd; |
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dd = &ce->tx[ce->ctx]; |
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ce->ctx++; |
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if (ce->ctx >= MAXDESC) |
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ce->ctx = 0; |
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return dd; |
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} |
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static struct descriptor *get_desc_rx(struct sl3516_ce_dev *ce) |
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{ |
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struct descriptor *rdd; |
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rdd = &ce->rx[ce->crx]; |
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ce->crx++; |
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if (ce->crx >= MAXDESC) |
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ce->crx = 0; |
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return rdd; |
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} |
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int sl3516_ce_run_task(struct sl3516_ce_dev *ce, struct sl3516_ce_cipher_req_ctx *rctx, |
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const char *name) |
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{ |
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struct descriptor *dd, *rdd = NULL; |
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u32 v; |
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int i, err = 0; |
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ce->stat_req++; |
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reinit_completion(&ce->complete); |
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ce->status = 0; |
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for (i = 0; i < rctx->nr_sgd; i++) { |
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dev_dbg(ce->dev, "%s handle DST SG %d/%d len=%d\n", __func__, |
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i, rctx->nr_sgd, rctx->t_dst[i].len); |
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rdd = get_desc_rx(ce); |
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rdd->buf_adr = rctx->t_dst[i].addr; |
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rdd->frame_ctrl.bits.buffer_size = rctx->t_dst[i].len; |
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rdd->frame_ctrl.bits.own = CE_DMA; |
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} |
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rdd->next_desc.bits.eofie = 1; |
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for (i = 0; i < rctx->nr_sgs; i++) { |
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dev_dbg(ce->dev, "%s handle SRC SG %d/%d len=%d\n", __func__, |
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i, rctx->nr_sgs, rctx->t_src[i].len); |
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rctx->h->algorithm_len = rctx->t_src[i].len; |
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dd = get_desc_tx(ce); |
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dd->frame_ctrl.raw = 0; |
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dd->flag_status.raw = 0; |
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dd->frame_ctrl.bits.buffer_size = rctx->pctrllen; |
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dd->buf_adr = ce->dctrl; |
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dd->flag_status.tx_flag.tqflag = rctx->tqflag; |
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dd->next_desc.bits.eofie = 0; |
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dd->next_desc.bits.dec = 0; |
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dd->next_desc.bits.sof_eof = DESC_FIRST | DESC_LAST; |
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dd->frame_ctrl.bits.own = CE_DMA; |
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dd = get_desc_tx(ce); |
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dd->frame_ctrl.raw = 0; |
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dd->flag_status.raw = 0; |
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dd->frame_ctrl.bits.buffer_size = rctx->t_src[i].len; |
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dd->buf_adr = rctx->t_src[i].addr; |
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dd->flag_status.tx_flag.tqflag = 0; |
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dd->next_desc.bits.eofie = 0; |
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dd->next_desc.bits.dec = 0; |
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dd->next_desc.bits.sof_eof = DESC_FIRST | DESC_LAST; |
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dd->frame_ctrl.bits.own = CE_DMA; |
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start_dma_tx(ce); |
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start_dma_rx(ce); |
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} |
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wait_for_completion_interruptible_timeout(&ce->complete, |
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msecs_to_jiffies(5000)); |
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if (ce->status == 0) { |
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dev_err(ce->dev, "DMA timeout for %s\n", name); |
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err = -EFAULT; |
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} |
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v = readl(ce->base + IPSEC_STATUS_REG); |
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if (v & 0xFFF) { |
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dev_err(ce->dev, "IPSEC_STATUS_REG %x\n", v); |
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err = -EFAULT; |
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} |
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return err; |
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} |
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static irqreturn_t ce_irq_handler(int irq, void *data) |
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{ |
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struct sl3516_ce_dev *ce = (struct sl3516_ce_dev *)data; |
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u32 v; |
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ce->stat_irq++; |
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v = readl(ce->base + IPSEC_DMA_STATUS); |
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writel(v, ce->base + IPSEC_DMA_STATUS); |
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if (v & DMA_STATUS_TS_DERR) |
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dev_err(ce->dev, "AHB bus Error While Tx !!!\n"); |
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if (v & DMA_STATUS_TS_PERR) |
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dev_err(ce->dev, "Tx Descriptor Protocol Error !!!\n"); |
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if (v & DMA_STATUS_RS_DERR) |
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dev_err(ce->dev, "AHB bus Error While Rx !!!\n"); |
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if (v & DMA_STATUS_RS_PERR) |
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dev_err(ce->dev, "Rx Descriptor Protocol Error !!!\n"); |
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if (v & DMA_STATUS_TS_EOFI) |
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ce->stat_irq_tx++; |
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if (v & DMA_STATUS_RS_EOFI) { |
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ce->status = 1; |
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complete(&ce->complete); |
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ce->stat_irq_rx++; |
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return IRQ_HANDLED; |
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} |
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return IRQ_HANDLED; |
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} |
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static struct sl3516_ce_alg_template ce_algs[] = { |
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{ |
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.type = CRYPTO_ALG_TYPE_SKCIPHER, |
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.mode = ECB_AES, |
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.alg.skcipher = { |
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.base = { |
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.cra_name = "ecb(aes)", |
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.cra_driver_name = "ecb-aes-sl3516", |
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.cra_priority = 400, |
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.cra_blocksize = AES_BLOCK_SIZE, |
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.cra_flags = CRYPTO_ALG_TYPE_SKCIPHER | |
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CRYPTO_ALG_ASYNC | CRYPTO_ALG_NEED_FALLBACK, |
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.cra_ctxsize = sizeof(struct sl3516_ce_cipher_tfm_ctx), |
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.cra_module = THIS_MODULE, |
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.cra_alignmask = 0xf, |
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.cra_init = sl3516_ce_cipher_init, |
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.cra_exit = sl3516_ce_cipher_exit, |
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}, |
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.min_keysize = AES_MIN_KEY_SIZE, |
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.max_keysize = AES_MAX_KEY_SIZE, |
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.setkey = sl3516_ce_aes_setkey, |
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.encrypt = sl3516_ce_skencrypt, |
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.decrypt = sl3516_ce_skdecrypt, |
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} |
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}, |
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}; |
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#ifdef CONFIG_CRYPTO_DEV_SL3516_DEBUG |
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static int sl3516_ce_debugfs_show(struct seq_file *seq, void *v) |
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{ |
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struct sl3516_ce_dev *ce = seq->private; |
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unsigned int i; |
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seq_printf(seq, "HWRNG %lu %lu\n", |
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ce->hwrng_stat_req, ce->hwrng_stat_bytes); |
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seq_printf(seq, "IRQ %lu\n", ce->stat_irq); |
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seq_printf(seq, "IRQ TX %lu\n", ce->stat_irq_tx); |
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seq_printf(seq, "IRQ RX %lu\n", ce->stat_irq_rx); |
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seq_printf(seq, "nreq %lu\n", ce->stat_req); |
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seq_printf(seq, "fallback SG count TX %lu\n", ce->fallback_sg_count_tx); |
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seq_printf(seq, "fallback SG count RX %lu\n", ce->fallback_sg_count_rx); |
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seq_printf(seq, "fallback modulo16 %lu\n", ce->fallback_mod16); |
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seq_printf(seq, "fallback align16 %lu\n", ce->fallback_align16); |
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seq_printf(seq, "fallback not same len %lu\n", ce->fallback_not_same_len); |
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for (i = 0; i < ARRAY_SIZE(ce_algs); i++) { |
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if (!ce_algs[i].ce) |
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continue; |
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switch (ce_algs[i].type) { |
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case CRYPTO_ALG_TYPE_SKCIPHER: |
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seq_printf(seq, "%s %s reqs=%lu fallback=%lu\n", |
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ce_algs[i].alg.skcipher.base.cra_driver_name, |
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ce_algs[i].alg.skcipher.base.cra_name, |
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ce_algs[i].stat_req, ce_algs[i].stat_fb); |
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break; |
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} |
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} |
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return 0; |
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} |
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DEFINE_SHOW_ATTRIBUTE(sl3516_ce_debugfs); |
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#endif |
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static int sl3516_ce_register_algs(struct sl3516_ce_dev *ce) |
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{ |
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int err; |
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unsigned int i; |
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for (i = 0; i < ARRAY_SIZE(ce_algs); i++) { |
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ce_algs[i].ce = ce; |
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switch (ce_algs[i].type) { |
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case CRYPTO_ALG_TYPE_SKCIPHER: |
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dev_info(ce->dev, "DEBUG: Register %s\n", |
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ce_algs[i].alg.skcipher.base.cra_name); |
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err = crypto_register_skcipher(&ce_algs[i].alg.skcipher); |
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if (err) { |
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dev_err(ce->dev, "Fail to register %s\n", |
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ce_algs[i].alg.skcipher.base.cra_name); |
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ce_algs[i].ce = NULL; |
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return err; |
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} |
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break; |
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default: |
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ce_algs[i].ce = NULL; |
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dev_err(ce->dev, "ERROR: tried to register an unknown algo\n"); |
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} |
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} |
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return 0; |
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} |
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static void sl3516_ce_unregister_algs(struct sl3516_ce_dev *ce) |
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{ |
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unsigned int i; |
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for (i = 0; i < ARRAY_SIZE(ce_algs); i++) { |
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if (!ce_algs[i].ce) |
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continue; |
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switch (ce_algs[i].type) { |
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case CRYPTO_ALG_TYPE_SKCIPHER: |
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dev_info(ce->dev, "Unregister %d %s\n", i, |
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ce_algs[i].alg.skcipher.base.cra_name); |
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crypto_unregister_skcipher(&ce_algs[i].alg.skcipher); |
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break; |
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} |
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} |
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} |
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static void sl3516_ce_start(struct sl3516_ce_dev *ce) |
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{ |
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ce->ctx = 0; |
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ce->crx = 0; |
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writel(ce->dtx, ce->base + IPSEC_TXDMA_CURR_DESC); |
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writel(ce->drx, ce->base + IPSEC_RXDMA_CURR_DESC); |
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writel(0, ce->base + IPSEC_DMA_STATUS); |
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} |
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/* |
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* Power management strategy: The device is suspended unless a TFM exists for |
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* one of the algorithms proposed by this driver. |
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*/ |
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static int sl3516_ce_pm_suspend(struct device *dev) |
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{ |
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struct sl3516_ce_dev *ce = dev_get_drvdata(dev); |
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reset_control_assert(ce->reset); |
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clk_disable_unprepare(ce->clks); |
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return 0; |
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} |
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static int sl3516_ce_pm_resume(struct device *dev) |
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{ |
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struct sl3516_ce_dev *ce = dev_get_drvdata(dev); |
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int err; |
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err = clk_prepare_enable(ce->clks); |
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if (err) { |
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dev_err(ce->dev, "Cannot prepare_enable\n"); |
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goto error; |
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} |
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err = reset_control_deassert(ce->reset); |
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if (err) { |
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dev_err(ce->dev, "Cannot deassert reset control\n"); |
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goto error; |
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} |
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sl3516_ce_start(ce); |
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return 0; |
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error: |
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sl3516_ce_pm_suspend(dev); |
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return err; |
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} |
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static const struct dev_pm_ops sl3516_ce_pm_ops = { |
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SET_RUNTIME_PM_OPS(sl3516_ce_pm_suspend, sl3516_ce_pm_resume, NULL) |
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}; |
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static int sl3516_ce_pm_init(struct sl3516_ce_dev *ce) |
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{ |
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int err; |
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pm_runtime_use_autosuspend(ce->dev); |
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pm_runtime_set_autosuspend_delay(ce->dev, 2000); |
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err = pm_runtime_set_suspended(ce->dev); |
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if (err) |
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return err; |
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pm_runtime_enable(ce->dev); |
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return err; |
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} |
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static void sl3516_ce_pm_exit(struct sl3516_ce_dev *ce) |
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{ |
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pm_runtime_disable(ce->dev); |
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} |
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static int sl3516_ce_probe(struct platform_device *pdev) |
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{ |
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struct sl3516_ce_dev *ce; |
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int err, irq; |
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u32 v; |
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ce = devm_kzalloc(&pdev->dev, sizeof(*ce), GFP_KERNEL); |
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if (!ce) |
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return -ENOMEM; |
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ce->dev = &pdev->dev; |
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platform_set_drvdata(pdev, ce); |
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ce->base = devm_platform_ioremap_resource(pdev, 0); |
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if (IS_ERR(ce->base)) |
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return PTR_ERR(ce->base); |
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irq = platform_get_irq(pdev, 0); |
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if (irq < 0) |
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return irq; |
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err = devm_request_irq(&pdev->dev, irq, ce_irq_handler, 0, "crypto", ce); |
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if (err) { |
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dev_err(ce->dev, "Cannot request Crypto Engine IRQ (err=%d)\n", err); |
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return err; |
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} |
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ce->reset = devm_reset_control_get(&pdev->dev, NULL); |
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if (IS_ERR(ce->reset)) |
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return dev_err_probe(&pdev->dev, PTR_ERR(ce->reset), |
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"No reset control found\n"); |
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ce->clks = devm_clk_get(ce->dev, NULL); |
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if (IS_ERR(ce->clks)) { |
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err = PTR_ERR(ce->clks); |
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dev_err(ce->dev, "Cannot get clock err=%d\n", err); |
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return err; |
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} |
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err = sl3516_ce_desc_init(ce); |
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if (err) |
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return err; |
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err = sl3516_ce_pm_init(ce); |
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if (err) |
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goto error_pm; |
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init_completion(&ce->complete); |
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ce->engine = crypto_engine_alloc_init(ce->dev, true); |
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if (!ce->engine) { |
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dev_err(ce->dev, "Cannot allocate engine\n"); |
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err = -ENOMEM; |
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goto error_engine; |
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} |
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err = crypto_engine_start(ce->engine); |
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if (err) { |
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dev_err(ce->dev, "Cannot start engine\n"); |
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goto error_engine; |
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} |
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err = sl3516_ce_register_algs(ce); |
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if (err) |
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goto error_alg; |
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err = sl3516_ce_rng_register(ce); |
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if (err) |
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goto error_rng; |
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err = pm_runtime_resume_and_get(ce->dev); |
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if (err < 0) |
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goto error_pmuse; |
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v = readl(ce->base + IPSEC_ID); |
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dev_info(ce->dev, "SL3516 dev %lx rev %lx\n", |
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v & GENMASK(31, 4), |
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v & GENMASK(3, 0)); |
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v = readl(ce->base + IPSEC_DMA_DEVICE_ID); |
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dev_info(ce->dev, "SL3516 DMA dev %lx rev %lx\n", |
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v & GENMASK(15, 4), |
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v & GENMASK(3, 0)); |
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pm_runtime_put_sync(ce->dev); |
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#ifdef CONFIG_CRYPTO_DEV_SL3516_DEBUG |
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/* Ignore error of debugfs */ |
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ce->dbgfs_dir = debugfs_create_dir("sl3516", NULL); |
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ce->dbgfs_stats = debugfs_create_file("stats", 0444, |
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ce->dbgfs_dir, ce, |
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&sl3516_ce_debugfs_fops); |
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#endif |
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return 0; |
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error_pmuse: |
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sl3516_ce_rng_unregister(ce); |
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error_rng: |
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sl3516_ce_unregister_algs(ce); |
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error_alg: |
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crypto_engine_exit(ce->engine); |
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error_engine: |
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sl3516_ce_pm_exit(ce); |
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error_pm: |
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sl3516_ce_free_descs(ce); |
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return err; |
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} |
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static int sl3516_ce_remove(struct platform_device *pdev) |
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{ |
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struct sl3516_ce_dev *ce = platform_get_drvdata(pdev); |
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sl3516_ce_rng_unregister(ce); |
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sl3516_ce_unregister_algs(ce); |
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crypto_engine_exit(ce->engine); |
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sl3516_ce_pm_exit(ce); |
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sl3516_ce_free_descs(ce); |
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#ifdef CONFIG_CRYPTO_DEV_SL3516_DEBUG |
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debugfs_remove_recursive(ce->dbgfs_dir); |
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#endif |
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return 0; |
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} |
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static const struct of_device_id sl3516_ce_crypto_of_match_table[] = { |
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{ .compatible = "cortina,sl3516-crypto"}, |
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{} |
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}; |
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MODULE_DEVICE_TABLE(of, sl3516_ce_crypto_of_match_table); |
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|
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static struct platform_driver sl3516_ce_driver = { |
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.probe = sl3516_ce_probe, |
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.remove = sl3516_ce_remove, |
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.driver = { |
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.name = "sl3516-crypto", |
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.pm = &sl3516_ce_pm_ops, |
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.of_match_table = sl3516_ce_crypto_of_match_table, |
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}, |
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}; |
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|
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module_platform_driver(sl3516_ce_driver); |
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|
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MODULE_DESCRIPTION("SL3516 cryptographic offloader"); |
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MODULE_LICENSE("GPL"); |
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MODULE_AUTHOR("Corentin Labbe <[email protected]>");
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|