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286 lines
6.9 KiB
286 lines
6.9 KiB
// SPDX-License-Identifier: GPL-2.0-only |
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/* |
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* Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved |
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*/ |
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#include <linux/cpufreq.h> |
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#include <linux/dma-mapping.h> |
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#include <linux/module.h> |
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#include <linux/of.h> |
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#include <linux/platform_device.h> |
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#include <soc/tegra/bpmp.h> |
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#include <soc/tegra/bpmp-abi.h> |
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#define TEGRA186_NUM_CLUSTERS 2 |
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#define EDVD_OFFSET_A57(core) ((SZ_64K * 6) + (0x20 + (core) * 0x4)) |
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#define EDVD_OFFSET_DENVER(core) ((SZ_64K * 7) + (0x20 + (core) * 0x4)) |
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#define EDVD_CORE_VOLT_FREQ_F_SHIFT 0 |
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#define EDVD_CORE_VOLT_FREQ_F_MASK 0xffff |
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#define EDVD_CORE_VOLT_FREQ_V_SHIFT 16 |
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struct tegra186_cpufreq_cpu { |
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unsigned int bpmp_cluster_id; |
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unsigned int edvd_offset; |
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}; |
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static const struct tegra186_cpufreq_cpu tegra186_cpus[] = { |
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/* CPU0 - A57 Cluster */ |
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{ |
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.bpmp_cluster_id = 1, |
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.edvd_offset = EDVD_OFFSET_A57(0) |
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}, |
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/* CPU1 - Denver Cluster */ |
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{ |
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.bpmp_cluster_id = 0, |
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.edvd_offset = EDVD_OFFSET_DENVER(0) |
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}, |
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/* CPU2 - Denver Cluster */ |
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{ |
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.bpmp_cluster_id = 0, |
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.edvd_offset = EDVD_OFFSET_DENVER(1) |
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}, |
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/* CPU3 - A57 Cluster */ |
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{ |
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.bpmp_cluster_id = 1, |
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.edvd_offset = EDVD_OFFSET_A57(1) |
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}, |
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/* CPU4 - A57 Cluster */ |
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{ |
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.bpmp_cluster_id = 1, |
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.edvd_offset = EDVD_OFFSET_A57(2) |
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}, |
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/* CPU5 - A57 Cluster */ |
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{ |
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.bpmp_cluster_id = 1, |
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.edvd_offset = EDVD_OFFSET_A57(3) |
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}, |
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}; |
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struct tegra186_cpufreq_cluster { |
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struct cpufreq_frequency_table *table; |
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u32 ref_clk_khz; |
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u32 div; |
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}; |
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struct tegra186_cpufreq_data { |
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void __iomem *regs; |
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struct tegra186_cpufreq_cluster *clusters; |
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const struct tegra186_cpufreq_cpu *cpus; |
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}; |
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static int tegra186_cpufreq_init(struct cpufreq_policy *policy) |
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{ |
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struct tegra186_cpufreq_data *data = cpufreq_get_driver_data(); |
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unsigned int cluster = data->cpus[policy->cpu].bpmp_cluster_id; |
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policy->freq_table = data->clusters[cluster].table; |
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policy->cpuinfo.transition_latency = 300 * 1000; |
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policy->driver_data = NULL; |
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return 0; |
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} |
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static int tegra186_cpufreq_set_target(struct cpufreq_policy *policy, |
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unsigned int index) |
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{ |
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struct tegra186_cpufreq_data *data = cpufreq_get_driver_data(); |
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struct cpufreq_frequency_table *tbl = policy->freq_table + index; |
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unsigned int edvd_offset = data->cpus[policy->cpu].edvd_offset; |
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u32 edvd_val = tbl->driver_data; |
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writel(edvd_val, data->regs + edvd_offset); |
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return 0; |
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} |
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static unsigned int tegra186_cpufreq_get(unsigned int cpu) |
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{ |
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struct tegra186_cpufreq_data *data = cpufreq_get_driver_data(); |
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struct tegra186_cpufreq_cluster *cluster; |
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struct cpufreq_policy *policy; |
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unsigned int edvd_offset, cluster_id; |
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u32 ndiv; |
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policy = cpufreq_cpu_get(cpu); |
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if (!policy) |
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return 0; |
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edvd_offset = data->cpus[policy->cpu].edvd_offset; |
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ndiv = readl(data->regs + edvd_offset) & EDVD_CORE_VOLT_FREQ_F_MASK; |
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cluster_id = data->cpus[policy->cpu].bpmp_cluster_id; |
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cluster = &data->clusters[cluster_id]; |
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cpufreq_cpu_put(policy); |
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return (cluster->ref_clk_khz * ndiv) / cluster->div; |
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} |
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static struct cpufreq_driver tegra186_cpufreq_driver = { |
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.name = "tegra186", |
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.flags = CPUFREQ_HAVE_GOVERNOR_PER_POLICY | |
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CPUFREQ_NEED_INITIAL_FREQ_CHECK, |
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.get = tegra186_cpufreq_get, |
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.verify = cpufreq_generic_frequency_table_verify, |
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.target_index = tegra186_cpufreq_set_target, |
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.init = tegra186_cpufreq_init, |
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.attr = cpufreq_generic_attr, |
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}; |
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static struct cpufreq_frequency_table *init_vhint_table( |
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struct platform_device *pdev, struct tegra_bpmp *bpmp, |
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struct tegra186_cpufreq_cluster *cluster, unsigned int cluster_id) |
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{ |
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struct cpufreq_frequency_table *table; |
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struct mrq_cpu_vhint_request req; |
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struct tegra_bpmp_message msg; |
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struct cpu_vhint_data *data; |
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int err, i, j, num_rates = 0; |
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dma_addr_t phys; |
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void *virt; |
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virt = dma_alloc_coherent(bpmp->dev, sizeof(*data), &phys, |
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GFP_KERNEL); |
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if (!virt) |
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return ERR_PTR(-ENOMEM); |
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data = (struct cpu_vhint_data *)virt; |
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memset(&req, 0, sizeof(req)); |
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req.addr = phys; |
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req.cluster_id = cluster_id; |
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memset(&msg, 0, sizeof(msg)); |
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msg.mrq = MRQ_CPU_VHINT; |
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msg.tx.data = &req; |
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msg.tx.size = sizeof(req); |
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err = tegra_bpmp_transfer(bpmp, &msg); |
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if (err) { |
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table = ERR_PTR(err); |
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goto free; |
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} |
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for (i = data->vfloor; i <= data->vceil; i++) { |
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u16 ndiv = data->ndiv[i]; |
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if (ndiv < data->ndiv_min || ndiv > data->ndiv_max) |
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continue; |
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/* Only store lowest voltage index for each rate */ |
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if (i > 0 && ndiv == data->ndiv[i - 1]) |
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continue; |
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num_rates++; |
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} |
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table = devm_kcalloc(&pdev->dev, num_rates + 1, sizeof(*table), |
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GFP_KERNEL); |
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if (!table) { |
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table = ERR_PTR(-ENOMEM); |
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goto free; |
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} |
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cluster->ref_clk_khz = data->ref_clk_hz / 1000; |
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cluster->div = data->pdiv * data->mdiv; |
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for (i = data->vfloor, j = 0; i <= data->vceil; i++) { |
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struct cpufreq_frequency_table *point; |
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u16 ndiv = data->ndiv[i]; |
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u32 edvd_val = 0; |
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if (ndiv < data->ndiv_min || ndiv > data->ndiv_max) |
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continue; |
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/* Only store lowest voltage index for each rate */ |
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if (i > 0 && ndiv == data->ndiv[i - 1]) |
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continue; |
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edvd_val |= i << EDVD_CORE_VOLT_FREQ_V_SHIFT; |
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edvd_val |= ndiv << EDVD_CORE_VOLT_FREQ_F_SHIFT; |
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point = &table[j++]; |
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point->driver_data = edvd_val; |
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point->frequency = (cluster->ref_clk_khz * ndiv) / cluster->div; |
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} |
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table[j].frequency = CPUFREQ_TABLE_END; |
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free: |
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dma_free_coherent(bpmp->dev, sizeof(*data), virt, phys); |
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return table; |
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} |
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static int tegra186_cpufreq_probe(struct platform_device *pdev) |
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{ |
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struct tegra186_cpufreq_data *data; |
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struct tegra_bpmp *bpmp; |
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unsigned int i = 0, err; |
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data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL); |
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if (!data) |
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return -ENOMEM; |
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data->clusters = devm_kcalloc(&pdev->dev, TEGRA186_NUM_CLUSTERS, |
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sizeof(*data->clusters), GFP_KERNEL); |
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if (!data->clusters) |
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return -ENOMEM; |
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data->cpus = tegra186_cpus; |
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bpmp = tegra_bpmp_get(&pdev->dev); |
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if (IS_ERR(bpmp)) |
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return PTR_ERR(bpmp); |
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data->regs = devm_platform_ioremap_resource(pdev, 0); |
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if (IS_ERR(data->regs)) { |
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err = PTR_ERR(data->regs); |
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goto put_bpmp; |
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} |
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for (i = 0; i < TEGRA186_NUM_CLUSTERS; i++) { |
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struct tegra186_cpufreq_cluster *cluster = &data->clusters[i]; |
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cluster->table = init_vhint_table(pdev, bpmp, cluster, i); |
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if (IS_ERR(cluster->table)) { |
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err = PTR_ERR(cluster->table); |
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goto put_bpmp; |
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} |
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} |
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tegra186_cpufreq_driver.driver_data = data; |
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err = cpufreq_register_driver(&tegra186_cpufreq_driver); |
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put_bpmp: |
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tegra_bpmp_put(bpmp); |
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return err; |
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} |
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static int tegra186_cpufreq_remove(struct platform_device *pdev) |
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{ |
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cpufreq_unregister_driver(&tegra186_cpufreq_driver); |
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return 0; |
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} |
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static const struct of_device_id tegra186_cpufreq_of_match[] = { |
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{ .compatible = "nvidia,tegra186-ccplex-cluster", }, |
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{ } |
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}; |
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MODULE_DEVICE_TABLE(of, tegra186_cpufreq_of_match); |
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static struct platform_driver tegra186_cpufreq_platform_driver = { |
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.driver = { |
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.name = "tegra186-cpufreq", |
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.of_match_table = tegra186_cpufreq_of_match, |
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}, |
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.probe = tegra186_cpufreq_probe, |
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.remove = tegra186_cpufreq_remove, |
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}; |
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module_platform_driver(tegra186_cpufreq_platform_driver); |
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MODULE_AUTHOR("Mikko Perttunen <[email protected]>"); |
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MODULE_DESCRIPTION("NVIDIA Tegra186 cpufreq driver"); |
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MODULE_LICENSE("GPL v2");
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