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436 lines
11 KiB
436 lines
11 KiB
// SPDX-License-Identifier: GPL-2.0-only |
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/* |
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* Copyright (C) 2019 David Lechner <[email protected]> |
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* |
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* Counter driver for Texas Instruments Enhanced Quadrature Encoder Pulse (eQEP) |
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*/ |
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#include <linux/bitops.h> |
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#include <linux/counter.h> |
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#include <linux/kernel.h> |
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#include <linux/mod_devicetable.h> |
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#include <linux/module.h> |
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#include <linux/platform_device.h> |
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#include <linux/pm_runtime.h> |
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#include <linux/regmap.h> |
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/* 32-bit registers */ |
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#define QPOSCNT 0x0 |
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#define QPOSINIT 0x4 |
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#define QPOSMAX 0x8 |
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#define QPOSCMP 0xc |
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#define QPOSILAT 0x10 |
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#define QPOSSLAT 0x14 |
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#define QPOSLAT 0x18 |
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#define QUTMR 0x1c |
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#define QUPRD 0x20 |
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/* 16-bit registers */ |
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#define QWDTMR 0x0 /* 0x24 */ |
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#define QWDPRD 0x2 /* 0x26 */ |
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#define QDECCTL 0x4 /* 0x28 */ |
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#define QEPCTL 0x6 /* 0x2a */ |
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#define QCAPCTL 0x8 /* 0x2c */ |
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#define QPOSCTL 0xa /* 0x2e */ |
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#define QEINT 0xc /* 0x30 */ |
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#define QFLG 0xe /* 0x32 */ |
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#define QCLR 0x10 /* 0x34 */ |
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#define QFRC 0x12 /* 0x36 */ |
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#define QEPSTS 0x14 /* 0x38 */ |
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#define QCTMR 0x16 /* 0x3a */ |
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#define QCPRD 0x18 /* 0x3c */ |
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#define QCTMRLAT 0x1a /* 0x3e */ |
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#define QCPRDLAT 0x1c /* 0x40 */ |
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#define QDECCTL_QSRC_SHIFT 14 |
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#define QDECCTL_QSRC GENMASK(15, 14) |
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#define QDECCTL_SOEN BIT(13) |
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#define QDECCTL_SPSEL BIT(12) |
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#define QDECCTL_XCR BIT(11) |
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#define QDECCTL_SWAP BIT(10) |
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#define QDECCTL_IGATE BIT(9) |
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#define QDECCTL_QAP BIT(8) |
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#define QDECCTL_QBP BIT(7) |
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#define QDECCTL_QIP BIT(6) |
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#define QDECCTL_QSP BIT(5) |
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#define QEPCTL_FREE_SOFT GENMASK(15, 14) |
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#define QEPCTL_PCRM GENMASK(13, 12) |
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#define QEPCTL_SEI GENMASK(11, 10) |
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#define QEPCTL_IEI GENMASK(9, 8) |
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#define QEPCTL_SWI BIT(7) |
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#define QEPCTL_SEL BIT(6) |
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#define QEPCTL_IEL GENMASK(5, 4) |
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#define QEPCTL_PHEN BIT(3) |
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#define QEPCTL_QCLM BIT(2) |
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#define QEPCTL_UTE BIT(1) |
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#define QEPCTL_WDE BIT(0) |
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/* EQEP Inputs */ |
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enum { |
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TI_EQEP_SIGNAL_QEPA, /* QEPA/XCLK */ |
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TI_EQEP_SIGNAL_QEPB, /* QEPB/XDIR */ |
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}; |
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/* Position Counter Input Modes */ |
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enum { |
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TI_EQEP_COUNT_FUNC_QUAD_COUNT, |
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TI_EQEP_COUNT_FUNC_DIR_COUNT, |
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TI_EQEP_COUNT_FUNC_UP_COUNT, |
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TI_EQEP_COUNT_FUNC_DOWN_COUNT, |
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}; |
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enum { |
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TI_EQEP_SYNAPSE_ACTION_BOTH_EDGES, |
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TI_EQEP_SYNAPSE_ACTION_RISING_EDGE, |
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TI_EQEP_SYNAPSE_ACTION_NONE, |
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}; |
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struct ti_eqep_cnt { |
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struct counter_device counter; |
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struct regmap *regmap32; |
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struct regmap *regmap16; |
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}; |
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static int ti_eqep_count_read(struct counter_device *counter, |
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struct counter_count *count, unsigned long *val) |
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{ |
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struct ti_eqep_cnt *priv = counter->priv; |
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u32 cnt; |
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regmap_read(priv->regmap32, QPOSCNT, &cnt); |
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*val = cnt; |
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return 0; |
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} |
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static int ti_eqep_count_write(struct counter_device *counter, |
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struct counter_count *count, unsigned long val) |
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{ |
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struct ti_eqep_cnt *priv = counter->priv; |
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u32 max; |
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regmap_read(priv->regmap32, QPOSMAX, &max); |
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if (val > max) |
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return -EINVAL; |
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return regmap_write(priv->regmap32, QPOSCNT, val); |
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} |
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static int ti_eqep_function_get(struct counter_device *counter, |
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struct counter_count *count, size_t *function) |
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{ |
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struct ti_eqep_cnt *priv = counter->priv; |
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u32 qdecctl; |
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regmap_read(priv->regmap16, QDECCTL, &qdecctl); |
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*function = (qdecctl & QDECCTL_QSRC) >> QDECCTL_QSRC_SHIFT; |
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return 0; |
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} |
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static int ti_eqep_function_set(struct counter_device *counter, |
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struct counter_count *count, size_t function) |
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{ |
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struct ti_eqep_cnt *priv = counter->priv; |
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return regmap_write_bits(priv->regmap16, QDECCTL, QDECCTL_QSRC, |
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function << QDECCTL_QSRC_SHIFT); |
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} |
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static int ti_eqep_action_get(struct counter_device *counter, |
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struct counter_count *count, |
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struct counter_synapse *synapse, size_t *action) |
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{ |
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struct ti_eqep_cnt *priv = counter->priv; |
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size_t function; |
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u32 qdecctl; |
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int err; |
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err = ti_eqep_function_get(counter, count, &function); |
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if (err) |
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return err; |
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switch (function) { |
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case TI_EQEP_COUNT_FUNC_QUAD_COUNT: |
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/* In quadrature mode, the rising and falling edge of both |
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* QEPA and QEPB trigger QCLK. |
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*/ |
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*action = TI_EQEP_SYNAPSE_ACTION_BOTH_EDGES; |
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return 0; |
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case TI_EQEP_COUNT_FUNC_DIR_COUNT: |
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/* In direction-count mode only rising edge of QEPA is counted |
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* and QEPB gives direction. |
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*/ |
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switch (synapse->signal->id) { |
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case TI_EQEP_SIGNAL_QEPA: |
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*action = TI_EQEP_SYNAPSE_ACTION_RISING_EDGE; |
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return 0; |
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case TI_EQEP_SIGNAL_QEPB: |
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*action = TI_EQEP_SYNAPSE_ACTION_NONE; |
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return 0; |
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default: |
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/* should never reach this path */ |
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return -EINVAL; |
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} |
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case TI_EQEP_COUNT_FUNC_UP_COUNT: |
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case TI_EQEP_COUNT_FUNC_DOWN_COUNT: |
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/* In up/down-count modes only QEPA is counted and QEPB is not |
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* used. |
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*/ |
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switch (synapse->signal->id) { |
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case TI_EQEP_SIGNAL_QEPA: |
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err = regmap_read(priv->regmap16, QDECCTL, &qdecctl); |
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if (err) |
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return err; |
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if (qdecctl & QDECCTL_XCR) |
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*action = TI_EQEP_SYNAPSE_ACTION_BOTH_EDGES; |
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else |
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*action = TI_EQEP_SYNAPSE_ACTION_RISING_EDGE; |
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return 0; |
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case TI_EQEP_SIGNAL_QEPB: |
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*action = TI_EQEP_SYNAPSE_ACTION_NONE; |
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return 0; |
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default: |
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/* should never reach this path */ |
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return -EINVAL; |
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} |
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default: |
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/* should never reach this path */ |
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return -EINVAL; |
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} |
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} |
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static const struct counter_ops ti_eqep_counter_ops = { |
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.count_read = ti_eqep_count_read, |
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.count_write = ti_eqep_count_write, |
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.function_get = ti_eqep_function_get, |
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.function_set = ti_eqep_function_set, |
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.action_get = ti_eqep_action_get, |
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}; |
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static ssize_t ti_eqep_position_ceiling_read(struct counter_device *counter, |
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struct counter_count *count, |
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void *ext_priv, char *buf) |
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{ |
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struct ti_eqep_cnt *priv = counter->priv; |
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u32 qposmax; |
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regmap_read(priv->regmap32, QPOSMAX, &qposmax); |
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return sprintf(buf, "%u\n", qposmax); |
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} |
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static ssize_t ti_eqep_position_ceiling_write(struct counter_device *counter, |
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struct counter_count *count, |
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void *ext_priv, const char *buf, |
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size_t len) |
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{ |
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struct ti_eqep_cnt *priv = counter->priv; |
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int err; |
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u32 res; |
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err = kstrtouint(buf, 0, &res); |
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if (err < 0) |
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return err; |
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regmap_write(priv->regmap32, QPOSMAX, res); |
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return len; |
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} |
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static ssize_t ti_eqep_position_enable_read(struct counter_device *counter, |
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struct counter_count *count, |
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void *ext_priv, char *buf) |
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{ |
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struct ti_eqep_cnt *priv = counter->priv; |
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u32 qepctl; |
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regmap_read(priv->regmap16, QEPCTL, &qepctl); |
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return sprintf(buf, "%u\n", !!(qepctl & QEPCTL_PHEN)); |
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} |
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static ssize_t ti_eqep_position_enable_write(struct counter_device *counter, |
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struct counter_count *count, |
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void *ext_priv, const char *buf, |
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size_t len) |
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{ |
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struct ti_eqep_cnt *priv = counter->priv; |
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int err; |
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bool res; |
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err = kstrtobool(buf, &res); |
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if (err < 0) |
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return err; |
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regmap_write_bits(priv->regmap16, QEPCTL, QEPCTL_PHEN, res ? -1 : 0); |
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return len; |
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} |
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static struct counter_count_ext ti_eqep_position_ext[] = { |
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{ |
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.name = "ceiling", |
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.read = ti_eqep_position_ceiling_read, |
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.write = ti_eqep_position_ceiling_write, |
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}, |
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{ |
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.name = "enable", |
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.read = ti_eqep_position_enable_read, |
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.write = ti_eqep_position_enable_write, |
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}, |
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}; |
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static struct counter_signal ti_eqep_signals[] = { |
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[TI_EQEP_SIGNAL_QEPA] = { |
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.id = TI_EQEP_SIGNAL_QEPA, |
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.name = "QEPA" |
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}, |
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[TI_EQEP_SIGNAL_QEPB] = { |
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.id = TI_EQEP_SIGNAL_QEPB, |
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.name = "QEPB" |
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}, |
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}; |
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static const enum counter_function ti_eqep_position_functions[] = { |
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[TI_EQEP_COUNT_FUNC_QUAD_COUNT] = COUNTER_FUNCTION_QUADRATURE_X4, |
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[TI_EQEP_COUNT_FUNC_DIR_COUNT] = COUNTER_FUNCTION_PULSE_DIRECTION, |
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[TI_EQEP_COUNT_FUNC_UP_COUNT] = COUNTER_FUNCTION_INCREASE, |
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[TI_EQEP_COUNT_FUNC_DOWN_COUNT] = COUNTER_FUNCTION_DECREASE, |
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}; |
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static const enum counter_synapse_action ti_eqep_position_synapse_actions[] = { |
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[TI_EQEP_SYNAPSE_ACTION_BOTH_EDGES] = COUNTER_SYNAPSE_ACTION_BOTH_EDGES, |
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[TI_EQEP_SYNAPSE_ACTION_RISING_EDGE] = COUNTER_SYNAPSE_ACTION_RISING_EDGE, |
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[TI_EQEP_SYNAPSE_ACTION_NONE] = COUNTER_SYNAPSE_ACTION_NONE, |
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}; |
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static struct counter_synapse ti_eqep_position_synapses[] = { |
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{ |
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.actions_list = ti_eqep_position_synapse_actions, |
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.num_actions = ARRAY_SIZE(ti_eqep_position_synapse_actions), |
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.signal = &ti_eqep_signals[TI_EQEP_SIGNAL_QEPA], |
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}, |
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{ |
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.actions_list = ti_eqep_position_synapse_actions, |
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.num_actions = ARRAY_SIZE(ti_eqep_position_synapse_actions), |
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.signal = &ti_eqep_signals[TI_EQEP_SIGNAL_QEPB], |
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}, |
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}; |
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static struct counter_count ti_eqep_counts[] = { |
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{ |
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.id = 0, |
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.name = "QPOSCNT", |
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.functions_list = ti_eqep_position_functions, |
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.num_functions = ARRAY_SIZE(ti_eqep_position_functions), |
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.synapses = ti_eqep_position_synapses, |
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.num_synapses = ARRAY_SIZE(ti_eqep_position_synapses), |
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.ext = ti_eqep_position_ext, |
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.num_ext = ARRAY_SIZE(ti_eqep_position_ext), |
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}, |
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}; |
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static const struct regmap_config ti_eqep_regmap32_config = { |
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.name = "32-bit", |
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.reg_bits = 32, |
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.val_bits = 32, |
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.reg_stride = 4, |
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.max_register = QUPRD, |
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}; |
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static const struct regmap_config ti_eqep_regmap16_config = { |
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.name = "16-bit", |
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.reg_bits = 16, |
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.val_bits = 16, |
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.reg_stride = 2, |
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.max_register = QCPRDLAT, |
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}; |
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static int ti_eqep_probe(struct platform_device *pdev) |
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{ |
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struct device *dev = &pdev->dev; |
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struct ti_eqep_cnt *priv; |
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void __iomem *base; |
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int err; |
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priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); |
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if (!priv) |
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return -ENOMEM; |
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base = devm_platform_ioremap_resource(pdev, 0); |
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if (IS_ERR(base)) |
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return PTR_ERR(base); |
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priv->regmap32 = devm_regmap_init_mmio(dev, base, |
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&ti_eqep_regmap32_config); |
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if (IS_ERR(priv->regmap32)) |
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return PTR_ERR(priv->regmap32); |
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priv->regmap16 = devm_regmap_init_mmio(dev, base + 0x24, |
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&ti_eqep_regmap16_config); |
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if (IS_ERR(priv->regmap16)) |
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return PTR_ERR(priv->regmap16); |
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priv->counter.name = dev_name(dev); |
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priv->counter.parent = dev; |
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priv->counter.ops = &ti_eqep_counter_ops; |
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priv->counter.counts = ti_eqep_counts; |
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priv->counter.num_counts = ARRAY_SIZE(ti_eqep_counts); |
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priv->counter.signals = ti_eqep_signals; |
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priv->counter.num_signals = ARRAY_SIZE(ti_eqep_signals); |
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priv->counter.priv = priv; |
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platform_set_drvdata(pdev, priv); |
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/* |
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* Need to make sure power is turned on. On AM33xx, this comes from the |
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* parent PWMSS bus driver. On AM17xx, this comes from the PSC power |
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* domain. |
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*/ |
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pm_runtime_enable(dev); |
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pm_runtime_get_sync(dev); |
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err = counter_register(&priv->counter); |
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if (err < 0) { |
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pm_runtime_put_sync(dev); |
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pm_runtime_disable(dev); |
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return err; |
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} |
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return 0; |
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} |
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static int ti_eqep_remove(struct platform_device *pdev) |
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{ |
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struct ti_eqep_cnt *priv = platform_get_drvdata(pdev); |
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struct device *dev = &pdev->dev; |
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counter_unregister(&priv->counter); |
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pm_runtime_put_sync(dev); |
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pm_runtime_disable(dev); |
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return 0; |
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} |
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static const struct of_device_id ti_eqep_of_match[] = { |
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{ .compatible = "ti,am3352-eqep", }, |
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{ }, |
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}; |
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MODULE_DEVICE_TABLE(of, ti_eqep_of_match); |
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static struct platform_driver ti_eqep_driver = { |
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.probe = ti_eqep_probe, |
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.remove = ti_eqep_remove, |
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.driver = { |
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.name = "ti-eqep-cnt", |
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.of_match_table = ti_eqep_of_match, |
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}, |
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}; |
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module_platform_driver(ti_eqep_driver); |
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MODULE_AUTHOR("David Lechner <[email protected]>"); |
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MODULE_DESCRIPTION("TI eQEP counter driver"); |
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MODULE_LICENSE("GPL v2");
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