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242 lines
6.7 KiB
242 lines
6.7 KiB
// SPDX-License-Identifier: GPL-2.0-or-later |
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/* |
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* Copyright (C) 2014 Oleksij Rempel <[email protected]> |
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*/ |
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#include <linux/kernel.h> |
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#include <linux/init.h> |
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#include <linux/interrupt.h> |
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#include <linux/sched.h> |
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#include <linux/clk.h> |
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#include <linux/clocksource.h> |
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#include <linux/clockchips.h> |
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#include <linux/io.h> |
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#include <linux/of.h> |
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#include <linux/of_address.h> |
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#include <linux/of_irq.h> |
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#include <linux/bitops.h> |
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#define DRIVER_NAME "asm9260-timer" |
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/* |
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* this device provide 4 offsets for each register: |
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* 0x0 - plain read write mode |
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* 0x4 - set mode, OR logic. |
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* 0x8 - clr mode, XOR logic. |
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* 0xc - togle mode. |
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*/ |
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#define SET_REG 4 |
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#define CLR_REG 8 |
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#define HW_IR 0x0000 /* RW. Interrupt */ |
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#define BM_IR_CR0 BIT(4) |
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#define BM_IR_MR3 BIT(3) |
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#define BM_IR_MR2 BIT(2) |
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#define BM_IR_MR1 BIT(1) |
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#define BM_IR_MR0 BIT(0) |
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#define HW_TCR 0x0010 /* RW. Timer controller */ |
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/* BM_C*_RST |
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* Timer Counter and the Prescale Counter are synchronously reset on the |
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* next positive edge of PCLK. The counters remain reset until TCR[1] is |
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* returned to zero. */ |
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#define BM_C3_RST BIT(7) |
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#define BM_C2_RST BIT(6) |
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#define BM_C1_RST BIT(5) |
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#define BM_C0_RST BIT(4) |
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/* BM_C*_EN |
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* 1 - Timer Counter and Prescale Counter are enabled for counting |
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* 0 - counters are disabled */ |
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#define BM_C3_EN BIT(3) |
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#define BM_C2_EN BIT(2) |
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#define BM_C1_EN BIT(1) |
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#define BM_C0_EN BIT(0) |
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#define HW_DIR 0x0020 /* RW. Direction? */ |
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/* 00 - count up |
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* 01 - count down |
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* 10 - ?? 2^n/2 */ |
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#define BM_DIR_COUNT_UP 0 |
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#define BM_DIR_COUNT_DOWN 1 |
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#define BM_DIR0_SHIFT 0 |
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#define BM_DIR1_SHIFT 4 |
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#define BM_DIR2_SHIFT 8 |
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#define BM_DIR3_SHIFT 12 |
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#define BM_DIR_DEFAULT (BM_DIR_COUNT_UP << BM_DIR0_SHIFT | \ |
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BM_DIR_COUNT_UP << BM_DIR1_SHIFT | \ |
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BM_DIR_COUNT_UP << BM_DIR2_SHIFT | \ |
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BM_DIR_COUNT_UP << BM_DIR3_SHIFT) |
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#define HW_TC0 0x0030 /* RO. Timer counter 0 */ |
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/* HW_TC*. Timer counter owerflow (0xffff.ffff to 0x0000.0000) do not generate |
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* interrupt. This registers can be used to detect overflow */ |
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#define HW_TC1 0x0040 |
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#define HW_TC2 0x0050 |
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#define HW_TC3 0x0060 |
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#define HW_PR 0x0070 /* RW. prescaler */ |
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#define BM_PR_DISABLE 0 |
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#define HW_PC 0x0080 /* RO. Prescaler counter */ |
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#define HW_MCR 0x0090 /* RW. Match control */ |
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/* enable interrupt on match */ |
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#define BM_MCR_INT_EN(n) (1 << (n * 3 + 0)) |
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/* enable TC reset on match */ |
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#define BM_MCR_RES_EN(n) (1 << (n * 3 + 1)) |
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/* enable stop TC on match */ |
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#define BM_MCR_STOP_EN(n) (1 << (n * 3 + 2)) |
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#define HW_MR0 0x00a0 /* RW. Match reg */ |
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#define HW_MR1 0x00b0 |
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#define HW_MR2 0x00C0 |
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#define HW_MR3 0x00D0 |
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#define HW_CTCR 0x0180 /* Counter control */ |
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#define BM_CTCR0_SHIFT 0 |
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#define BM_CTCR1_SHIFT 2 |
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#define BM_CTCR2_SHIFT 4 |
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#define BM_CTCR3_SHIFT 6 |
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#define BM_CTCR_TM 0 /* Timer mode. Every rising PCLK edge. */ |
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#define BM_CTCR_DEFAULT (BM_CTCR_TM << BM_CTCR0_SHIFT | \ |
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BM_CTCR_TM << BM_CTCR1_SHIFT | \ |
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BM_CTCR_TM << BM_CTCR2_SHIFT | \ |
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BM_CTCR_TM << BM_CTCR3_SHIFT) |
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static struct asm9260_timer_priv { |
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void __iomem *base; |
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unsigned long ticks_per_jiffy; |
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} priv; |
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static int asm9260_timer_set_next_event(unsigned long delta, |
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struct clock_event_device *evt) |
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{ |
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/* configure match count for TC0 */ |
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writel_relaxed(delta, priv.base + HW_MR0); |
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/* enable TC0 */ |
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writel_relaxed(BM_C0_EN, priv.base + HW_TCR + SET_REG); |
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return 0; |
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} |
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static inline void __asm9260_timer_shutdown(struct clock_event_device *evt) |
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{ |
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/* stop timer0 */ |
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writel_relaxed(BM_C0_EN, priv.base + HW_TCR + CLR_REG); |
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} |
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static int asm9260_timer_shutdown(struct clock_event_device *evt) |
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{ |
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__asm9260_timer_shutdown(evt); |
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return 0; |
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} |
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static int asm9260_timer_set_oneshot(struct clock_event_device *evt) |
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{ |
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__asm9260_timer_shutdown(evt); |
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/* enable reset and stop on match */ |
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writel_relaxed(BM_MCR_RES_EN(0) | BM_MCR_STOP_EN(0), |
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priv.base + HW_MCR + SET_REG); |
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return 0; |
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} |
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static int asm9260_timer_set_periodic(struct clock_event_device *evt) |
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{ |
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__asm9260_timer_shutdown(evt); |
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/* disable reset and stop on match */ |
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writel_relaxed(BM_MCR_RES_EN(0) | BM_MCR_STOP_EN(0), |
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priv.base + HW_MCR + CLR_REG); |
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/* configure match count for TC0 */ |
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writel_relaxed(priv.ticks_per_jiffy, priv.base + HW_MR0); |
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/* enable TC0 */ |
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writel_relaxed(BM_C0_EN, priv.base + HW_TCR + SET_REG); |
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return 0; |
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} |
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static struct clock_event_device event_dev = { |
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.name = DRIVER_NAME, |
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.rating = 200, |
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.features = CLOCK_EVT_FEAT_PERIODIC | |
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CLOCK_EVT_FEAT_ONESHOT, |
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.set_next_event = asm9260_timer_set_next_event, |
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.set_state_shutdown = asm9260_timer_shutdown, |
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.set_state_periodic = asm9260_timer_set_periodic, |
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.set_state_oneshot = asm9260_timer_set_oneshot, |
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.tick_resume = asm9260_timer_shutdown, |
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}; |
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static irqreturn_t asm9260_timer_interrupt(int irq, void *dev_id) |
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{ |
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struct clock_event_device *evt = dev_id; |
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evt->event_handler(evt); |
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writel_relaxed(BM_IR_MR0, priv.base + HW_IR); |
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return IRQ_HANDLED; |
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} |
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/* |
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* --------------------------------------------------------------------------- |
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* Timer initialization |
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* --------------------------------------------------------------------------- |
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*/ |
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static int __init asm9260_timer_init(struct device_node *np) |
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{ |
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int irq; |
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struct clk *clk; |
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int ret; |
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unsigned long rate; |
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priv.base = of_io_request_and_map(np, 0, np->name); |
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if (IS_ERR(priv.base)) { |
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pr_err("%pOFn: unable to map resource\n", np); |
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return PTR_ERR(priv.base); |
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} |
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clk = of_clk_get(np, 0); |
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if (IS_ERR(clk)) { |
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pr_err("Failed to get clk!\n"); |
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return PTR_ERR(clk); |
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} |
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ret = clk_prepare_enable(clk); |
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if (ret) { |
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pr_err("Failed to enable clk!\n"); |
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return ret; |
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} |
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irq = irq_of_parse_and_map(np, 0); |
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ret = request_irq(irq, asm9260_timer_interrupt, IRQF_TIMER, |
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DRIVER_NAME, &event_dev); |
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if (ret) { |
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pr_err("Failed to setup irq!\n"); |
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return ret; |
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} |
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/* set all timers for count-up */ |
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writel_relaxed(BM_DIR_DEFAULT, priv.base + HW_DIR); |
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/* disable divider */ |
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writel_relaxed(BM_PR_DISABLE, priv.base + HW_PR); |
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/* make sure all timers use every rising PCLK edge. */ |
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writel_relaxed(BM_CTCR_DEFAULT, priv.base + HW_CTCR); |
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/* enable interrupt for TC0 and clean setting for all other lines */ |
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writel_relaxed(BM_MCR_INT_EN(0) , priv.base + HW_MCR); |
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rate = clk_get_rate(clk); |
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clocksource_mmio_init(priv.base + HW_TC1, DRIVER_NAME, rate, |
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200, 32, clocksource_mmio_readl_up); |
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/* Seems like we can't use counter without match register even if |
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* actions for MR are disabled. So, set MR to max value. */ |
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writel_relaxed(0xffffffff, priv.base + HW_MR1); |
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/* enable TC1 */ |
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writel_relaxed(BM_C1_EN, priv.base + HW_TCR + SET_REG); |
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priv.ticks_per_jiffy = DIV_ROUND_CLOSEST(rate, HZ); |
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event_dev.cpumask = cpumask_of(0); |
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clockevents_config_and_register(&event_dev, rate, 0x2c00, 0xfffffffe); |
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return 0; |
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} |
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TIMER_OF_DECLARE(asm9260_timer, "alphascale,asm9260-timer", |
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asm9260_timer_init);
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