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242 lines
6.2 KiB
242 lines
6.2 KiB
// SPDX-License-Identifier: GPL-2.0 |
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/* |
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* Copyright (C) 2015 Chen-Yu Tsai |
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* |
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* Chen-Yu Tsai <[email protected]> |
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* |
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* Allwinner A80 CPUS clock driver |
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* |
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*/ |
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#include <linux/clk.h> |
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#include <linux/clk-provider.h> |
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#include <linux/io.h> |
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#include <linux/slab.h> |
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#include <linux/spinlock.h> |
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#include <linux/of.h> |
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#include <linux/of_address.h> |
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static DEFINE_SPINLOCK(sun9i_a80_cpus_lock); |
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/** |
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* sun9i_a80_cpus_clk_setup() - Setup function for a80 cpus composite clk |
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*/ |
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#define SUN9I_CPUS_MAX_PARENTS 4 |
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#define SUN9I_CPUS_MUX_PARENT_PLL4 3 |
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#define SUN9I_CPUS_MUX_SHIFT 16 |
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#define SUN9I_CPUS_MUX_MASK GENMASK(17, 16) |
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#define SUN9I_CPUS_MUX_GET_PARENT(reg) ((reg & SUN9I_CPUS_MUX_MASK) >> \ |
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SUN9I_CPUS_MUX_SHIFT) |
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#define SUN9I_CPUS_DIV_SHIFT 4 |
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#define SUN9I_CPUS_DIV_MASK GENMASK(5, 4) |
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#define SUN9I_CPUS_DIV_GET(reg) ((reg & SUN9I_CPUS_DIV_MASK) >> \ |
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SUN9I_CPUS_DIV_SHIFT) |
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#define SUN9I_CPUS_DIV_SET(reg, div) ((reg & ~SUN9I_CPUS_DIV_MASK) | \ |
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(div << SUN9I_CPUS_DIV_SHIFT)) |
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#define SUN9I_CPUS_PLL4_DIV_SHIFT 8 |
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#define SUN9I_CPUS_PLL4_DIV_MASK GENMASK(12, 8) |
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#define SUN9I_CPUS_PLL4_DIV_GET(reg) ((reg & SUN9I_CPUS_PLL4_DIV_MASK) >> \ |
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SUN9I_CPUS_PLL4_DIV_SHIFT) |
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#define SUN9I_CPUS_PLL4_DIV_SET(reg, div) ((reg & ~SUN9I_CPUS_PLL4_DIV_MASK) | \ |
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(div << SUN9I_CPUS_PLL4_DIV_SHIFT)) |
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struct sun9i_a80_cpus_clk { |
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struct clk_hw hw; |
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void __iomem *reg; |
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}; |
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#define to_sun9i_a80_cpus_clk(_hw) container_of(_hw, struct sun9i_a80_cpus_clk, hw) |
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static unsigned long sun9i_a80_cpus_clk_recalc_rate(struct clk_hw *hw, |
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unsigned long parent_rate) |
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{ |
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struct sun9i_a80_cpus_clk *cpus = to_sun9i_a80_cpus_clk(hw); |
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unsigned long rate; |
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u32 reg; |
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/* Fetch the register value */ |
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reg = readl(cpus->reg); |
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/* apply pre-divider first if parent is pll4 */ |
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if (SUN9I_CPUS_MUX_GET_PARENT(reg) == SUN9I_CPUS_MUX_PARENT_PLL4) |
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parent_rate /= SUN9I_CPUS_PLL4_DIV_GET(reg) + 1; |
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/* clk divider */ |
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rate = parent_rate / (SUN9I_CPUS_DIV_GET(reg) + 1); |
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return rate; |
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} |
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static long sun9i_a80_cpus_clk_round(unsigned long rate, u8 *divp, u8 *pre_divp, |
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u8 parent, unsigned long parent_rate) |
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{ |
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u8 div, pre_div = 1; |
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/* |
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* clock can only divide, so we will never be able to achieve |
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* frequencies higher than the parent frequency |
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*/ |
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if (parent_rate && rate > parent_rate) |
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rate = parent_rate; |
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div = DIV_ROUND_UP(parent_rate, rate); |
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/* calculate pre-divider if parent is pll4 */ |
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if (parent == SUN9I_CPUS_MUX_PARENT_PLL4 && div > 4) { |
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/* pre-divider is 1 ~ 32 */ |
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if (div < 32) { |
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pre_div = div; |
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div = 1; |
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} else if (div < 64) { |
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pre_div = DIV_ROUND_UP(div, 2); |
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div = 2; |
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} else if (div < 96) { |
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pre_div = DIV_ROUND_UP(div, 3); |
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div = 3; |
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} else { |
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pre_div = DIV_ROUND_UP(div, 4); |
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div = 4; |
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} |
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} |
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/* we were asked to pass back divider values */ |
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if (divp) { |
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*divp = div - 1; |
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*pre_divp = pre_div - 1; |
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} |
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return parent_rate / pre_div / div; |
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} |
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static int sun9i_a80_cpus_clk_determine_rate(struct clk_hw *clk, |
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struct clk_rate_request *req) |
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{ |
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struct clk_hw *parent, *best_parent = NULL; |
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int i, num_parents; |
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unsigned long parent_rate, best = 0, child_rate, best_child_rate = 0; |
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unsigned long rate = req->rate; |
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/* find the parent that can help provide the fastest rate <= rate */ |
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num_parents = clk_hw_get_num_parents(clk); |
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for (i = 0; i < num_parents; i++) { |
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parent = clk_hw_get_parent_by_index(clk, i); |
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if (!parent) |
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continue; |
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if (clk_hw_get_flags(clk) & CLK_SET_RATE_PARENT) |
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parent_rate = clk_hw_round_rate(parent, rate); |
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else |
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parent_rate = clk_hw_get_rate(parent); |
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child_rate = sun9i_a80_cpus_clk_round(rate, NULL, NULL, i, |
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parent_rate); |
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if (child_rate <= rate && child_rate > best_child_rate) { |
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best_parent = parent; |
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best = parent_rate; |
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best_child_rate = child_rate; |
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} |
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} |
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if (!best_parent) |
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return -EINVAL; |
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req->best_parent_hw = best_parent; |
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req->best_parent_rate = best; |
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req->rate = best_child_rate; |
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return 0; |
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} |
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static int sun9i_a80_cpus_clk_set_rate(struct clk_hw *hw, unsigned long rate, |
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unsigned long parent_rate) |
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{ |
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struct sun9i_a80_cpus_clk *cpus = to_sun9i_a80_cpus_clk(hw); |
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unsigned long flags; |
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u8 div, pre_div, parent; |
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u32 reg; |
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spin_lock_irqsave(&sun9i_a80_cpus_lock, flags); |
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reg = readl(cpus->reg); |
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/* need to know which parent is used to apply pre-divider */ |
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parent = SUN9I_CPUS_MUX_GET_PARENT(reg); |
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sun9i_a80_cpus_clk_round(rate, &div, &pre_div, parent, parent_rate); |
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reg = SUN9I_CPUS_DIV_SET(reg, div); |
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reg = SUN9I_CPUS_PLL4_DIV_SET(reg, pre_div); |
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writel(reg, cpus->reg); |
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spin_unlock_irqrestore(&sun9i_a80_cpus_lock, flags); |
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return 0; |
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} |
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static const struct clk_ops sun9i_a80_cpus_clk_ops = { |
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.determine_rate = sun9i_a80_cpus_clk_determine_rate, |
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.recalc_rate = sun9i_a80_cpus_clk_recalc_rate, |
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.set_rate = sun9i_a80_cpus_clk_set_rate, |
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}; |
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static void sun9i_a80_cpus_setup(struct device_node *node) |
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{ |
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const char *clk_name = node->name; |
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const char *parents[SUN9I_CPUS_MAX_PARENTS]; |
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struct resource res; |
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struct sun9i_a80_cpus_clk *cpus; |
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struct clk_mux *mux; |
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struct clk *clk; |
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int ret; |
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cpus = kzalloc(sizeof(*cpus), GFP_KERNEL); |
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if (!cpus) |
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return; |
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cpus->reg = of_io_request_and_map(node, 0, of_node_full_name(node)); |
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if (IS_ERR(cpus->reg)) |
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goto err_free_cpus; |
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of_property_read_string(node, "clock-output-names", &clk_name); |
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/* we have a mux, we will have >1 parents */ |
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ret = of_clk_parent_fill(node, parents, SUN9I_CPUS_MAX_PARENTS); |
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mux = kzalloc(sizeof(*mux), GFP_KERNEL); |
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if (!mux) |
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goto err_unmap; |
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/* set up clock properties */ |
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mux->reg = cpus->reg; |
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mux->shift = SUN9I_CPUS_MUX_SHIFT; |
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/* un-shifted mask is what mux_clk expects */ |
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mux->mask = SUN9I_CPUS_MUX_MASK >> SUN9I_CPUS_MUX_SHIFT; |
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mux->lock = &sun9i_a80_cpus_lock; |
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clk = clk_register_composite(NULL, clk_name, parents, ret, |
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&mux->hw, &clk_mux_ops, |
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&cpus->hw, &sun9i_a80_cpus_clk_ops, |
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NULL, NULL, 0); |
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if (IS_ERR(clk)) |
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goto err_free_mux; |
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ret = of_clk_add_provider(node, of_clk_src_simple_get, clk); |
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if (ret) |
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goto err_unregister; |
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return; |
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err_unregister: |
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clk_unregister(clk); |
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err_free_mux: |
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kfree(mux); |
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err_unmap: |
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iounmap(cpus->reg); |
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of_address_to_resource(node, 0, &res); |
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release_mem_region(res.start, resource_size(&res)); |
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err_free_cpus: |
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kfree(cpus); |
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} |
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CLK_OF_DECLARE(sun9i_a80_cpus, "allwinner,sun9i-a80-cpus-clk", |
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sun9i_a80_cpus_setup);
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