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163 lines
3.7 KiB
163 lines
3.7 KiB
/* |
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* Copyright (C) 2012 ST Microelectronics |
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* Viresh Kumar <[email protected]> |
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* |
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* This file is licensed under the terms of the GNU General Public |
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* License version 2. This program is licensed "as is" without any |
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* warranty of any kind, whether express or implied. |
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* |
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* Fractional Synthesizer clock implementation |
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*/ |
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#define pr_fmt(fmt) "clk-frac-synth: " fmt |
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#include <linux/clk-provider.h> |
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#include <linux/slab.h> |
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#include <linux/io.h> |
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#include <linux/err.h> |
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#include "clk.h" |
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#define DIV_FACTOR_MASK 0x1FFFF |
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/* |
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* DOC: Fractional Synthesizer clock |
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* |
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* Fout from synthesizer can be given from below equation: |
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* |
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* Fout= Fin/2*div (division factor) |
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* div is 17 bits:- |
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* 0-13 (fractional part) |
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* 14-16 (integer part) |
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* div is (16-14 bits).(13-0 bits) (in binary) |
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* |
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* Fout = Fin/(2 * div) |
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* Fout = ((Fin / 10000)/(2 * div)) * 10000 |
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* Fout = (2^14 * (Fin / 10000)/(2^14 * (2 * div))) * 10000 |
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* Fout = (((Fin / 10000) << 14)/(2 * (div << 14))) * 10000 |
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* |
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* div << 14 simply 17 bit value written at register. |
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* Max error due to scaling down by 10000 is 10 KHz |
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*/ |
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#define to_clk_frac(_hw) container_of(_hw, struct clk_frac, hw) |
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static unsigned long frac_calc_rate(struct clk_hw *hw, unsigned long prate, |
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int index) |
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{ |
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struct clk_frac *frac = to_clk_frac(hw); |
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struct frac_rate_tbl *rtbl = frac->rtbl; |
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prate /= 10000; |
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prate <<= 14; |
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prate /= (2 * rtbl[index].div); |
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prate *= 10000; |
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return prate; |
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} |
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static long clk_frac_round_rate(struct clk_hw *hw, unsigned long drate, |
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unsigned long *prate) |
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{ |
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struct clk_frac *frac = to_clk_frac(hw); |
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int unused; |
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return clk_round_rate_index(hw, drate, *prate, frac_calc_rate, |
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frac->rtbl_cnt, &unused); |
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} |
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static unsigned long clk_frac_recalc_rate(struct clk_hw *hw, |
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unsigned long parent_rate) |
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{ |
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struct clk_frac *frac = to_clk_frac(hw); |
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unsigned long flags = 0; |
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unsigned int div = 1, val; |
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if (frac->lock) |
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spin_lock_irqsave(frac->lock, flags); |
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val = readl_relaxed(frac->reg); |
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if (frac->lock) |
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spin_unlock_irqrestore(frac->lock, flags); |
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div = val & DIV_FACTOR_MASK; |
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if (!div) |
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return 0; |
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parent_rate = parent_rate / 10000; |
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parent_rate = (parent_rate << 14) / (2 * div); |
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return parent_rate * 10000; |
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} |
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/* Configures new clock rate of frac */ |
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static int clk_frac_set_rate(struct clk_hw *hw, unsigned long drate, |
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unsigned long prate) |
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{ |
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struct clk_frac *frac = to_clk_frac(hw); |
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struct frac_rate_tbl *rtbl = frac->rtbl; |
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unsigned long flags = 0, val; |
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int i; |
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clk_round_rate_index(hw, drate, prate, frac_calc_rate, frac->rtbl_cnt, |
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&i); |
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if (frac->lock) |
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spin_lock_irqsave(frac->lock, flags); |
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val = readl_relaxed(frac->reg) & ~DIV_FACTOR_MASK; |
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val |= rtbl[i].div & DIV_FACTOR_MASK; |
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writel_relaxed(val, frac->reg); |
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if (frac->lock) |
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spin_unlock_irqrestore(frac->lock, flags); |
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return 0; |
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} |
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static const struct clk_ops clk_frac_ops = { |
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.recalc_rate = clk_frac_recalc_rate, |
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.round_rate = clk_frac_round_rate, |
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.set_rate = clk_frac_set_rate, |
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}; |
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struct clk *clk_register_frac(const char *name, const char *parent_name, |
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unsigned long flags, void __iomem *reg, |
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struct frac_rate_tbl *rtbl, u8 rtbl_cnt, spinlock_t *lock) |
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{ |
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struct clk_init_data init; |
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struct clk_frac *frac; |
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struct clk *clk; |
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if (!name || !parent_name || !reg || !rtbl || !rtbl_cnt) { |
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pr_err("Invalid arguments passed\n"); |
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return ERR_PTR(-EINVAL); |
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} |
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frac = kzalloc(sizeof(*frac), GFP_KERNEL); |
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if (!frac) |
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return ERR_PTR(-ENOMEM); |
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/* struct clk_frac assignments */ |
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frac->reg = reg; |
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frac->rtbl = rtbl; |
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frac->rtbl_cnt = rtbl_cnt; |
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frac->lock = lock; |
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frac->hw.init = &init; |
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init.name = name; |
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init.ops = &clk_frac_ops; |
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init.flags = flags; |
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init.parent_names = &parent_name; |
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init.num_parents = 1; |
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clk = clk_register(NULL, &frac->hw); |
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if (!IS_ERR_OR_NULL(clk)) |
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return clk; |
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pr_err("clk register failed\n"); |
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kfree(frac); |
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return NULL; |
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}
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