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211 lines
5.7 KiB
211 lines
5.7 KiB
// SPDX-License-Identifier: GPL-2.0-only |
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/* |
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* Copyright (c) 2014 Tomasz Figa <[email protected]> |
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* |
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* Based on Exynos Audio Subsystem Clock Controller driver: |
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* |
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* Copyright (c) 2013 Samsung Electronics Co., Ltd. |
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* Author: Padmavathi Venna <[email protected]> |
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* |
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* Driver for Audio Subsystem Clock Controller of S5PV210-compatible SoCs. |
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*/ |
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#include <linux/io.h> |
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#include <linux/clk.h> |
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#include <linux/clk-provider.h> |
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#include <linux/of_address.h> |
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#include <linux/syscore_ops.h> |
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#include <linux/init.h> |
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#include <linux/platform_device.h> |
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#include <dt-bindings/clock/s5pv210-audss.h> |
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static DEFINE_SPINLOCK(lock); |
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static void __iomem *reg_base; |
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static struct clk_hw_onecell_data *clk_data; |
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#define ASS_CLK_SRC 0x0 |
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#define ASS_CLK_DIV 0x4 |
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#define ASS_CLK_GATE 0x8 |
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#ifdef CONFIG_PM_SLEEP |
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static unsigned long reg_save[][2] = { |
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{ASS_CLK_SRC, 0}, |
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{ASS_CLK_DIV, 0}, |
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{ASS_CLK_GATE, 0}, |
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}; |
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static int s5pv210_audss_clk_suspend(void) |
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{ |
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int i; |
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for (i = 0; i < ARRAY_SIZE(reg_save); i++) |
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reg_save[i][1] = readl(reg_base + reg_save[i][0]); |
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return 0; |
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} |
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static void s5pv210_audss_clk_resume(void) |
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{ |
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int i; |
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for (i = 0; i < ARRAY_SIZE(reg_save); i++) |
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writel(reg_save[i][1], reg_base + reg_save[i][0]); |
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} |
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static struct syscore_ops s5pv210_audss_clk_syscore_ops = { |
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.suspend = s5pv210_audss_clk_suspend, |
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.resume = s5pv210_audss_clk_resume, |
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}; |
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#endif /* CONFIG_PM_SLEEP */ |
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/* register s5pv210_audss clocks */ |
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static int s5pv210_audss_clk_probe(struct platform_device *pdev) |
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{ |
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int i, ret = 0; |
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struct resource *res; |
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const char *mout_audss_p[2]; |
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const char *mout_i2s_p[3]; |
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const char *hclk_p; |
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struct clk_hw **clk_table; |
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struct clk *hclk, *pll_ref, *pll_in, *cdclk, *sclk_audio; |
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
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reg_base = devm_ioremap_resource(&pdev->dev, res); |
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if (IS_ERR(reg_base)) |
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return PTR_ERR(reg_base); |
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clk_data = devm_kzalloc(&pdev->dev, |
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struct_size(clk_data, hws, AUDSS_MAX_CLKS), |
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GFP_KERNEL); |
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if (!clk_data) |
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return -ENOMEM; |
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clk_data->num = AUDSS_MAX_CLKS; |
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clk_table = clk_data->hws; |
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hclk = devm_clk_get(&pdev->dev, "hclk"); |
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if (IS_ERR(hclk)) { |
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dev_err(&pdev->dev, "failed to get hclk clock\n"); |
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return PTR_ERR(hclk); |
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} |
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pll_in = devm_clk_get(&pdev->dev, "fout_epll"); |
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if (IS_ERR(pll_in)) { |
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dev_err(&pdev->dev, "failed to get fout_epll clock\n"); |
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return PTR_ERR(pll_in); |
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} |
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sclk_audio = devm_clk_get(&pdev->dev, "sclk_audio0"); |
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if (IS_ERR(sclk_audio)) { |
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dev_err(&pdev->dev, "failed to get sclk_audio0 clock\n"); |
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return PTR_ERR(sclk_audio); |
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} |
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/* iiscdclk0 is an optional external I2S codec clock */ |
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cdclk = devm_clk_get(&pdev->dev, "iiscdclk0"); |
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pll_ref = devm_clk_get(&pdev->dev, "xxti"); |
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if (!IS_ERR(pll_ref)) |
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mout_audss_p[0] = __clk_get_name(pll_ref); |
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else |
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mout_audss_p[0] = "xxti"; |
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mout_audss_p[1] = __clk_get_name(pll_in); |
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clk_table[CLK_MOUT_AUDSS] = clk_hw_register_mux(NULL, "mout_audss", |
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mout_audss_p, ARRAY_SIZE(mout_audss_p), |
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CLK_SET_RATE_NO_REPARENT, |
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reg_base + ASS_CLK_SRC, 0, 1, 0, &lock); |
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mout_i2s_p[0] = "mout_audss"; |
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if (!IS_ERR(cdclk)) |
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mout_i2s_p[1] = __clk_get_name(cdclk); |
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else |
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mout_i2s_p[1] = "iiscdclk0"; |
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mout_i2s_p[2] = __clk_get_name(sclk_audio); |
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clk_table[CLK_MOUT_I2S_A] = clk_hw_register_mux(NULL, "mout_i2s_audss", |
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mout_i2s_p, ARRAY_SIZE(mout_i2s_p), |
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CLK_SET_RATE_NO_REPARENT, |
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reg_base + ASS_CLK_SRC, 2, 2, 0, &lock); |
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clk_table[CLK_DOUT_AUD_BUS] = clk_hw_register_divider(NULL, |
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"dout_aud_bus", "mout_audss", 0, |
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reg_base + ASS_CLK_DIV, 0, 4, 0, &lock); |
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clk_table[CLK_DOUT_I2S_A] = clk_hw_register_divider(NULL, |
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"dout_i2s_audss", "mout_i2s_audss", 0, |
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reg_base + ASS_CLK_DIV, 4, 4, 0, &lock); |
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clk_table[CLK_I2S] = clk_hw_register_gate(NULL, "i2s_audss", |
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"dout_i2s_audss", CLK_SET_RATE_PARENT, |
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reg_base + ASS_CLK_GATE, 6, 0, &lock); |
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hclk_p = __clk_get_name(hclk); |
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clk_table[CLK_HCLK_I2S] = clk_hw_register_gate(NULL, "hclk_i2s_audss", |
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hclk_p, CLK_IGNORE_UNUSED, |
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reg_base + ASS_CLK_GATE, 5, 0, &lock); |
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clk_table[CLK_HCLK_UART] = clk_hw_register_gate(NULL, "hclk_uart_audss", |
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hclk_p, CLK_IGNORE_UNUSED, |
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reg_base + ASS_CLK_GATE, 4, 0, &lock); |
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clk_table[CLK_HCLK_HWA] = clk_hw_register_gate(NULL, "hclk_hwa_audss", |
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hclk_p, CLK_IGNORE_UNUSED, |
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reg_base + ASS_CLK_GATE, 3, 0, &lock); |
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clk_table[CLK_HCLK_DMA] = clk_hw_register_gate(NULL, "hclk_dma_audss", |
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hclk_p, CLK_IGNORE_UNUSED, |
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reg_base + ASS_CLK_GATE, 2, 0, &lock); |
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clk_table[CLK_HCLK_BUF] = clk_hw_register_gate(NULL, "hclk_buf_audss", |
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hclk_p, CLK_IGNORE_UNUSED, |
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reg_base + ASS_CLK_GATE, 1, 0, &lock); |
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clk_table[CLK_HCLK_RP] = clk_hw_register_gate(NULL, "hclk_rp_audss", |
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hclk_p, CLK_IGNORE_UNUSED, |
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reg_base + ASS_CLK_GATE, 0, 0, &lock); |
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for (i = 0; i < clk_data->num; i++) { |
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if (IS_ERR(clk_table[i])) { |
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dev_err(&pdev->dev, "failed to register clock %d\n", i); |
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ret = PTR_ERR(clk_table[i]); |
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goto unregister; |
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} |
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} |
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ret = of_clk_add_hw_provider(pdev->dev.of_node, of_clk_hw_onecell_get, |
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clk_data); |
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if (ret) { |
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dev_err(&pdev->dev, "failed to add clock provider\n"); |
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goto unregister; |
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} |
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#ifdef CONFIG_PM_SLEEP |
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register_syscore_ops(&s5pv210_audss_clk_syscore_ops); |
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#endif |
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return 0; |
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unregister: |
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for (i = 0; i < clk_data->num; i++) { |
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if (!IS_ERR(clk_table[i])) |
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clk_hw_unregister(clk_table[i]); |
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} |
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return ret; |
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} |
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static const struct of_device_id s5pv210_audss_clk_of_match[] = { |
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{ .compatible = "samsung,s5pv210-audss-clock", }, |
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{}, |
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}; |
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static struct platform_driver s5pv210_audss_clk_driver = { |
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.driver = { |
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.name = "s5pv210-audss-clk", |
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.suppress_bind_attrs = true, |
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.of_match_table = s5pv210_audss_clk_of_match, |
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}, |
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.probe = s5pv210_audss_clk_probe, |
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}; |
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static int __init s5pv210_audss_clk_init(void) |
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{ |
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return platform_driver_register(&s5pv210_audss_clk_driver); |
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} |
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core_initcall(s5pv210_audss_clk_init);
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