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109 lines
2.2 KiB
109 lines
2.2 KiB
// SPDX-License-Identifier: GPL-2.0-or-later |
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/* |
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* Copyright 2012 Freescale Semiconductor, Inc. |
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*/ |
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#include <linux/clk-provider.h> |
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#include <linux/delay.h> |
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#include <linux/err.h> |
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#include <linux/io.h> |
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#include <linux/slab.h> |
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#include "clk.h" |
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/** |
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* struct clk_pll - mxs pll clock |
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* @hw: clk_hw for the pll |
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* @base: base address of the pll |
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* @power: the shift of power bit |
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* @rate: the clock rate of the pll |
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* |
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* The mxs pll is a fixed rate clock with power and gate control, |
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* and the shift of gate bit is always 31. |
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*/ |
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struct clk_pll { |
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struct clk_hw hw; |
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void __iomem *base; |
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u8 power; |
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unsigned long rate; |
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}; |
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#define to_clk_pll(_hw) container_of(_hw, struct clk_pll, hw) |
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static int clk_pll_prepare(struct clk_hw *hw) |
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{ |
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struct clk_pll *pll = to_clk_pll(hw); |
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writel_relaxed(1 << pll->power, pll->base + SET); |
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udelay(10); |
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return 0; |
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} |
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static void clk_pll_unprepare(struct clk_hw *hw) |
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{ |
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struct clk_pll *pll = to_clk_pll(hw); |
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writel_relaxed(1 << pll->power, pll->base + CLR); |
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} |
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static int clk_pll_enable(struct clk_hw *hw) |
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{ |
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struct clk_pll *pll = to_clk_pll(hw); |
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writel_relaxed(1 << 31, pll->base + CLR); |
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return 0; |
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} |
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static void clk_pll_disable(struct clk_hw *hw) |
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{ |
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struct clk_pll *pll = to_clk_pll(hw); |
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writel_relaxed(1 << 31, pll->base + SET); |
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} |
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static unsigned long clk_pll_recalc_rate(struct clk_hw *hw, |
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unsigned long parent_rate) |
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{ |
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struct clk_pll *pll = to_clk_pll(hw); |
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return pll->rate; |
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} |
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static const struct clk_ops clk_pll_ops = { |
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.prepare = clk_pll_prepare, |
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.unprepare = clk_pll_unprepare, |
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.enable = clk_pll_enable, |
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.disable = clk_pll_disable, |
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.recalc_rate = clk_pll_recalc_rate, |
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}; |
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struct clk *mxs_clk_pll(const char *name, const char *parent_name, |
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void __iomem *base, u8 power, unsigned long rate) |
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{ |
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struct clk_pll *pll; |
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struct clk *clk; |
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struct clk_init_data init; |
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pll = kzalloc(sizeof(*pll), GFP_KERNEL); |
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if (!pll) |
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return ERR_PTR(-ENOMEM); |
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init.name = name; |
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init.ops = &clk_pll_ops; |
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init.flags = 0; |
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init.parent_names = (parent_name ? &parent_name: NULL); |
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init.num_parents = (parent_name ? 1 : 0); |
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pll->base = base; |
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pll->rate = rate; |
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pll->power = power; |
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pll->hw.init = &init; |
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clk = clk_register(NULL, &pll->hw); |
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if (IS_ERR(clk)) |
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kfree(pll); |
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return clk; |
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}
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