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149 lines
3.3 KiB
149 lines
3.3 KiB
// SPDX-License-Identifier: GPL-2.0+ |
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/* |
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* Amlogic Meson8 DDR clock controller |
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* |
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* Copyright (C) 2019 Martin Blumenstingl <[email protected]> |
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*/ |
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#include <dt-bindings/clock/meson8-ddr-clkc.h> |
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#include <linux/clk-provider.h> |
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#include <linux/platform_device.h> |
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#include "clk-regmap.h" |
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#include "clk-pll.h" |
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#define AM_DDR_PLL_CNTL 0x00 |
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#define AM_DDR_PLL_CNTL1 0x04 |
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#define AM_DDR_PLL_CNTL2 0x08 |
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#define AM_DDR_PLL_CNTL3 0x0c |
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#define AM_DDR_PLL_CNTL4 0x10 |
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#define AM_DDR_PLL_STS 0x14 |
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#define DDR_CLK_CNTL 0x18 |
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#define DDR_CLK_STS 0x1c |
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static struct clk_regmap meson8_ddr_pll_dco = { |
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.data = &(struct meson_clk_pll_data){ |
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.en = { |
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.reg_off = AM_DDR_PLL_CNTL, |
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.shift = 30, |
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.width = 1, |
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}, |
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.m = { |
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.reg_off = AM_DDR_PLL_CNTL, |
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.shift = 0, |
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.width = 9, |
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}, |
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.n = { |
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.reg_off = AM_DDR_PLL_CNTL, |
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.shift = 9, |
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.width = 5, |
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}, |
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.l = { |
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.reg_off = AM_DDR_PLL_CNTL, |
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.shift = 31, |
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.width = 1, |
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}, |
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.rst = { |
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.reg_off = AM_DDR_PLL_CNTL, |
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.shift = 29, |
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.width = 1, |
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}, |
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}, |
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.hw.init = &(struct clk_init_data){ |
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.name = "ddr_pll_dco", |
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.ops = &meson_clk_pll_ro_ops, |
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.parent_data = &(const struct clk_parent_data) { |
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.fw_name = "xtal", |
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}, |
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.num_parents = 1, |
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}, |
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}; |
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static struct clk_regmap meson8_ddr_pll = { |
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.data = &(struct clk_regmap_div_data){ |
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.offset = AM_DDR_PLL_CNTL, |
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.shift = 16, |
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.width = 2, |
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.flags = CLK_DIVIDER_POWER_OF_TWO, |
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}, |
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.hw.init = &(struct clk_init_data){ |
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.name = "ddr_pll", |
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.ops = &clk_regmap_divider_ro_ops, |
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.parent_hws = (const struct clk_hw *[]) { |
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&meson8_ddr_pll_dco.hw |
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}, |
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.num_parents = 1, |
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}, |
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}; |
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static struct clk_hw_onecell_data meson8_ddr_clk_hw_onecell_data = { |
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.hws = { |
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[DDR_CLKID_DDR_PLL_DCO] = &meson8_ddr_pll_dco.hw, |
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[DDR_CLKID_DDR_PLL] = &meson8_ddr_pll.hw, |
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}, |
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.num = 2, |
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}; |
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static struct clk_regmap *const meson8_ddr_clk_regmaps[] = { |
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&meson8_ddr_pll_dco, |
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&meson8_ddr_pll, |
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}; |
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static const struct regmap_config meson8_ddr_clkc_regmap_config = { |
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.reg_bits = 8, |
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.val_bits = 32, |
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.reg_stride = 4, |
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.max_register = DDR_CLK_STS, |
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}; |
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static int meson8_ddr_clkc_probe(struct platform_device *pdev) |
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{ |
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struct regmap *regmap; |
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void __iomem *base; |
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struct clk_hw *hw; |
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int ret, i; |
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base = devm_platform_ioremap_resource(pdev, 0); |
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if (IS_ERR(base)) |
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return PTR_ERR(base); |
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regmap = devm_regmap_init_mmio(&pdev->dev, base, |
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&meson8_ddr_clkc_regmap_config); |
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if (IS_ERR(regmap)) |
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return PTR_ERR(regmap); |
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/* Populate regmap */ |
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for (i = 0; i < ARRAY_SIZE(meson8_ddr_clk_regmaps); i++) |
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meson8_ddr_clk_regmaps[i]->map = regmap; |
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/* Register all clks */ |
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for (i = 0; i < meson8_ddr_clk_hw_onecell_data.num; i++) { |
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hw = meson8_ddr_clk_hw_onecell_data.hws[i]; |
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ret = devm_clk_hw_register(&pdev->dev, hw); |
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if (ret) { |
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dev_err(&pdev->dev, "Clock registration failed\n"); |
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return ret; |
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} |
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} |
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return devm_of_clk_add_hw_provider(&pdev->dev, of_clk_hw_onecell_get, |
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&meson8_ddr_clk_hw_onecell_data); |
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} |
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static const struct of_device_id meson8_ddr_clkc_match_table[] = { |
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{ .compatible = "amlogic,meson8-ddr-clkc" }, |
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{ .compatible = "amlogic,meson8b-ddr-clkc" }, |
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{ /* sentinel */ } |
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}; |
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static struct platform_driver meson8_ddr_clkc_driver = { |
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.probe = meson8_ddr_clkc_probe, |
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.driver = { |
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.name = "meson8-ddr-clkc", |
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.of_match_table = meson8_ddr_clkc_match_table, |
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}, |
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}; |
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builtin_platform_driver(meson8_ddr_clkc_driver);
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