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143 lines
4.8 KiB
143 lines
4.8 KiB
/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ |
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/* |
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* Copyright (c) 2018 BayLibre, SAS. |
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* Author: Jerome Brunet <[email protected]> |
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*/ |
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#ifndef __AXG_AUDIO_CLKC_H |
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#define __AXG_AUDIO_CLKC_H |
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/* |
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* Audio Clock register offsets |
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* |
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* Register offsets from the datasheet must be multiplied by 4 before |
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* to get the right offset |
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*/ |
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#define AUDIO_CLK_GATE_EN 0x000 |
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#define AUDIO_MCLK_A_CTRL 0x004 |
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#define AUDIO_MCLK_B_CTRL 0x008 |
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#define AUDIO_MCLK_C_CTRL 0x00C |
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#define AUDIO_MCLK_D_CTRL 0x010 |
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#define AUDIO_MCLK_E_CTRL 0x014 |
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#define AUDIO_MCLK_F_CTRL 0x018 |
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#define AUDIO_MST_PAD_CTRL0 0x01c |
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#define AUDIO_MST_PAD_CTRL1 0x020 |
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#define AUDIO_SW_RESET 0x024 |
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#define AUDIO_MST_A_SCLK_CTRL0 0x040 |
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#define AUDIO_MST_A_SCLK_CTRL1 0x044 |
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#define AUDIO_MST_B_SCLK_CTRL0 0x048 |
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#define AUDIO_MST_B_SCLK_CTRL1 0x04C |
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#define AUDIO_MST_C_SCLK_CTRL0 0x050 |
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#define AUDIO_MST_C_SCLK_CTRL1 0x054 |
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#define AUDIO_MST_D_SCLK_CTRL0 0x058 |
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#define AUDIO_MST_D_SCLK_CTRL1 0x05C |
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#define AUDIO_MST_E_SCLK_CTRL0 0x060 |
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#define AUDIO_MST_E_SCLK_CTRL1 0x064 |
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#define AUDIO_MST_F_SCLK_CTRL0 0x068 |
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#define AUDIO_MST_F_SCLK_CTRL1 0x06C |
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#define AUDIO_CLK_TDMIN_A_CTRL 0x080 |
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#define AUDIO_CLK_TDMIN_B_CTRL 0x084 |
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#define AUDIO_CLK_TDMIN_C_CTRL 0x088 |
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#define AUDIO_CLK_TDMIN_LB_CTRL 0x08C |
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#define AUDIO_CLK_TDMOUT_A_CTRL 0x090 |
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#define AUDIO_CLK_TDMOUT_B_CTRL 0x094 |
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#define AUDIO_CLK_TDMOUT_C_CTRL 0x098 |
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#define AUDIO_CLK_SPDIFIN_CTRL 0x09C |
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#define AUDIO_CLK_SPDIFOUT_CTRL 0x0A0 |
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#define AUDIO_CLK_RESAMPLE_CTRL 0x0A4 |
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#define AUDIO_CLK_LOCKER_CTRL 0x0A8 |
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#define AUDIO_CLK_PDMIN_CTRL0 0x0AC |
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#define AUDIO_CLK_PDMIN_CTRL1 0x0B0 |
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#define AUDIO_CLK_SPDIFOUT_B_CTRL 0x0B4 |
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/* SM1 introduce new register and some shifts :( */ |
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#define AUDIO_CLK_GATE_EN1 0x004 |
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#define AUDIO_SM1_MCLK_A_CTRL 0x008 |
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#define AUDIO_SM1_MCLK_B_CTRL 0x00C |
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#define AUDIO_SM1_MCLK_C_CTRL 0x010 |
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#define AUDIO_SM1_MCLK_D_CTRL 0x014 |
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#define AUDIO_SM1_MCLK_E_CTRL 0x018 |
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#define AUDIO_SM1_MCLK_F_CTRL 0x01C |
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#define AUDIO_SM1_MST_PAD_CTRL0 0x020 |
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#define AUDIO_SM1_MST_PAD_CTRL1 0x024 |
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#define AUDIO_SM1_SW_RESET0 0x028 |
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#define AUDIO_SM1_SW_RESET1 0x02C |
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#define AUDIO_CLK81_CTRL 0x030 |
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#define AUDIO_CLK81_EN 0x034 |
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/* |
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* CLKID index values |
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* These indices are entirely contrived and do not map onto the hardware. |
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*/ |
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#define AUD_CLKID_MST_A_MCLK_SEL 59 |
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#define AUD_CLKID_MST_B_MCLK_SEL 60 |
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#define AUD_CLKID_MST_C_MCLK_SEL 61 |
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#define AUD_CLKID_MST_D_MCLK_SEL 62 |
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#define AUD_CLKID_MST_E_MCLK_SEL 63 |
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#define AUD_CLKID_MST_F_MCLK_SEL 64 |
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#define AUD_CLKID_MST_A_MCLK_DIV 65 |
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#define AUD_CLKID_MST_B_MCLK_DIV 66 |
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#define AUD_CLKID_MST_C_MCLK_DIV 67 |
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#define AUD_CLKID_MST_D_MCLK_DIV 68 |
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#define AUD_CLKID_MST_E_MCLK_DIV 69 |
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#define AUD_CLKID_MST_F_MCLK_DIV 70 |
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#define AUD_CLKID_SPDIFOUT_CLK_SEL 71 |
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#define AUD_CLKID_SPDIFOUT_CLK_DIV 72 |
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#define AUD_CLKID_SPDIFIN_CLK_SEL 73 |
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#define AUD_CLKID_SPDIFIN_CLK_DIV 74 |
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#define AUD_CLKID_PDM_DCLK_SEL 75 |
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#define AUD_CLKID_PDM_DCLK_DIV 76 |
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#define AUD_CLKID_PDM_SYSCLK_SEL 77 |
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#define AUD_CLKID_PDM_SYSCLK_DIV 78 |
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#define AUD_CLKID_MST_A_SCLK_PRE_EN 92 |
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#define AUD_CLKID_MST_B_SCLK_PRE_EN 93 |
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#define AUD_CLKID_MST_C_SCLK_PRE_EN 94 |
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#define AUD_CLKID_MST_D_SCLK_PRE_EN 95 |
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#define AUD_CLKID_MST_E_SCLK_PRE_EN 96 |
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#define AUD_CLKID_MST_F_SCLK_PRE_EN 97 |
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#define AUD_CLKID_MST_A_SCLK_DIV 98 |
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#define AUD_CLKID_MST_B_SCLK_DIV 99 |
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#define AUD_CLKID_MST_C_SCLK_DIV 100 |
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#define AUD_CLKID_MST_D_SCLK_DIV 101 |
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#define AUD_CLKID_MST_E_SCLK_DIV 102 |
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#define AUD_CLKID_MST_F_SCLK_DIV 103 |
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#define AUD_CLKID_MST_A_SCLK_POST_EN 104 |
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#define AUD_CLKID_MST_B_SCLK_POST_EN 105 |
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#define AUD_CLKID_MST_C_SCLK_POST_EN 106 |
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#define AUD_CLKID_MST_D_SCLK_POST_EN 107 |
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#define AUD_CLKID_MST_E_SCLK_POST_EN 108 |
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#define AUD_CLKID_MST_F_SCLK_POST_EN 109 |
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#define AUD_CLKID_MST_A_LRCLK_DIV 110 |
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#define AUD_CLKID_MST_B_LRCLK_DIV 111 |
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#define AUD_CLKID_MST_C_LRCLK_DIV 112 |
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#define AUD_CLKID_MST_D_LRCLK_DIV 113 |
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#define AUD_CLKID_MST_E_LRCLK_DIV 114 |
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#define AUD_CLKID_MST_F_LRCLK_DIV 115 |
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#define AUD_CLKID_TDMIN_A_SCLK_PRE_EN 137 |
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#define AUD_CLKID_TDMIN_B_SCLK_PRE_EN 138 |
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#define AUD_CLKID_TDMIN_C_SCLK_PRE_EN 139 |
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#define AUD_CLKID_TDMIN_LB_SCLK_PRE_EN 140 |
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#define AUD_CLKID_TDMOUT_A_SCLK_PRE_EN 141 |
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#define AUD_CLKID_TDMOUT_B_SCLK_PRE_EN 142 |
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#define AUD_CLKID_TDMOUT_C_SCLK_PRE_EN 143 |
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#define AUD_CLKID_TDMIN_A_SCLK_POST_EN 144 |
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#define AUD_CLKID_TDMIN_B_SCLK_POST_EN 145 |
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#define AUD_CLKID_TDMIN_C_SCLK_POST_EN 146 |
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#define AUD_CLKID_TDMIN_LB_SCLK_POST_EN 147 |
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#define AUD_CLKID_TDMOUT_A_SCLK_POST_EN 148 |
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#define AUD_CLKID_TDMOUT_B_SCLK_POST_EN 149 |
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#define AUD_CLKID_TDMOUT_C_SCLK_POST_EN 150 |
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#define AUD_CLKID_SPDIFOUT_B_CLK_SEL 153 |
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#define AUD_CLKID_SPDIFOUT_B_CLK_DIV 154 |
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#define AUD_CLKID_CLK81_EN 173 |
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#define AUD_CLKID_SYSCLK_A_DIV 174 |
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#define AUD_CLKID_SYSCLK_B_DIV 175 |
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#define AUD_CLKID_SYSCLK_A_EN 176 |
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#define AUD_CLKID_SYSCLK_B_EN 177 |
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/* include the CLKIDs which are part of the DT bindings */ |
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#include <dt-bindings/clock/axg-audio-clkc.h> |
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#define NR_CLKS 178 |
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#endif /*__AXG_AUDIO_CLKC_H */
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