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113 lines
2.8 KiB
113 lines
2.8 KiB
// SPDX-License-Identifier: GPL-2.0-or-later |
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/* |
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* Hisilicon clock separated gate driver |
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* |
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* Copyright (c) 2012-2013 Hisilicon Limited. |
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* Copyright (c) 2012-2013 Linaro Limited. |
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* |
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* Author: Haojian Zhuang <[email protected]> |
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* Xin Li <[email protected]> |
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*/ |
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#include <linux/kernel.h> |
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#include <linux/clk-provider.h> |
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#include <linux/io.h> |
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#include <linux/slab.h> |
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#include "clk.h" |
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/* clock separated gate register offset */ |
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#define CLKGATE_SEPERATED_ENABLE 0x0 |
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#define CLKGATE_SEPERATED_DISABLE 0x4 |
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#define CLKGATE_SEPERATED_STATUS 0x8 |
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struct clkgate_separated { |
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struct clk_hw hw; |
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void __iomem *enable; /* enable register */ |
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u8 bit_idx; /* bits in enable/disable register */ |
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u8 flags; |
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spinlock_t *lock; |
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}; |
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static int clkgate_separated_enable(struct clk_hw *hw) |
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{ |
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struct clkgate_separated *sclk; |
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unsigned long flags = 0; |
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u32 reg; |
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sclk = container_of(hw, struct clkgate_separated, hw); |
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if (sclk->lock) |
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spin_lock_irqsave(sclk->lock, flags); |
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reg = BIT(sclk->bit_idx); |
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writel_relaxed(reg, sclk->enable); |
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readl_relaxed(sclk->enable + CLKGATE_SEPERATED_STATUS); |
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if (sclk->lock) |
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spin_unlock_irqrestore(sclk->lock, flags); |
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return 0; |
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} |
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static void clkgate_separated_disable(struct clk_hw *hw) |
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{ |
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struct clkgate_separated *sclk; |
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unsigned long flags = 0; |
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u32 reg; |
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sclk = container_of(hw, struct clkgate_separated, hw); |
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if (sclk->lock) |
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spin_lock_irqsave(sclk->lock, flags); |
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reg = BIT(sclk->bit_idx); |
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writel_relaxed(reg, sclk->enable + CLKGATE_SEPERATED_DISABLE); |
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readl_relaxed(sclk->enable + CLKGATE_SEPERATED_STATUS); |
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if (sclk->lock) |
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spin_unlock_irqrestore(sclk->lock, flags); |
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} |
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static int clkgate_separated_is_enabled(struct clk_hw *hw) |
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{ |
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struct clkgate_separated *sclk; |
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u32 reg; |
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sclk = container_of(hw, struct clkgate_separated, hw); |
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reg = readl_relaxed(sclk->enable + CLKGATE_SEPERATED_STATUS); |
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reg &= BIT(sclk->bit_idx); |
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return reg ? 1 : 0; |
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} |
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static const struct clk_ops clkgate_separated_ops = { |
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.enable = clkgate_separated_enable, |
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.disable = clkgate_separated_disable, |
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.is_enabled = clkgate_separated_is_enabled, |
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}; |
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struct clk *hisi_register_clkgate_sep(struct device *dev, const char *name, |
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const char *parent_name, |
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unsigned long flags, |
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void __iomem *reg, u8 bit_idx, |
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u8 clk_gate_flags, spinlock_t *lock) |
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{ |
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struct clkgate_separated *sclk; |
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struct clk *clk; |
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struct clk_init_data init; |
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sclk = kzalloc(sizeof(*sclk), GFP_KERNEL); |
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if (!sclk) |
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return ERR_PTR(-ENOMEM); |
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init.name = name; |
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init.ops = &clkgate_separated_ops; |
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init.flags = flags; |
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init.parent_names = (parent_name ? &parent_name : NULL); |
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init.num_parents = (parent_name ? 1 : 0); |
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sclk->enable = reg + CLKGATE_SEPERATED_ENABLE; |
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sclk->bit_idx = bit_idx; |
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sclk->flags = clk_gate_flags; |
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sclk->hw.init = &init; |
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sclk->lock = lock; |
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clk = clk_register(dev, &sclk->hw); |
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if (IS_ERR(clk)) |
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kfree(sclk); |
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return clk; |
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}
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