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154 lines
3.6 KiB
154 lines
3.6 KiB
// SPDX-License-Identifier: GPL-2.0-only |
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/* |
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* Hisilicon hi6220 SoC divider clock driver |
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* |
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* Copyright (c) 2015 Hisilicon Limited. |
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* |
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* Author: Bintian Wang <[email protected]> |
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*/ |
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#include <linux/kernel.h> |
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#include <linux/clk-provider.h> |
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#include <linux/slab.h> |
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#include <linux/io.h> |
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#include <linux/err.h> |
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#include <linux/spinlock.h> |
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#include "clk.h" |
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#define div_mask(width) ((1 << (width)) - 1) |
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/** |
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* struct hi6220_clk_divider - divider clock for hi6220 |
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* |
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* @hw: handle between common and hardware-specific interfaces |
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* @reg: register containing divider |
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* @shift: shift to the divider bit field |
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* @width: width of the divider bit field |
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* @mask: mask for setting divider rate |
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* @table: the div table that the divider supports |
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* @lock: register lock |
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*/ |
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struct hi6220_clk_divider { |
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struct clk_hw hw; |
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void __iomem *reg; |
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u8 shift; |
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u8 width; |
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u32 mask; |
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const struct clk_div_table *table; |
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spinlock_t *lock; |
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}; |
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#define to_hi6220_clk_divider(_hw) \ |
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container_of(_hw, struct hi6220_clk_divider, hw) |
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static unsigned long hi6220_clkdiv_recalc_rate(struct clk_hw *hw, |
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unsigned long parent_rate) |
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{ |
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unsigned int val; |
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struct hi6220_clk_divider *dclk = to_hi6220_clk_divider(hw); |
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val = readl_relaxed(dclk->reg) >> dclk->shift; |
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val &= div_mask(dclk->width); |
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return divider_recalc_rate(hw, parent_rate, val, dclk->table, |
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CLK_DIVIDER_ROUND_CLOSEST, dclk->width); |
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} |
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static long hi6220_clkdiv_round_rate(struct clk_hw *hw, unsigned long rate, |
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unsigned long *prate) |
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{ |
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struct hi6220_clk_divider *dclk = to_hi6220_clk_divider(hw); |
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return divider_round_rate(hw, rate, prate, dclk->table, |
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dclk->width, CLK_DIVIDER_ROUND_CLOSEST); |
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} |
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static int hi6220_clkdiv_set_rate(struct clk_hw *hw, unsigned long rate, |
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unsigned long parent_rate) |
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{ |
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int value; |
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unsigned long flags = 0; |
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u32 data; |
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struct hi6220_clk_divider *dclk = to_hi6220_clk_divider(hw); |
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value = divider_get_val(rate, parent_rate, dclk->table, |
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dclk->width, CLK_DIVIDER_ROUND_CLOSEST); |
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if (dclk->lock) |
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spin_lock_irqsave(dclk->lock, flags); |
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data = readl_relaxed(dclk->reg); |
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data &= ~(div_mask(dclk->width) << dclk->shift); |
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data |= value << dclk->shift; |
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data |= dclk->mask; |
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writel_relaxed(data, dclk->reg); |
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if (dclk->lock) |
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spin_unlock_irqrestore(dclk->lock, flags); |
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return 0; |
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} |
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static const struct clk_ops hi6220_clkdiv_ops = { |
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.recalc_rate = hi6220_clkdiv_recalc_rate, |
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.round_rate = hi6220_clkdiv_round_rate, |
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.set_rate = hi6220_clkdiv_set_rate, |
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}; |
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struct clk *hi6220_register_clkdiv(struct device *dev, const char *name, |
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const char *parent_name, unsigned long flags, void __iomem *reg, |
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u8 shift, u8 width, u32 mask_bit, spinlock_t *lock) |
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{ |
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struct hi6220_clk_divider *div; |
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struct clk *clk; |
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struct clk_init_data init; |
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struct clk_div_table *table; |
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u32 max_div, min_div; |
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int i; |
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/* allocate the divider */ |
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div = kzalloc(sizeof(*div), GFP_KERNEL); |
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if (!div) |
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return ERR_PTR(-ENOMEM); |
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/* Init the divider table */ |
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max_div = div_mask(width) + 1; |
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min_div = 1; |
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table = kcalloc(max_div + 1, sizeof(*table), GFP_KERNEL); |
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if (!table) { |
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kfree(div); |
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return ERR_PTR(-ENOMEM); |
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} |
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for (i = 0; i < max_div; i++) { |
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table[i].div = min_div + i; |
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table[i].val = table[i].div - 1; |
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} |
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init.name = name; |
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init.ops = &hi6220_clkdiv_ops; |
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init.flags = flags; |
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init.parent_names = parent_name ? &parent_name : NULL; |
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init.num_parents = parent_name ? 1 : 0; |
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/* struct hi6220_clk_divider assignments */ |
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div->reg = reg; |
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div->shift = shift; |
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div->width = width; |
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div->mask = mask_bit ? BIT(mask_bit) : 0; |
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div->lock = lock; |
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div->hw.init = &init; |
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div->table = table; |
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/* register the clock */ |
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clk = clk_register(dev, &div->hw); |
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if (IS_ERR(clk)) { |
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kfree(table); |
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kfree(div); |
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} |
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return clk; |
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}
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