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398 lines
9.3 KiB
398 lines
9.3 KiB
// SPDX-License-Identifier: GPL-2.0-or-later |
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/* |
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* WM831x clock control |
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* |
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* Copyright 2011-2 Wolfson Microelectronics PLC. |
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* |
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* Author: Mark Brown <[email protected]> |
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*/ |
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#include <linux/clk-provider.h> |
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#include <linux/delay.h> |
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#include <linux/module.h> |
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#include <linux/slab.h> |
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#include <linux/platform_device.h> |
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#include <linux/mfd/wm831x/core.h> |
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struct wm831x_clk { |
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struct wm831x *wm831x; |
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struct clk_hw xtal_hw; |
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struct clk_hw fll_hw; |
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struct clk_hw clkout_hw; |
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bool xtal_ena; |
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}; |
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static int wm831x_xtal_is_prepared(struct clk_hw *hw) |
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{ |
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struct wm831x_clk *clkdata = container_of(hw, struct wm831x_clk, |
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xtal_hw); |
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return clkdata->xtal_ena; |
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} |
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static unsigned long wm831x_xtal_recalc_rate(struct clk_hw *hw, |
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unsigned long parent_rate) |
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{ |
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struct wm831x_clk *clkdata = container_of(hw, struct wm831x_clk, |
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xtal_hw); |
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if (clkdata->xtal_ena) |
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return 32768; |
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else |
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return 0; |
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} |
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static const struct clk_ops wm831x_xtal_ops = { |
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.is_prepared = wm831x_xtal_is_prepared, |
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.recalc_rate = wm831x_xtal_recalc_rate, |
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}; |
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static const struct clk_init_data wm831x_xtal_init = { |
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.name = "xtal", |
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.ops = &wm831x_xtal_ops, |
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}; |
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static const unsigned long wm831x_fll_auto_rates[] = { |
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2048000, |
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11289600, |
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12000000, |
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12288000, |
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19200000, |
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22579600, |
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24000000, |
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24576000, |
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}; |
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static int wm831x_fll_is_prepared(struct clk_hw *hw) |
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{ |
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struct wm831x_clk *clkdata = container_of(hw, struct wm831x_clk, |
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fll_hw); |
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struct wm831x *wm831x = clkdata->wm831x; |
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int ret; |
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ret = wm831x_reg_read(wm831x, WM831X_FLL_CONTROL_1); |
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if (ret < 0) { |
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dev_err(wm831x->dev, "Unable to read FLL_CONTROL_1: %d\n", |
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ret); |
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return true; |
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} |
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return (ret & WM831X_FLL_ENA) != 0; |
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} |
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static int wm831x_fll_prepare(struct clk_hw *hw) |
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{ |
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struct wm831x_clk *clkdata = container_of(hw, struct wm831x_clk, |
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fll_hw); |
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struct wm831x *wm831x = clkdata->wm831x; |
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int ret; |
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ret = wm831x_set_bits(wm831x, WM831X_FLL_CONTROL_1, |
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WM831X_FLL_ENA, WM831X_FLL_ENA); |
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if (ret != 0) |
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dev_crit(wm831x->dev, "Failed to enable FLL: %d\n", ret); |
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/* wait 2-3 ms for new frequency taking effect */ |
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usleep_range(2000, 3000); |
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return ret; |
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} |
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static void wm831x_fll_unprepare(struct clk_hw *hw) |
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{ |
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struct wm831x_clk *clkdata = container_of(hw, struct wm831x_clk, |
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fll_hw); |
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struct wm831x *wm831x = clkdata->wm831x; |
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int ret; |
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ret = wm831x_set_bits(wm831x, WM831X_FLL_CONTROL_1, WM831X_FLL_ENA, 0); |
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if (ret != 0) |
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dev_crit(wm831x->dev, "Failed to disable FLL: %d\n", ret); |
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} |
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static unsigned long wm831x_fll_recalc_rate(struct clk_hw *hw, |
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unsigned long parent_rate) |
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{ |
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struct wm831x_clk *clkdata = container_of(hw, struct wm831x_clk, |
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fll_hw); |
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struct wm831x *wm831x = clkdata->wm831x; |
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int ret; |
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ret = wm831x_reg_read(wm831x, WM831X_CLOCK_CONTROL_2); |
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if (ret < 0) { |
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dev_err(wm831x->dev, "Unable to read CLOCK_CONTROL_2: %d\n", |
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ret); |
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return 0; |
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} |
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if (ret & WM831X_FLL_AUTO) |
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return wm831x_fll_auto_rates[ret & WM831X_FLL_AUTO_FREQ_MASK]; |
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dev_err(wm831x->dev, "FLL only supported in AUTO mode\n"); |
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return 0; |
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} |
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static long wm831x_fll_round_rate(struct clk_hw *hw, unsigned long rate, |
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unsigned long *unused) |
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{ |
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int best = 0; |
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int i; |
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for (i = 0; i < ARRAY_SIZE(wm831x_fll_auto_rates); i++) |
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if (abs(wm831x_fll_auto_rates[i] - rate) < |
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abs(wm831x_fll_auto_rates[best] - rate)) |
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best = i; |
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return wm831x_fll_auto_rates[best]; |
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} |
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static int wm831x_fll_set_rate(struct clk_hw *hw, unsigned long rate, |
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unsigned long parent_rate) |
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{ |
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struct wm831x_clk *clkdata = container_of(hw, struct wm831x_clk, |
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fll_hw); |
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struct wm831x *wm831x = clkdata->wm831x; |
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int i; |
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for (i = 0; i < ARRAY_SIZE(wm831x_fll_auto_rates); i++) |
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if (wm831x_fll_auto_rates[i] == rate) |
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break; |
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if (i == ARRAY_SIZE(wm831x_fll_auto_rates)) |
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return -EINVAL; |
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if (wm831x_fll_is_prepared(hw)) |
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return -EPERM; |
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return wm831x_set_bits(wm831x, WM831X_CLOCK_CONTROL_2, |
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WM831X_FLL_AUTO_FREQ_MASK, i); |
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} |
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static const char *wm831x_fll_parents[] = { |
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"xtal", |
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"clkin", |
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}; |
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static u8 wm831x_fll_get_parent(struct clk_hw *hw) |
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{ |
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struct wm831x_clk *clkdata = container_of(hw, struct wm831x_clk, |
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fll_hw); |
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struct wm831x *wm831x = clkdata->wm831x; |
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int ret; |
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/* AUTO mode is always clocked from the crystal */ |
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ret = wm831x_reg_read(wm831x, WM831X_CLOCK_CONTROL_2); |
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if (ret < 0) { |
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dev_err(wm831x->dev, "Unable to read CLOCK_CONTROL_2: %d\n", |
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ret); |
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return 0; |
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} |
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if (ret & WM831X_FLL_AUTO) |
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return 0; |
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ret = wm831x_reg_read(wm831x, WM831X_FLL_CONTROL_5); |
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if (ret < 0) { |
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dev_err(wm831x->dev, "Unable to read FLL_CONTROL_5: %d\n", |
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ret); |
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return 0; |
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} |
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switch (ret & WM831X_FLL_CLK_SRC_MASK) { |
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case 0: |
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return 0; |
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case 1: |
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return 1; |
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default: |
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dev_err(wm831x->dev, "Unsupported FLL clock source %d\n", |
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ret & WM831X_FLL_CLK_SRC_MASK); |
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return 0; |
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} |
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} |
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static const struct clk_ops wm831x_fll_ops = { |
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.is_prepared = wm831x_fll_is_prepared, |
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.prepare = wm831x_fll_prepare, |
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.unprepare = wm831x_fll_unprepare, |
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.round_rate = wm831x_fll_round_rate, |
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.recalc_rate = wm831x_fll_recalc_rate, |
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.set_rate = wm831x_fll_set_rate, |
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.get_parent = wm831x_fll_get_parent, |
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}; |
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static const struct clk_init_data wm831x_fll_init = { |
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.name = "fll", |
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.ops = &wm831x_fll_ops, |
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.parent_names = wm831x_fll_parents, |
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.num_parents = ARRAY_SIZE(wm831x_fll_parents), |
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.flags = CLK_SET_RATE_GATE, |
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}; |
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static int wm831x_clkout_is_prepared(struct clk_hw *hw) |
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{ |
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struct wm831x_clk *clkdata = container_of(hw, struct wm831x_clk, |
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clkout_hw); |
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struct wm831x *wm831x = clkdata->wm831x; |
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int ret; |
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ret = wm831x_reg_read(wm831x, WM831X_CLOCK_CONTROL_1); |
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if (ret < 0) { |
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dev_err(wm831x->dev, "Unable to read CLOCK_CONTROL_1: %d\n", |
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ret); |
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return false; |
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} |
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return (ret & WM831X_CLKOUT_ENA) != 0; |
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} |
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static int wm831x_clkout_prepare(struct clk_hw *hw) |
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{ |
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struct wm831x_clk *clkdata = container_of(hw, struct wm831x_clk, |
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clkout_hw); |
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struct wm831x *wm831x = clkdata->wm831x; |
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int ret; |
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ret = wm831x_reg_unlock(wm831x); |
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if (ret != 0) { |
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dev_crit(wm831x->dev, "Failed to lock registers: %d\n", ret); |
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return ret; |
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} |
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ret = wm831x_set_bits(wm831x, WM831X_CLOCK_CONTROL_1, |
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WM831X_CLKOUT_ENA, WM831X_CLKOUT_ENA); |
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if (ret != 0) |
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dev_crit(wm831x->dev, "Failed to enable CLKOUT: %d\n", ret); |
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wm831x_reg_lock(wm831x); |
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return ret; |
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} |
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static void wm831x_clkout_unprepare(struct clk_hw *hw) |
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{ |
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struct wm831x_clk *clkdata = container_of(hw, struct wm831x_clk, |
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clkout_hw); |
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struct wm831x *wm831x = clkdata->wm831x; |
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int ret; |
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ret = wm831x_reg_unlock(wm831x); |
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if (ret != 0) { |
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dev_crit(wm831x->dev, "Failed to lock registers: %d\n", ret); |
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return; |
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} |
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ret = wm831x_set_bits(wm831x, WM831X_CLOCK_CONTROL_1, |
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WM831X_CLKOUT_ENA, 0); |
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if (ret != 0) |
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dev_crit(wm831x->dev, "Failed to disable CLKOUT: %d\n", ret); |
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wm831x_reg_lock(wm831x); |
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} |
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static const char *wm831x_clkout_parents[] = { |
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"fll", |
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"xtal", |
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}; |
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static u8 wm831x_clkout_get_parent(struct clk_hw *hw) |
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{ |
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struct wm831x_clk *clkdata = container_of(hw, struct wm831x_clk, |
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clkout_hw); |
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struct wm831x *wm831x = clkdata->wm831x; |
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int ret; |
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ret = wm831x_reg_read(wm831x, WM831X_CLOCK_CONTROL_1); |
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if (ret < 0) { |
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dev_err(wm831x->dev, "Unable to read CLOCK_CONTROL_1: %d\n", |
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ret); |
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return 0; |
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} |
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if (ret & WM831X_CLKOUT_SRC) |
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return 1; |
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else |
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return 0; |
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} |
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static int wm831x_clkout_set_parent(struct clk_hw *hw, u8 parent) |
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{ |
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struct wm831x_clk *clkdata = container_of(hw, struct wm831x_clk, |
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clkout_hw); |
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struct wm831x *wm831x = clkdata->wm831x; |
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return wm831x_set_bits(wm831x, WM831X_CLOCK_CONTROL_1, |
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WM831X_CLKOUT_SRC, |
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parent << WM831X_CLKOUT_SRC_SHIFT); |
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} |
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static const struct clk_ops wm831x_clkout_ops = { |
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.is_prepared = wm831x_clkout_is_prepared, |
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.prepare = wm831x_clkout_prepare, |
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.unprepare = wm831x_clkout_unprepare, |
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.get_parent = wm831x_clkout_get_parent, |
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.set_parent = wm831x_clkout_set_parent, |
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}; |
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static const struct clk_init_data wm831x_clkout_init = { |
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.name = "clkout", |
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.ops = &wm831x_clkout_ops, |
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.parent_names = wm831x_clkout_parents, |
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.num_parents = ARRAY_SIZE(wm831x_clkout_parents), |
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.flags = CLK_SET_RATE_PARENT, |
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}; |
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static int wm831x_clk_probe(struct platform_device *pdev) |
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{ |
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struct wm831x *wm831x = dev_get_drvdata(pdev->dev.parent); |
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struct wm831x_clk *clkdata; |
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int ret; |
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clkdata = devm_kzalloc(&pdev->dev, sizeof(*clkdata), GFP_KERNEL); |
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if (!clkdata) |
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return -ENOMEM; |
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clkdata->wm831x = wm831x; |
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/* XTAL_ENA can only be set via OTP/InstantConfig so just read once */ |
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ret = wm831x_reg_read(wm831x, WM831X_CLOCK_CONTROL_2); |
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if (ret < 0) { |
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dev_err(wm831x->dev, "Unable to read CLOCK_CONTROL_2: %d\n", |
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ret); |
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return ret; |
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} |
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clkdata->xtal_ena = ret & WM831X_XTAL_ENA; |
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clkdata->xtal_hw.init = &wm831x_xtal_init; |
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ret = devm_clk_hw_register(&pdev->dev, &clkdata->xtal_hw); |
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if (ret) |
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return ret; |
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clkdata->fll_hw.init = &wm831x_fll_init; |
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ret = devm_clk_hw_register(&pdev->dev, &clkdata->fll_hw); |
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if (ret) |
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return ret; |
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clkdata->clkout_hw.init = &wm831x_clkout_init; |
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ret = devm_clk_hw_register(&pdev->dev, &clkdata->clkout_hw); |
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if (ret) |
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return ret; |
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platform_set_drvdata(pdev, clkdata); |
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return 0; |
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} |
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static struct platform_driver wm831x_clk_driver = { |
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.probe = wm831x_clk_probe, |
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.driver = { |
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.name = "wm831x-clk", |
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}, |
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}; |
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module_platform_driver(wm831x_clk_driver); |
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/* Module information */ |
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MODULE_AUTHOR("Mark Brown <[email protected]>"); |
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MODULE_DESCRIPTION("WM831x clock driver"); |
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MODULE_LICENSE("GPL"); |
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MODULE_ALIAS("platform:wm831x-clk");
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