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422 lines
10 KiB
422 lines
10 KiB
// SPDX-License-Identifier: GPL-2.0-only |
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/* |
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* HP Quicksilver AGP GART routines |
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* |
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* Copyright (c) 2006, Kyle McMartin <[email protected]> |
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* |
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* Based on drivers/char/agpgart/hp-agp.c which is |
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* (c) Copyright 2002, 2003 Hewlett-Packard Development Company, L.P. |
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* Bjorn Helgaas <[email protected]> |
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*/ |
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#include <linux/module.h> |
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#include <linux/pci.h> |
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#include <linux/init.h> |
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#include <linux/klist.h> |
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#include <linux/agp_backend.h> |
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#include <linux/log2.h> |
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#include <linux/slab.h> |
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#include <asm/parisc-device.h> |
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#include <asm/ropes.h> |
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#include "agp.h" |
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#define DRVNAME "quicksilver" |
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#define DRVPFX DRVNAME ": " |
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#define AGP8X_MODE_BIT 3 |
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#define AGP8X_MODE (1 << AGP8X_MODE_BIT) |
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static unsigned long |
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parisc_agp_mask_memory(struct agp_bridge_data *bridge, dma_addr_t addr, |
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int type); |
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static struct _parisc_agp_info { |
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void __iomem *ioc_regs; |
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void __iomem *lba_regs; |
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int lba_cap_offset; |
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u64 *gatt; |
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u64 gatt_entries; |
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u64 gart_base; |
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u64 gart_size; |
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int io_page_size; |
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int io_pages_per_kpage; |
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} parisc_agp_info; |
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static struct gatt_mask parisc_agp_masks[] = |
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{ |
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{ |
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.mask = SBA_PDIR_VALID_BIT, |
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.type = 0 |
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} |
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}; |
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static struct aper_size_info_fixed parisc_agp_sizes[] = |
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{ |
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{0, 0, 0}, /* filled in by parisc_agp_fetch_size() */ |
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}; |
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static int |
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parisc_agp_fetch_size(void) |
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{ |
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int size; |
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size = parisc_agp_info.gart_size / MB(1); |
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parisc_agp_sizes[0].size = size; |
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agp_bridge->current_size = (void *) &parisc_agp_sizes[0]; |
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return size; |
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} |
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static int |
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parisc_agp_configure(void) |
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{ |
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struct _parisc_agp_info *info = &parisc_agp_info; |
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agp_bridge->gart_bus_addr = info->gart_base; |
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agp_bridge->capndx = info->lba_cap_offset; |
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agp_bridge->mode = readl(info->lba_regs+info->lba_cap_offset+PCI_AGP_STATUS); |
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return 0; |
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} |
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static void |
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parisc_agp_tlbflush(struct agp_memory *mem) |
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{ |
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struct _parisc_agp_info *info = &parisc_agp_info; |
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writeq(info->gart_base | ilog2(info->gart_size), info->ioc_regs+IOC_PCOM); |
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readq(info->ioc_regs+IOC_PCOM); /* flush */ |
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} |
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static int |
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parisc_agp_create_gatt_table(struct agp_bridge_data *bridge) |
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{ |
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struct _parisc_agp_info *info = &parisc_agp_info; |
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int i; |
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for (i = 0; i < info->gatt_entries; i++) { |
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info->gatt[i] = (unsigned long)agp_bridge->scratch_page; |
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} |
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return 0; |
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} |
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static int |
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parisc_agp_free_gatt_table(struct agp_bridge_data *bridge) |
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{ |
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struct _parisc_agp_info *info = &parisc_agp_info; |
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info->gatt[0] = SBA_AGPGART_COOKIE; |
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return 0; |
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} |
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static int |
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parisc_agp_insert_memory(struct agp_memory *mem, off_t pg_start, int type) |
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{ |
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struct _parisc_agp_info *info = &parisc_agp_info; |
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int i, k; |
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off_t j, io_pg_start; |
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int io_pg_count; |
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if (type != mem->type || |
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agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type)) { |
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return -EINVAL; |
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} |
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io_pg_start = info->io_pages_per_kpage * pg_start; |
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io_pg_count = info->io_pages_per_kpage * mem->page_count; |
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if ((io_pg_start + io_pg_count) > info->gatt_entries) { |
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return -EINVAL; |
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} |
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j = io_pg_start; |
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while (j < (io_pg_start + io_pg_count)) { |
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if (info->gatt[j]) |
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return -EBUSY; |
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j++; |
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} |
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if (!mem->is_flushed) { |
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global_cache_flush(); |
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mem->is_flushed = true; |
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} |
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for (i = 0, j = io_pg_start; i < mem->page_count; i++) { |
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unsigned long paddr; |
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paddr = page_to_phys(mem->pages[i]); |
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for (k = 0; |
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k < info->io_pages_per_kpage; |
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k++, j++, paddr += info->io_page_size) { |
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info->gatt[j] = |
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parisc_agp_mask_memory(agp_bridge, |
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paddr, type); |
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} |
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} |
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agp_bridge->driver->tlb_flush(mem); |
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return 0; |
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} |
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static int |
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parisc_agp_remove_memory(struct agp_memory *mem, off_t pg_start, int type) |
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{ |
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struct _parisc_agp_info *info = &parisc_agp_info; |
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int i, io_pg_start, io_pg_count; |
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if (type != mem->type || |
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agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type)) { |
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return -EINVAL; |
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} |
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io_pg_start = info->io_pages_per_kpage * pg_start; |
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io_pg_count = info->io_pages_per_kpage * mem->page_count; |
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for (i = io_pg_start; i < io_pg_count + io_pg_start; i++) { |
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info->gatt[i] = agp_bridge->scratch_page; |
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} |
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agp_bridge->driver->tlb_flush(mem); |
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return 0; |
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} |
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static unsigned long |
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parisc_agp_mask_memory(struct agp_bridge_data *bridge, dma_addr_t addr, |
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int type) |
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{ |
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return SBA_PDIR_VALID_BIT | addr; |
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} |
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static void |
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parisc_agp_enable(struct agp_bridge_data *bridge, u32 mode) |
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{ |
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struct _parisc_agp_info *info = &parisc_agp_info; |
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u32 command; |
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command = readl(info->lba_regs + info->lba_cap_offset + PCI_AGP_STATUS); |
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command = agp_collect_device_status(bridge, mode, command); |
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command |= 0x00000100; |
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writel(command, info->lba_regs + info->lba_cap_offset + PCI_AGP_COMMAND); |
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agp_device_command(command, (mode & AGP8X_MODE) != 0); |
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} |
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static const struct agp_bridge_driver parisc_agp_driver = { |
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.owner = THIS_MODULE, |
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.size_type = FIXED_APER_SIZE, |
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.configure = parisc_agp_configure, |
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.fetch_size = parisc_agp_fetch_size, |
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.tlb_flush = parisc_agp_tlbflush, |
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.mask_memory = parisc_agp_mask_memory, |
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.masks = parisc_agp_masks, |
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.agp_enable = parisc_agp_enable, |
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.cache_flush = global_cache_flush, |
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.create_gatt_table = parisc_agp_create_gatt_table, |
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.free_gatt_table = parisc_agp_free_gatt_table, |
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.insert_memory = parisc_agp_insert_memory, |
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.remove_memory = parisc_agp_remove_memory, |
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.alloc_by_type = agp_generic_alloc_by_type, |
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.free_by_type = agp_generic_free_by_type, |
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.agp_alloc_page = agp_generic_alloc_page, |
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.agp_alloc_pages = agp_generic_alloc_pages, |
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.agp_destroy_page = agp_generic_destroy_page, |
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.agp_destroy_pages = agp_generic_destroy_pages, |
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.agp_type_to_mask_type = agp_generic_type_to_mask_type, |
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.cant_use_aperture = true, |
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}; |
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static int __init |
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agp_ioc_init(void __iomem *ioc_regs) |
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{ |
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struct _parisc_agp_info *info = &parisc_agp_info; |
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u64 iova_base, *io_pdir, io_tlb_ps; |
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int io_tlb_shift; |
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printk(KERN_INFO DRVPFX "IO PDIR shared with sba_iommu\n"); |
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info->ioc_regs = ioc_regs; |
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io_tlb_ps = readq(info->ioc_regs+IOC_TCNFG); |
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switch (io_tlb_ps) { |
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case 0: io_tlb_shift = 12; break; |
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case 1: io_tlb_shift = 13; break; |
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case 2: io_tlb_shift = 14; break; |
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case 3: io_tlb_shift = 16; break; |
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default: |
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printk(KERN_ERR DRVPFX "Invalid IOTLB page size " |
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"configuration 0x%llx\n", io_tlb_ps); |
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info->gatt = NULL; |
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info->gatt_entries = 0; |
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return -ENODEV; |
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} |
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info->io_page_size = 1 << io_tlb_shift; |
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info->io_pages_per_kpage = PAGE_SIZE / info->io_page_size; |
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iova_base = readq(info->ioc_regs+IOC_IBASE) & ~0x1; |
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info->gart_base = iova_base + PLUTO_IOVA_SIZE - PLUTO_GART_SIZE; |
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info->gart_size = PLUTO_GART_SIZE; |
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info->gatt_entries = info->gart_size / info->io_page_size; |
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io_pdir = phys_to_virt(readq(info->ioc_regs+IOC_PDIR_BASE)); |
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info->gatt = &io_pdir[(PLUTO_IOVA_SIZE/2) >> PAGE_SHIFT]; |
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if (info->gatt[0] != SBA_AGPGART_COOKIE) { |
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info->gatt = NULL; |
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info->gatt_entries = 0; |
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printk(KERN_ERR DRVPFX "No reserved IO PDIR entry found; " |
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"GART disabled\n"); |
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return -ENODEV; |
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} |
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return 0; |
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} |
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static int |
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lba_find_capability(int cap) |
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{ |
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struct _parisc_agp_info *info = &parisc_agp_info; |
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u16 status; |
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u8 pos, id; |
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int ttl = 48; |
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status = readw(info->lba_regs + PCI_STATUS); |
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if (!(status & PCI_STATUS_CAP_LIST)) |
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return 0; |
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pos = readb(info->lba_regs + PCI_CAPABILITY_LIST); |
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while (ttl-- && pos >= 0x40) { |
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pos &= ~3; |
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id = readb(info->lba_regs + pos + PCI_CAP_LIST_ID); |
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if (id == 0xff) |
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break; |
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if (id == cap) |
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return pos; |
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pos = readb(info->lba_regs + pos + PCI_CAP_LIST_NEXT); |
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} |
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return 0; |
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} |
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static int __init |
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agp_lba_init(void __iomem *lba_hpa) |
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{ |
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struct _parisc_agp_info *info = &parisc_agp_info; |
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int cap; |
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info->lba_regs = lba_hpa; |
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info->lba_cap_offset = lba_find_capability(PCI_CAP_ID_AGP); |
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cap = readl(lba_hpa + info->lba_cap_offset) & 0xff; |
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if (cap != PCI_CAP_ID_AGP) { |
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printk(KERN_ERR DRVPFX "Invalid capability ID 0x%02x at 0x%x\n", |
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cap, info->lba_cap_offset); |
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return -ENODEV; |
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} |
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return 0; |
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} |
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static int __init |
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parisc_agp_setup(void __iomem *ioc_hpa, void __iomem *lba_hpa) |
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{ |
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struct pci_dev *fake_bridge_dev = NULL; |
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struct agp_bridge_data *bridge; |
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int error = 0; |
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fake_bridge_dev = pci_alloc_dev(NULL); |
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if (!fake_bridge_dev) { |
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error = -ENOMEM; |
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goto fail; |
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} |
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error = agp_ioc_init(ioc_hpa); |
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if (error) |
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goto fail; |
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error = agp_lba_init(lba_hpa); |
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if (error) |
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goto fail; |
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bridge = agp_alloc_bridge(); |
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if (!bridge) { |
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error = -ENOMEM; |
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goto fail; |
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} |
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bridge->driver = &parisc_agp_driver; |
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fake_bridge_dev->vendor = PCI_VENDOR_ID_HP; |
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fake_bridge_dev->device = PCI_DEVICE_ID_HP_PCIX_LBA; |
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bridge->dev = fake_bridge_dev; |
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error = agp_add_bridge(bridge); |
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if (error) |
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goto fail; |
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return 0; |
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fail: |
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kfree(fake_bridge_dev); |
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return error; |
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} |
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static int |
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find_quicksilver(struct device *dev, void *data) |
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{ |
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struct parisc_device **lba = data; |
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struct parisc_device *padev = to_parisc_device(dev); |
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if (IS_QUICKSILVER(padev)) |
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*lba = padev; |
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return 0; |
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} |
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static int |
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parisc_agp_init(void) |
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{ |
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extern struct sba_device *sba_list; |
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int err = -1; |
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struct parisc_device *sba = NULL, *lba = NULL; |
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struct lba_device *lbadev = NULL; |
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if (!sba_list) |
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goto out; |
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/* Find our parent Pluto */ |
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sba = sba_list->dev; |
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if (!IS_PLUTO(sba)) { |
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printk(KERN_INFO DRVPFX "No Pluto found, so no AGPGART for you.\n"); |
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goto out; |
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} |
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/* Now search our Pluto for our precious AGP device... */ |
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device_for_each_child(&sba->dev, &lba, find_quicksilver); |
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if (!lba) { |
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printk(KERN_INFO DRVPFX "No AGP devices found.\n"); |
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goto out; |
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} |
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lbadev = parisc_get_drvdata(lba); |
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/* w00t, let's go find our cookies... */ |
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parisc_agp_setup(sba_list->ioc[0].ioc_hpa, lbadev->hba.base_addr); |
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return 0; |
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out: |
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return err; |
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} |
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module_init(parisc_agp_init); |
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MODULE_AUTHOR("Kyle McMartin <[email protected]>"); |
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MODULE_LICENSE("GPL");
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