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465 lines
13 KiB
465 lines
13 KiB
// SPDX-License-Identifier: GPL-2.0 |
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/* |
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* Setup routines for AGP 3.5 compliant bridges. |
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*/ |
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|
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#include <linux/list.h> |
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#include <linux/pci.h> |
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#include <linux/agp_backend.h> |
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#include <linux/module.h> |
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#include <linux/slab.h> |
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#include "agp.h" |
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/* Generic AGP 3.5 enabling routines */ |
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struct agp_3_5_dev { |
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struct list_head list; |
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u8 capndx; |
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u32 maxbw; |
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struct pci_dev *dev; |
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}; |
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static void agp_3_5_dev_list_insert(struct list_head *head, struct list_head *new) |
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{ |
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struct agp_3_5_dev *cur, *n = list_entry(new, struct agp_3_5_dev, list); |
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struct list_head *pos; |
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list_for_each(pos, head) { |
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cur = list_entry(pos, struct agp_3_5_dev, list); |
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if (cur->maxbw > n->maxbw) |
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break; |
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} |
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list_add_tail(new, pos); |
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} |
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static void agp_3_5_dev_list_sort(struct agp_3_5_dev *list, unsigned int ndevs) |
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{ |
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struct agp_3_5_dev *cur; |
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struct pci_dev *dev; |
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struct list_head *pos, *tmp, *head = &list->list, *start = head->next; |
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u32 nistat; |
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INIT_LIST_HEAD(head); |
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for (pos=start; pos!=head; ) { |
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cur = list_entry(pos, struct agp_3_5_dev, list); |
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dev = cur->dev; |
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pci_read_config_dword(dev, cur->capndx+AGPNISTAT, &nistat); |
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cur->maxbw = (nistat >> 16) & 0xff; |
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tmp = pos; |
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pos = pos->next; |
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agp_3_5_dev_list_insert(head, tmp); |
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} |
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} |
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/* |
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* Initialize all isochronous transfer parameters for an AGP 3.0 |
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* node (i.e. a host bridge in combination with the adapters |
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* lying behind it...) |
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*/ |
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static int agp_3_5_isochronous_node_enable(struct agp_bridge_data *bridge, |
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struct agp_3_5_dev *dev_list, unsigned int ndevs) |
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{ |
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/* |
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* Convenience structure to make the calculations clearer |
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* here. The field names come straight from the AGP 3.0 spec. |
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*/ |
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struct isoch_data { |
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u32 maxbw; |
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u32 n; |
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u32 y; |
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u32 l; |
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u32 rq; |
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struct agp_3_5_dev *dev; |
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}; |
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struct pci_dev *td = bridge->dev, *dev; |
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struct list_head *head = &dev_list->list, *pos; |
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struct agp_3_5_dev *cur; |
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struct isoch_data *master, target; |
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unsigned int cdev = 0; |
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u32 mnistat, tnistat, tstatus, mcmd; |
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u16 tnicmd, mnicmd; |
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u32 tot_bw = 0, tot_n = 0, tot_rq = 0, y_max, rq_isoch, rq_async; |
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u32 step, rem, rem_isoch, rem_async; |
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int ret = 0; |
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/* |
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* We'll work with an array of isoch_data's (one for each |
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* device in dev_list) throughout this function. |
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*/ |
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master = kmalloc_array(ndevs, sizeof(*master), GFP_KERNEL); |
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if (master == NULL) { |
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ret = -ENOMEM; |
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goto get_out; |
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} |
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/* |
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* Sort the device list by maxbw. We need to do this because the |
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* spec suggests that the devices with the smallest requirements |
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* have their resources allocated first, with all remaining resources |
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* falling to the device with the largest requirement. |
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* |
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* We don't exactly do this, we divide target resources by ndevs |
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* and split them amongst the AGP 3.0 devices. The remainder of such |
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* division operations are dropped on the last device, sort of like |
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* the spec mentions it should be done. |
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* |
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* We can't do this sort when we initially construct the dev_list |
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* because we don't know until this function whether isochronous |
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* transfers are enabled and consequently whether maxbw will mean |
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* anything. |
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*/ |
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agp_3_5_dev_list_sort(dev_list, ndevs); |
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pci_read_config_dword(td, bridge->capndx+AGPNISTAT, &tnistat); |
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pci_read_config_dword(td, bridge->capndx+AGPSTAT, &tstatus); |
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/* Extract power-on defaults from the target */ |
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target.maxbw = (tnistat >> 16) & 0xff; |
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target.n = (tnistat >> 8) & 0xff; |
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target.y = (tnistat >> 6) & 0x3; |
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target.l = (tnistat >> 3) & 0x7; |
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target.rq = (tstatus >> 24) & 0xff; |
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y_max = target.y; |
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/* |
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* Extract power-on defaults for each device in dev_list. Along |
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* the way, calculate the total isochronous bandwidth required |
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* by these devices and the largest requested payload size. |
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*/ |
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list_for_each(pos, head) { |
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cur = list_entry(pos, struct agp_3_5_dev, list); |
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dev = cur->dev; |
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pci_read_config_dword(dev, cur->capndx+AGPNISTAT, &mnistat); |
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master[cdev].maxbw = (mnistat >> 16) & 0xff; |
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master[cdev].n = (mnistat >> 8) & 0xff; |
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master[cdev].y = (mnistat >> 6) & 0x3; |
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master[cdev].dev = cur; |
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tot_bw += master[cdev].maxbw; |
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y_max = max(y_max, master[cdev].y); |
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cdev++; |
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} |
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/* Check if this configuration has any chance of working */ |
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if (tot_bw > target.maxbw) { |
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dev_err(&td->dev, "isochronous bandwidth required " |
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"by AGP 3.0 devices exceeds that which is supported by " |
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"the AGP 3.0 bridge!\n"); |
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ret = -ENODEV; |
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goto free_and_exit; |
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} |
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target.y = y_max; |
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/* |
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* Write the calculated payload size into the target's NICMD |
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* register. Doing this directly effects the ISOCH_N value |
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* in the target's NISTAT register, so we need to do this now |
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* to get an accurate value for ISOCH_N later. |
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*/ |
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pci_read_config_word(td, bridge->capndx+AGPNICMD, &tnicmd); |
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tnicmd &= ~(0x3 << 6); |
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tnicmd |= target.y << 6; |
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pci_write_config_word(td, bridge->capndx+AGPNICMD, tnicmd); |
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/* Reread the target's ISOCH_N */ |
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pci_read_config_dword(td, bridge->capndx+AGPNISTAT, &tnistat); |
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target.n = (tnistat >> 8) & 0xff; |
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/* Calculate the minimum ISOCH_N needed by each master */ |
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for (cdev=0; cdev<ndevs; cdev++) { |
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master[cdev].y = target.y; |
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master[cdev].n = master[cdev].maxbw / (master[cdev].y + 1); |
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tot_n += master[cdev].n; |
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} |
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/* Exit if the minimal ISOCH_N allocation among the masters is more |
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* than the target can handle. */ |
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if (tot_n > target.n) { |
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dev_err(&td->dev, "number of isochronous " |
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"transactions per period required by AGP 3.0 devices " |
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"exceeds that which is supported by the AGP 3.0 " |
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"bridge!\n"); |
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ret = -ENODEV; |
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goto free_and_exit; |
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} |
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/* Calculate left over ISOCH_N capability in the target. We'll give |
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* this to the hungriest device (as per the spec) */ |
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rem = target.n - tot_n; |
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/* |
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* Calculate the minimum isochronous RQ depth needed by each master. |
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* Along the way, distribute the extra ISOCH_N capability calculated |
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* above. |
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*/ |
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for (cdev=0; cdev<ndevs; cdev++) { |
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/* |
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* This is a little subtle. If ISOCH_Y > 64B, then ISOCH_Y |
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* byte isochronous writes will be broken into 64B pieces. |
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* This means we need to budget more RQ depth to account for |
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* these kind of writes (each isochronous write is actually |
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* many writes on the AGP bus). |
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*/ |
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master[cdev].rq = master[cdev].n; |
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if (master[cdev].y > 0x1) |
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master[cdev].rq *= (1 << (master[cdev].y - 1)); |
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tot_rq += master[cdev].rq; |
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} |
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master[ndevs-1].n += rem; |
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/* Figure the number of isochronous and asynchronous RQ slots the |
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* target is providing. */ |
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rq_isoch = (target.y > 0x1) ? target.n * (1 << (target.y - 1)) : target.n; |
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rq_async = target.rq - rq_isoch; |
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/* Exit if the minimal RQ needs of the masters exceeds what the target |
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* can provide. */ |
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if (tot_rq > rq_isoch) { |
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dev_err(&td->dev, "number of request queue slots " |
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"required by the isochronous bandwidth requested by " |
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"AGP 3.0 devices exceeds the number provided by the " |
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"AGP 3.0 bridge!\n"); |
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ret = -ENODEV; |
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goto free_and_exit; |
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} |
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/* Calculate asynchronous RQ capability in the target (per master) as |
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* well as the total number of leftover isochronous RQ slots. */ |
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step = rq_async / ndevs; |
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rem_async = step + (rq_async % ndevs); |
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rem_isoch = rq_isoch - tot_rq; |
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/* Distribute the extra RQ slots calculated above and write our |
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* isochronous settings out to the actual devices. */ |
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for (cdev=0; cdev<ndevs; cdev++) { |
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cur = master[cdev].dev; |
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dev = cur->dev; |
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master[cdev].rq += (cdev == ndevs - 1) |
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? (rem_async + rem_isoch) : step; |
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pci_read_config_word(dev, cur->capndx+AGPNICMD, &mnicmd); |
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pci_read_config_dword(dev, cur->capndx+AGPCMD, &mcmd); |
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mnicmd &= ~(0xff << 8); |
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mnicmd &= ~(0x3 << 6); |
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mcmd &= ~(0xff << 24); |
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mnicmd |= master[cdev].n << 8; |
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mnicmd |= master[cdev].y << 6; |
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mcmd |= master[cdev].rq << 24; |
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pci_write_config_dword(dev, cur->capndx+AGPCMD, mcmd); |
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pci_write_config_word(dev, cur->capndx+AGPNICMD, mnicmd); |
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} |
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free_and_exit: |
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kfree(master); |
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get_out: |
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return ret; |
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} |
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/* |
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* This function basically allocates request queue slots among the |
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* AGP 3.0 systems in nonisochronous nodes. The algorithm is |
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* pretty stupid, divide the total number of RQ slots provided by the |
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* target by ndevs. Distribute this many slots to each AGP 3.0 device, |
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* giving any left over slots to the last device in dev_list. |
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*/ |
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static void agp_3_5_nonisochronous_node_enable(struct agp_bridge_data *bridge, |
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struct agp_3_5_dev *dev_list, unsigned int ndevs) |
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{ |
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struct agp_3_5_dev *cur; |
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struct list_head *head = &dev_list->list, *pos; |
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u32 tstatus, mcmd; |
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u32 trq, mrq, rem; |
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unsigned int cdev = 0; |
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pci_read_config_dword(bridge->dev, bridge->capndx+AGPSTAT, &tstatus); |
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trq = (tstatus >> 24) & 0xff; |
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mrq = trq / ndevs; |
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rem = mrq + (trq % ndevs); |
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for (pos=head->next; cdev<ndevs; cdev++, pos=pos->next) { |
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cur = list_entry(pos, struct agp_3_5_dev, list); |
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pci_read_config_dword(cur->dev, cur->capndx+AGPCMD, &mcmd); |
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mcmd &= ~(0xff << 24); |
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mcmd |= ((cdev == ndevs - 1) ? rem : mrq) << 24; |
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pci_write_config_dword(cur->dev, cur->capndx+AGPCMD, mcmd); |
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} |
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} |
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/* |
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* Fully configure and enable an AGP 3.0 host bridge and all the devices |
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* lying behind it. |
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*/ |
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int agp_3_5_enable(struct agp_bridge_data *bridge) |
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{ |
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struct pci_dev *td = bridge->dev, *dev = NULL; |
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u8 mcapndx; |
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u32 isoch; |
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u32 tstatus, mstatus, ncapid; |
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u32 mmajor; |
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u16 mpstat; |
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struct agp_3_5_dev *dev_list, *cur; |
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struct list_head *head, *pos; |
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unsigned int ndevs = 0; |
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int ret = 0; |
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/* Extract some power-on defaults from the target */ |
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pci_read_config_dword(td, bridge->capndx+AGPSTAT, &tstatus); |
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isoch = (tstatus >> 17) & 0x1; |
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if (isoch == 0) /* isoch xfers not available, bail out. */ |
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return -ENODEV; |
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/* |
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* Allocate a head for our AGP 3.5 device list |
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* (multiple AGP v3 devices are allowed behind a single bridge). |
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*/ |
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if ((dev_list = kmalloc(sizeof(*dev_list), GFP_KERNEL)) == NULL) { |
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ret = -ENOMEM; |
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goto get_out; |
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} |
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head = &dev_list->list; |
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INIT_LIST_HEAD(head); |
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/* Find all AGP devices, and add them to dev_list. */ |
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for_each_pci_dev(dev) { |
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mcapndx = pci_find_capability(dev, PCI_CAP_ID_AGP); |
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if (mcapndx == 0) |
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continue; |
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switch ((dev->class >>8) & 0xff00) { |
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case 0x0600: /* Bridge */ |
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/* Skip bridges. We should call this function for each one. */ |
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continue; |
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case 0x0001: /* Unclassified device */ |
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/* Don't know what this is, but log it for investigation. */ |
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if (mcapndx != 0) { |
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dev_info(&td->dev, "wacky, found unclassified AGP device %s [%04x/%04x]\n", |
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pci_name(dev), |
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dev->vendor, dev->device); |
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} |
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continue; |
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case 0x0300: /* Display controller */ |
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case 0x0400: /* Multimedia controller */ |
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if ((cur = kmalloc(sizeof(*cur), GFP_KERNEL)) == NULL) { |
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ret = -ENOMEM; |
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goto free_and_exit; |
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} |
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cur->dev = dev; |
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pos = &cur->list; |
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list_add(pos, head); |
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ndevs++; |
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continue; |
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default: |
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continue; |
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} |
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} |
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/* |
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* Take an initial pass through the devices lying behind our host |
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* bridge. Make sure each one is actually an AGP 3.0 device, otherwise |
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* exit with an error message. Along the way store the AGP 3.0 |
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* cap_ptr for each device |
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*/ |
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list_for_each(pos, head) { |
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cur = list_entry(pos, struct agp_3_5_dev, list); |
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dev = cur->dev; |
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pci_read_config_word(dev, PCI_STATUS, &mpstat); |
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if ((mpstat & PCI_STATUS_CAP_LIST) == 0) |
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continue; |
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pci_read_config_byte(dev, PCI_CAPABILITY_LIST, &mcapndx); |
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if (mcapndx != 0) { |
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do { |
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pci_read_config_dword(dev, mcapndx, &ncapid); |
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if ((ncapid & 0xff) != 2) |
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mcapndx = (ncapid >> 8) & 0xff; |
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} |
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while (((ncapid & 0xff) != 2) && (mcapndx != 0)); |
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} |
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if (mcapndx == 0) { |
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dev_err(&td->dev, "woah! Non-AGP device %s on " |
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"secondary bus of AGP 3.5 bridge!\n", |
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pci_name(dev)); |
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ret = -ENODEV; |
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goto free_and_exit; |
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} |
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mmajor = (ncapid >> AGP_MAJOR_VERSION_SHIFT) & 0xf; |
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if (mmajor < 3) { |
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dev_err(&td->dev, "woah! AGP 2.0 device %s on " |
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"secondary bus of AGP 3.5 bridge operating " |
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"with AGP 3.0 electricals!\n", pci_name(dev)); |
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ret = -ENODEV; |
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goto free_and_exit; |
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} |
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cur->capndx = mcapndx; |
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pci_read_config_dword(dev, cur->capndx+AGPSTAT, &mstatus); |
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if (((mstatus >> 3) & 0x1) == 0) { |
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dev_err(&td->dev, "woah! AGP 3.x device %s not " |
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"operating in AGP 3.x mode on secondary bus " |
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"of AGP 3.5 bridge operating with AGP 3.0 " |
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"electricals!\n", pci_name(dev)); |
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ret = -ENODEV; |
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goto free_and_exit; |
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} |
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} |
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/* |
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* Call functions to divide target resources amongst the AGP 3.0 |
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* masters. This process is dramatically different depending on |
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* whether isochronous transfers are supported. |
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*/ |
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if (isoch) { |
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ret = agp_3_5_isochronous_node_enable(bridge, dev_list, ndevs); |
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if (ret) { |
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dev_info(&td->dev, "something bad happened setting " |
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"up isochronous xfers; falling back to " |
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"non-isochronous xfer mode\n"); |
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} else { |
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goto free_and_exit; |
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} |
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} |
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agp_3_5_nonisochronous_node_enable(bridge, dev_list, ndevs); |
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free_and_exit: |
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/* Be sure to free the dev_list */ |
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for (pos=head->next; pos!=head; ) { |
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cur = list_entry(pos, struct agp_3_5_dev, list); |
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pos = pos->next; |
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kfree(cur); |
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} |
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kfree(dev_list); |
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get_out: |
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return ret; |
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}
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