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632 lines
17 KiB
632 lines
17 KiB
// SPDX-License-Identifier: GPL-2.0-only |
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/* |
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* Calxeda Highbank AHCI SATA platform driver |
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* Copyright 2012 Calxeda, Inc. |
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* |
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* based on the AHCI SATA platform driver by Jeff Garzik and Anton Vorontsov |
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*/ |
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#include <linux/kernel.h> |
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#include <linux/gfp.h> |
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#include <linux/module.h> |
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#include <linux/types.h> |
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#include <linux/err.h> |
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#include <linux/io.h> |
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#include <linux/spinlock.h> |
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#include <linux/device.h> |
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#include <linux/of_device.h> |
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#include <linux/of_address.h> |
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#include <linux/platform_device.h> |
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#include <linux/libata.h> |
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#include <linux/interrupt.h> |
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#include <linux/delay.h> |
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#include <linux/export.h> |
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#include <linux/gpio/consumer.h> |
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|
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#include "ahci.h" |
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|
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#define CPHY_MAP(dev, addr) ((((dev) & 0x1f) << 7) | (((addr) >> 9) & 0x7f)) |
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#define CPHY_ADDR(addr) (((addr) & 0x1ff) << 2) |
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#define SERDES_CR_CTL 0x80a0 |
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#define SERDES_CR_ADDR 0x80a1 |
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#define SERDES_CR_DATA 0x80a2 |
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#define CR_BUSY 0x0001 |
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#define CR_START 0x0001 |
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#define CR_WR_RDN 0x0002 |
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#define CPHY_TX_INPUT_STS 0x2001 |
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#define CPHY_RX_INPUT_STS 0x2002 |
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#define CPHY_SATA_TX_OVERRIDE 0x8000 |
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#define CPHY_SATA_RX_OVERRIDE 0x4000 |
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#define CPHY_TX_OVERRIDE 0x2004 |
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#define CPHY_RX_OVERRIDE 0x2005 |
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#define SPHY_LANE 0x100 |
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#define SPHY_HALF_RATE 0x0001 |
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#define CPHY_SATA_DPLL_MODE 0x0700 |
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#define CPHY_SATA_DPLL_SHIFT 8 |
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#define CPHY_SATA_DPLL_RESET (1 << 11) |
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#define CPHY_SATA_TX_ATTEN 0x1c00 |
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#define CPHY_SATA_TX_ATTEN_SHIFT 10 |
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#define CPHY_PHY_COUNT 6 |
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#define CPHY_LANE_COUNT 4 |
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#define CPHY_PORT_COUNT (CPHY_PHY_COUNT * CPHY_LANE_COUNT) |
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|
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static DEFINE_SPINLOCK(cphy_lock); |
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/* Each of the 6 phys can have up to 4 sata ports attached to i. Map 0-based |
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* sata ports to their phys and then to their lanes within the phys |
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*/ |
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struct phy_lane_info { |
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void __iomem *phy_base; |
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u8 lane_mapping; |
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u8 phy_devs; |
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u8 tx_atten; |
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}; |
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static struct phy_lane_info port_data[CPHY_PORT_COUNT]; |
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|
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static DEFINE_SPINLOCK(sgpio_lock); |
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#define SCLOCK 0 |
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#define SLOAD 1 |
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#define SDATA 2 |
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#define SGPIO_PINS 3 |
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#define SGPIO_PORTS 8 |
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struct ecx_plat_data { |
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u32 n_ports; |
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/* number of extra clocks that the SGPIO PIC controller expects */ |
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u32 pre_clocks; |
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u32 post_clocks; |
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struct gpio_desc *sgpio_gpiod[SGPIO_PINS]; |
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u32 sgpio_pattern; |
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u32 port_to_sgpio[SGPIO_PORTS]; |
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}; |
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#define SGPIO_SIGNALS 3 |
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#define ECX_ACTIVITY_BITS 0x300000 |
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#define ECX_ACTIVITY_SHIFT 0 |
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#define ECX_LOCATE_BITS 0x80000 |
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#define ECX_LOCATE_SHIFT 1 |
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#define ECX_FAULT_BITS 0x400000 |
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#define ECX_FAULT_SHIFT 2 |
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static inline int sgpio_bit_shift(struct ecx_plat_data *pdata, u32 port, |
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u32 shift) |
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{ |
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return 1 << (3 * pdata->port_to_sgpio[port] + shift); |
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} |
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static void ecx_parse_sgpio(struct ecx_plat_data *pdata, u32 port, u32 state) |
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{ |
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if (state & ECX_ACTIVITY_BITS) |
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pdata->sgpio_pattern |= sgpio_bit_shift(pdata, port, |
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ECX_ACTIVITY_SHIFT); |
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else |
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pdata->sgpio_pattern &= ~sgpio_bit_shift(pdata, port, |
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ECX_ACTIVITY_SHIFT); |
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if (state & ECX_LOCATE_BITS) |
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pdata->sgpio_pattern |= sgpio_bit_shift(pdata, port, |
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ECX_LOCATE_SHIFT); |
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else |
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pdata->sgpio_pattern &= ~sgpio_bit_shift(pdata, port, |
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ECX_LOCATE_SHIFT); |
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if (state & ECX_FAULT_BITS) |
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pdata->sgpio_pattern |= sgpio_bit_shift(pdata, port, |
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ECX_FAULT_SHIFT); |
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else |
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pdata->sgpio_pattern &= ~sgpio_bit_shift(pdata, port, |
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ECX_FAULT_SHIFT); |
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} |
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/* |
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* Tell the LED controller that the signal has changed by raising the clock |
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* line for 50 uS and then lowering it for 50 uS. |
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*/ |
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static void ecx_led_cycle_clock(struct ecx_plat_data *pdata) |
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{ |
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gpiod_set_value(pdata->sgpio_gpiod[SCLOCK], 1); |
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udelay(50); |
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gpiod_set_value(pdata->sgpio_gpiod[SCLOCK], 0); |
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udelay(50); |
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} |
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static ssize_t ecx_transmit_led_message(struct ata_port *ap, u32 state, |
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ssize_t size) |
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{ |
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struct ahci_host_priv *hpriv = ap->host->private_data; |
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struct ecx_plat_data *pdata = hpriv->plat_data; |
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struct ahci_port_priv *pp = ap->private_data; |
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unsigned long flags; |
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int pmp, i; |
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struct ahci_em_priv *emp; |
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u32 sgpio_out; |
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/* get the slot number from the message */ |
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pmp = (state & EM_MSG_LED_PMP_SLOT) >> 8; |
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if (pmp < EM_MAX_SLOTS) |
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emp = &pp->em_priv[pmp]; |
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else |
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return -EINVAL; |
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if (!(hpriv->em_msg_type & EM_MSG_TYPE_LED)) |
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return size; |
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spin_lock_irqsave(&sgpio_lock, flags); |
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ecx_parse_sgpio(pdata, ap->port_no, state); |
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sgpio_out = pdata->sgpio_pattern; |
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for (i = 0; i < pdata->pre_clocks; i++) |
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ecx_led_cycle_clock(pdata); |
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gpiod_set_value(pdata->sgpio_gpiod[SLOAD], 1); |
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ecx_led_cycle_clock(pdata); |
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gpiod_set_value(pdata->sgpio_gpiod[SLOAD], 0); |
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/* |
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* bit-bang out the SGPIO pattern, by consuming a bit and then |
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* clocking it out. |
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*/ |
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for (i = 0; i < (SGPIO_SIGNALS * pdata->n_ports); i++) { |
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gpiod_set_value(pdata->sgpio_gpiod[SDATA], sgpio_out & 1); |
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sgpio_out >>= 1; |
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ecx_led_cycle_clock(pdata); |
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} |
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for (i = 0; i < pdata->post_clocks; i++) |
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ecx_led_cycle_clock(pdata); |
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/* save off new led state for port/slot */ |
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emp->led_state = state; |
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spin_unlock_irqrestore(&sgpio_lock, flags); |
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return size; |
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} |
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static void highbank_set_em_messages(struct device *dev, |
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struct ahci_host_priv *hpriv, |
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struct ata_port_info *pi) |
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{ |
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struct device_node *np = dev->of_node; |
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struct ecx_plat_data *pdata = hpriv->plat_data; |
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int i; |
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for (i = 0; i < SGPIO_PINS; i++) { |
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struct gpio_desc *gpiod; |
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gpiod = devm_gpiod_get_index(dev, "calxeda,sgpio", i, |
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GPIOD_OUT_HIGH); |
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if (IS_ERR(gpiod)) { |
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dev_err(dev, "failed to get GPIO %d\n", i); |
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continue; |
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} |
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gpiod_set_consumer_name(gpiod, "CX SGPIO"); |
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pdata->sgpio_gpiod[i] = gpiod; |
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} |
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of_property_read_u32_array(np, "calxeda,led-order", |
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pdata->port_to_sgpio, |
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pdata->n_ports); |
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if (of_property_read_u32(np, "calxeda,pre-clocks", &pdata->pre_clocks)) |
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pdata->pre_clocks = 0; |
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if (of_property_read_u32(np, "calxeda,post-clocks", |
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&pdata->post_clocks)) |
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pdata->post_clocks = 0; |
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/* store em_loc */ |
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hpriv->em_loc = 0; |
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hpriv->em_buf_sz = 4; |
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hpriv->em_msg_type = EM_MSG_TYPE_LED; |
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pi->flags |= ATA_FLAG_EM | ATA_FLAG_SW_ACTIVITY; |
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} |
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static u32 __combo_phy_reg_read(u8 sata_port, u32 addr) |
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{ |
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u32 data; |
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u8 dev = port_data[sata_port].phy_devs; |
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spin_lock(&cphy_lock); |
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writel(CPHY_MAP(dev, addr), port_data[sata_port].phy_base + 0x800); |
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data = readl(port_data[sata_port].phy_base + CPHY_ADDR(addr)); |
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spin_unlock(&cphy_lock); |
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return data; |
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} |
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static void __combo_phy_reg_write(u8 sata_port, u32 addr, u32 data) |
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{ |
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u8 dev = port_data[sata_port].phy_devs; |
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spin_lock(&cphy_lock); |
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writel(CPHY_MAP(dev, addr), port_data[sata_port].phy_base + 0x800); |
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writel(data, port_data[sata_port].phy_base + CPHY_ADDR(addr)); |
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spin_unlock(&cphy_lock); |
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} |
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static void combo_phy_wait_for_ready(u8 sata_port) |
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{ |
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while (__combo_phy_reg_read(sata_port, SERDES_CR_CTL) & CR_BUSY) |
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udelay(5); |
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} |
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static u32 combo_phy_read(u8 sata_port, u32 addr) |
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{ |
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combo_phy_wait_for_ready(sata_port); |
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__combo_phy_reg_write(sata_port, SERDES_CR_ADDR, addr); |
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__combo_phy_reg_write(sata_port, SERDES_CR_CTL, CR_START); |
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combo_phy_wait_for_ready(sata_port); |
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return __combo_phy_reg_read(sata_port, SERDES_CR_DATA); |
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} |
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static void combo_phy_write(u8 sata_port, u32 addr, u32 data) |
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{ |
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combo_phy_wait_for_ready(sata_port); |
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__combo_phy_reg_write(sata_port, SERDES_CR_ADDR, addr); |
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__combo_phy_reg_write(sata_port, SERDES_CR_DATA, data); |
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__combo_phy_reg_write(sata_port, SERDES_CR_CTL, CR_WR_RDN | CR_START); |
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} |
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static void highbank_cphy_disable_overrides(u8 sata_port) |
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{ |
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u8 lane = port_data[sata_port].lane_mapping; |
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u32 tmp; |
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if (unlikely(port_data[sata_port].phy_base == NULL)) |
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return; |
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tmp = combo_phy_read(sata_port, CPHY_RX_INPUT_STS + lane * SPHY_LANE); |
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tmp &= ~CPHY_SATA_RX_OVERRIDE; |
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combo_phy_write(sata_port, CPHY_RX_OVERRIDE + lane * SPHY_LANE, tmp); |
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} |
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static void cphy_override_tx_attenuation(u8 sata_port, u32 val) |
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{ |
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u8 lane = port_data[sata_port].lane_mapping; |
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u32 tmp; |
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if (val & 0x8) |
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return; |
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tmp = combo_phy_read(sata_port, CPHY_TX_INPUT_STS + lane * SPHY_LANE); |
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tmp &= ~CPHY_SATA_TX_OVERRIDE; |
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combo_phy_write(sata_port, CPHY_TX_OVERRIDE + lane * SPHY_LANE, tmp); |
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tmp |= CPHY_SATA_TX_OVERRIDE; |
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combo_phy_write(sata_port, CPHY_TX_OVERRIDE + lane * SPHY_LANE, tmp); |
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tmp |= (val << CPHY_SATA_TX_ATTEN_SHIFT) & CPHY_SATA_TX_ATTEN; |
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combo_phy_write(sata_port, CPHY_TX_OVERRIDE + lane * SPHY_LANE, tmp); |
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} |
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static void cphy_override_rx_mode(u8 sata_port, u32 val) |
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{ |
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u8 lane = port_data[sata_port].lane_mapping; |
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u32 tmp; |
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tmp = combo_phy_read(sata_port, CPHY_RX_INPUT_STS + lane * SPHY_LANE); |
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tmp &= ~CPHY_SATA_RX_OVERRIDE; |
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combo_phy_write(sata_port, CPHY_RX_OVERRIDE + lane * SPHY_LANE, tmp); |
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tmp |= CPHY_SATA_RX_OVERRIDE; |
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combo_phy_write(sata_port, CPHY_RX_OVERRIDE + lane * SPHY_LANE, tmp); |
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tmp &= ~CPHY_SATA_DPLL_MODE; |
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tmp |= val << CPHY_SATA_DPLL_SHIFT; |
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combo_phy_write(sata_port, CPHY_RX_OVERRIDE + lane * SPHY_LANE, tmp); |
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tmp |= CPHY_SATA_DPLL_RESET; |
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combo_phy_write(sata_port, CPHY_RX_OVERRIDE + lane * SPHY_LANE, tmp); |
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tmp &= ~CPHY_SATA_DPLL_RESET; |
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combo_phy_write(sata_port, CPHY_RX_OVERRIDE + lane * SPHY_LANE, tmp); |
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msleep(15); |
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} |
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static void highbank_cphy_override_lane(u8 sata_port) |
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{ |
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u8 lane = port_data[sata_port].lane_mapping; |
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u32 tmp, k = 0; |
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if (unlikely(port_data[sata_port].phy_base == NULL)) |
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return; |
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do { |
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tmp = combo_phy_read(sata_port, CPHY_RX_INPUT_STS + |
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lane * SPHY_LANE); |
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} while ((tmp & SPHY_HALF_RATE) && (k++ < 1000)); |
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cphy_override_rx_mode(sata_port, 3); |
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cphy_override_tx_attenuation(sata_port, port_data[sata_port].tx_atten); |
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} |
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static int highbank_initialize_phys(struct device *dev, void __iomem *addr) |
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{ |
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struct device_node *sata_node = dev->of_node; |
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int phy_count = 0, phy, port = 0, i; |
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void __iomem *cphy_base[CPHY_PHY_COUNT] = {}; |
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struct device_node *phy_nodes[CPHY_PHY_COUNT] = {}; |
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u32 tx_atten[CPHY_PORT_COUNT] = {}; |
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memset(port_data, 0, sizeof(struct phy_lane_info) * CPHY_PORT_COUNT); |
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do { |
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u32 tmp; |
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struct of_phandle_args phy_data; |
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if (of_parse_phandle_with_args(sata_node, |
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"calxeda,port-phys", "#phy-cells", |
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port, &phy_data)) |
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break; |
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for (phy = 0; phy < phy_count; phy++) { |
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if (phy_nodes[phy] == phy_data.np) |
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break; |
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} |
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if (phy_nodes[phy] == NULL) { |
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phy_nodes[phy] = phy_data.np; |
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cphy_base[phy] = of_iomap(phy_nodes[phy], 0); |
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if (cphy_base[phy] == NULL) { |
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return 0; |
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} |
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phy_count += 1; |
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} |
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port_data[port].lane_mapping = phy_data.args[0]; |
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of_property_read_u32(phy_nodes[phy], "phydev", &tmp); |
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port_data[port].phy_devs = tmp; |
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port_data[port].phy_base = cphy_base[phy]; |
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of_node_put(phy_data.np); |
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port += 1; |
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} while (port < CPHY_PORT_COUNT); |
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of_property_read_u32_array(sata_node, "calxeda,tx-atten", |
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tx_atten, port); |
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for (i = 0; i < port; i++) |
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port_data[i].tx_atten = (u8) tx_atten[i]; |
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return 0; |
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} |
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/* |
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* The Calxeda SATA phy intermittently fails to bring up a link with Gen3 |
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* Retrying the phy hard reset can work around the issue, but the drive |
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* may fail again. In less than 150 out of 15000 test runs, it took more |
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* than 10 tries for the link to be established (but never more than 35). |
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* Triple the maximum observed retry count to provide plenty of margin for |
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* rare events and to guarantee that the link is established. |
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* |
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* Also, the default 2 second time-out on a failed drive is too long in |
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* this situation. The uboot implementation of the same driver function |
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* uses a much shorter time-out period and never experiences a time out |
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* issue. Reducing the time-out to 500ms improves the responsiveness. |
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* The other timing constants were kept the same as the stock AHCI driver. |
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* This change was also tested 15000 times on 24 drives and none of them |
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* experienced a time out. |
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*/ |
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static int ahci_highbank_hardreset(struct ata_link *link, unsigned int *class, |
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unsigned long deadline) |
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{ |
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static const unsigned long timing[] = { 5, 100, 500}; |
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struct ata_port *ap = link->ap; |
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struct ahci_port_priv *pp = ap->private_data; |
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struct ahci_host_priv *hpriv = ap->host->private_data; |
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u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG; |
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struct ata_taskfile tf; |
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bool online; |
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u32 sstatus; |
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int rc; |
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int retry = 100; |
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hpriv->stop_engine(ap); |
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|
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/* clear D2H reception area to properly wait for D2H FIS */ |
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ata_tf_init(link->device, &tf); |
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tf.command = ATA_BUSY; |
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ata_tf_to_fis(&tf, 0, 0, d2h_fis); |
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do { |
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highbank_cphy_disable_overrides(link->ap->port_no); |
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rc = sata_link_hardreset(link, timing, deadline, &online, NULL); |
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highbank_cphy_override_lane(link->ap->port_no); |
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|
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/* If the status is 1, we are connected, but the link did not |
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* come up. So retry resetting the link again. |
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*/ |
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if (sata_scr_read(link, SCR_STATUS, &sstatus)) |
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break; |
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if (!(sstatus & 0x3)) |
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break; |
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} while (!online && retry--); |
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hpriv->start_engine(ap); |
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if (online) |
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*class = ahci_dev_classify(ap); |
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return rc; |
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} |
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static struct ata_port_operations ahci_highbank_ops = { |
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.inherits = &ahci_ops, |
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.hardreset = ahci_highbank_hardreset, |
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.transmit_led_message = ecx_transmit_led_message, |
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}; |
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static const struct ata_port_info ahci_highbank_port_info = { |
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.flags = AHCI_FLAG_COMMON, |
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.pio_mask = ATA_PIO4, |
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.udma_mask = ATA_UDMA6, |
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.port_ops = &ahci_highbank_ops, |
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}; |
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static struct scsi_host_template ahci_highbank_platform_sht = { |
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AHCI_SHT("sata_highbank"), |
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}; |
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static const struct of_device_id ahci_of_match[] = { |
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{ .compatible = "calxeda,hb-ahci" }, |
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{}, |
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}; |
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MODULE_DEVICE_TABLE(of, ahci_of_match); |
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|
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static int ahci_highbank_probe(struct platform_device *pdev) |
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{ |
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struct device *dev = &pdev->dev; |
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struct ahci_host_priv *hpriv; |
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struct ecx_plat_data *pdata; |
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struct ata_host *host; |
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struct resource *mem; |
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int irq; |
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int i; |
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int rc; |
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u32 n_ports; |
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struct ata_port_info pi = ahci_highbank_port_info; |
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const struct ata_port_info *ppi[] = { &pi, NULL }; |
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mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
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if (!mem) { |
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dev_err(dev, "no mmio space\n"); |
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return -EINVAL; |
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} |
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irq = platform_get_irq(pdev, 0); |
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if (irq < 0) { |
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dev_err(dev, "no irq\n"); |
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return irq; |
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} |
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if (!irq) |
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return -EINVAL; |
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|
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hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL); |
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if (!hpriv) { |
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dev_err(dev, "can't alloc ahci_host_priv\n"); |
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return -ENOMEM; |
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} |
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pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL); |
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if (!pdata) { |
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dev_err(dev, "can't alloc ecx_plat_data\n"); |
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return -ENOMEM; |
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} |
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|
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hpriv->irq = irq; |
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hpriv->flags |= (unsigned long)pi.private_data; |
|
|
|
hpriv->mmio = devm_ioremap(dev, mem->start, resource_size(mem)); |
|
if (!hpriv->mmio) { |
|
dev_err(dev, "can't map %pR\n", mem); |
|
return -ENOMEM; |
|
} |
|
|
|
rc = highbank_initialize_phys(dev, hpriv->mmio); |
|
if (rc) |
|
return rc; |
|
|
|
|
|
ahci_save_initial_config(dev, hpriv); |
|
|
|
/* prepare host */ |
|
if (hpriv->cap & HOST_CAP_NCQ) |
|
pi.flags |= ATA_FLAG_NCQ; |
|
|
|
if (hpriv->cap & HOST_CAP_PMP) |
|
pi.flags |= ATA_FLAG_PMP; |
|
|
|
if (hpriv->cap & HOST_CAP_64) |
|
dma_set_coherent_mask(dev, DMA_BIT_MASK(64)); |
|
|
|
/* CAP.NP sometimes indicate the index of the last enabled |
|
* port, at other times, that of the last possible port, so |
|
* determining the maximum port number requires looking at |
|
* both CAP.NP and port_map. |
|
*/ |
|
n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map)); |
|
|
|
pdata->n_ports = n_ports; |
|
hpriv->plat_data = pdata; |
|
highbank_set_em_messages(dev, hpriv, &pi); |
|
|
|
host = ata_host_alloc_pinfo(dev, ppi, n_ports); |
|
if (!host) { |
|
rc = -ENOMEM; |
|
goto err0; |
|
} |
|
|
|
host->private_data = hpriv; |
|
|
|
if (!(hpriv->cap & HOST_CAP_SSS) || ahci_ignore_sss) |
|
host->flags |= ATA_HOST_PARALLEL_SCAN; |
|
|
|
for (i = 0; i < host->n_ports; i++) { |
|
struct ata_port *ap = host->ports[i]; |
|
|
|
ata_port_desc(ap, "mmio %pR", mem); |
|
ata_port_desc(ap, "port 0x%x", 0x100 + ap->port_no * 0x80); |
|
|
|
/* set enclosure management message type */ |
|
if (ap->flags & ATA_FLAG_EM) |
|
ap->em_message_type = hpriv->em_msg_type; |
|
|
|
/* disabled/not-implemented port */ |
|
if (!(hpriv->port_map & (1 << i))) |
|
ap->ops = &ata_dummy_port_ops; |
|
} |
|
|
|
rc = ahci_reset_controller(host); |
|
if (rc) |
|
goto err0; |
|
|
|
ahci_init_controller(host); |
|
ahci_print_info(host, "platform"); |
|
|
|
rc = ahci_host_activate(host, &ahci_highbank_platform_sht); |
|
if (rc) |
|
goto err0; |
|
|
|
return 0; |
|
err0: |
|
return rc; |
|
} |
|
|
|
#ifdef CONFIG_PM_SLEEP |
|
static int ahci_highbank_suspend(struct device *dev) |
|
{ |
|
struct ata_host *host = dev_get_drvdata(dev); |
|
struct ahci_host_priv *hpriv = host->private_data; |
|
void __iomem *mmio = hpriv->mmio; |
|
u32 ctl; |
|
|
|
if (hpriv->flags & AHCI_HFLAG_NO_SUSPEND) { |
|
dev_err(dev, "firmware update required for suspend/resume\n"); |
|
return -EIO; |
|
} |
|
|
|
/* |
|
* AHCI spec rev1.1 section 8.3.3: |
|
* Software must disable interrupts prior to requesting a |
|
* transition of the HBA to D3 state. |
|
*/ |
|
ctl = readl(mmio + HOST_CTL); |
|
ctl &= ~HOST_IRQ_EN; |
|
writel(ctl, mmio + HOST_CTL); |
|
readl(mmio + HOST_CTL); /* flush */ |
|
|
|
return ata_host_suspend(host, PMSG_SUSPEND); |
|
} |
|
|
|
static int ahci_highbank_resume(struct device *dev) |
|
{ |
|
struct ata_host *host = dev_get_drvdata(dev); |
|
int rc; |
|
|
|
if (dev->power.power_state.event == PM_EVENT_SUSPEND) { |
|
rc = ahci_reset_controller(host); |
|
if (rc) |
|
return rc; |
|
|
|
ahci_init_controller(host); |
|
} |
|
|
|
ata_host_resume(host); |
|
|
|
return 0; |
|
} |
|
#endif |
|
|
|
static SIMPLE_DEV_PM_OPS(ahci_highbank_pm_ops, |
|
ahci_highbank_suspend, ahci_highbank_resume); |
|
|
|
static struct platform_driver ahci_highbank_driver = { |
|
.remove = ata_platform_remove_one, |
|
.driver = { |
|
.name = "highbank-ahci", |
|
.of_match_table = ahci_of_match, |
|
.pm = &ahci_highbank_pm_ops, |
|
}, |
|
.probe = ahci_highbank_probe, |
|
}; |
|
|
|
module_platform_driver(ahci_highbank_driver); |
|
|
|
MODULE_DESCRIPTION("Calxeda Highbank AHCI SATA platform driver"); |
|
MODULE_AUTHOR("Mark Langsdorf <[email protected]>"); |
|
MODULE_LICENSE("GPL"); |
|
MODULE_ALIAS("sata:highbank");
|
|
|