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425 lines
11 KiB
425 lines
11 KiB
// SPDX-License-Identifier: GPL-2.0-only |
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/* |
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* Libata driver for the highpoint 366 and 368 UDMA66 ATA controllers. |
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* |
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* This driver is heavily based upon: |
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* |
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* linux/drivers/ide/pci/hpt366.c Version 0.36 April 25, 2003 |
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* |
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* Copyright (C) 1999-2003 Andre Hedrick <[email protected]> |
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* Portions Copyright (C) 2001 Sun Microsystems, Inc. |
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* Portions Copyright (C) 2003 Red Hat Inc |
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* |
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* |
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* TODO |
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* Look into engine reset on timeout errors. Should not be required. |
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*/ |
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#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
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#include <linux/kernel.h> |
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#include <linux/module.h> |
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#include <linux/pci.h> |
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#include <linux/blkdev.h> |
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#include <linux/delay.h> |
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#include <scsi/scsi_host.h> |
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#include <linux/libata.h> |
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#define DRV_NAME "pata_hpt366" |
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#define DRV_VERSION "0.6.11" |
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struct hpt_clock { |
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u8 xfer_mode; |
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u32 timing; |
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}; |
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/* key for bus clock timings |
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* bit |
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* 0:3 data_high_time. Inactive time of DIOW_/DIOR_ for PIO and MW DMA. |
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* cycles = value + 1 |
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* 4:7 data_low_time. Active time of DIOW_/DIOR_ for PIO and MW DMA. |
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* cycles = value + 1 |
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* 8:11 cmd_high_time. Inactive time of DIOW_/DIOR_ during task file |
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* register access. |
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* 12:15 cmd_low_time. Active time of DIOW_/DIOR_ during task file |
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* register access. |
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* 16:18 udma_cycle_time. Clock cycles for UDMA xfer? |
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* 19:21 pre_high_time. Time to initialize 1st cycle for PIO and MW DMA xfer. |
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* 22:24 cmd_pre_high_time. Time to initialize 1st PIO cycle for task file |
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* register access. |
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* 28 UDMA enable. |
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* 29 DMA enable. |
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* 30 PIO_MST enable. If set, the chip is in bus master mode during |
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* PIO xfer. |
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* 31 FIFO enable. |
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*/ |
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static const struct hpt_clock hpt366_40[] = { |
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{ XFER_UDMA_4, 0x900fd943 }, |
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{ XFER_UDMA_3, 0x900ad943 }, |
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{ XFER_UDMA_2, 0x900bd943 }, |
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{ XFER_UDMA_1, 0x9008d943 }, |
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{ XFER_UDMA_0, 0x9008d943 }, |
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{ XFER_MW_DMA_2, 0xa008d943 }, |
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{ XFER_MW_DMA_1, 0xa010d955 }, |
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{ XFER_MW_DMA_0, 0xa010d9fc }, |
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{ XFER_PIO_4, 0xc008d963 }, |
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{ XFER_PIO_3, 0xc010d974 }, |
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{ XFER_PIO_2, 0xc010d997 }, |
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{ XFER_PIO_1, 0xc010d9c7 }, |
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{ XFER_PIO_0, 0xc018d9d9 }, |
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{ 0, 0x0120d9d9 } |
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}; |
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static const struct hpt_clock hpt366_33[] = { |
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{ XFER_UDMA_4, 0x90c9a731 }, |
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{ XFER_UDMA_3, 0x90cfa731 }, |
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{ XFER_UDMA_2, 0x90caa731 }, |
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{ XFER_UDMA_1, 0x90cba731 }, |
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{ XFER_UDMA_0, 0x90c8a731 }, |
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{ XFER_MW_DMA_2, 0xa0c8a731 }, |
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{ XFER_MW_DMA_1, 0xa0c8a732 }, /* 0xa0c8a733 */ |
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{ XFER_MW_DMA_0, 0xa0c8a797 }, |
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{ XFER_PIO_4, 0xc0c8a731 }, |
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{ XFER_PIO_3, 0xc0c8a742 }, |
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{ XFER_PIO_2, 0xc0d0a753 }, |
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{ XFER_PIO_1, 0xc0d0a7a3 }, /* 0xc0d0a793 */ |
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{ XFER_PIO_0, 0xc0d0a7aa }, /* 0xc0d0a7a7 */ |
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{ 0, 0x0120a7a7 } |
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}; |
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static const struct hpt_clock hpt366_25[] = { |
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{ XFER_UDMA_4, 0x90c98521 }, |
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{ XFER_UDMA_3, 0x90cf8521 }, |
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{ XFER_UDMA_2, 0x90cf8521 }, |
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{ XFER_UDMA_1, 0x90cb8521 }, |
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{ XFER_UDMA_0, 0x90cb8521 }, |
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{ XFER_MW_DMA_2, 0xa0ca8521 }, |
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{ XFER_MW_DMA_1, 0xa0ca8532 }, |
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{ XFER_MW_DMA_0, 0xa0ca8575 }, |
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{ XFER_PIO_4, 0xc0ca8521 }, |
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{ XFER_PIO_3, 0xc0ca8532 }, |
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{ XFER_PIO_2, 0xc0ca8542 }, |
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{ XFER_PIO_1, 0xc0d08572 }, |
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{ XFER_PIO_0, 0xc0d08585 }, |
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{ 0, 0x01208585 } |
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}; |
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/** |
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* hpt36x_find_mode - find the hpt36x timing |
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* @ap: ATA port |
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* @speed: transfer mode |
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* |
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* Return the 32bit register programming information for this channel |
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* that matches the speed provided. |
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*/ |
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static u32 hpt36x_find_mode(struct ata_port *ap, int speed) |
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{ |
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struct hpt_clock *clocks = ap->host->private_data; |
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while (clocks->xfer_mode) { |
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if (clocks->xfer_mode == speed) |
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return clocks->timing; |
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clocks++; |
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} |
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BUG(); |
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return 0xffffffffU; /* silence compiler warning */ |
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} |
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static const char * const bad_ata33[] = { |
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"Maxtor 92720U8", "Maxtor 92040U6", "Maxtor 91360U4", "Maxtor 91020U3", |
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"Maxtor 90845U3", "Maxtor 90650U2", |
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"Maxtor 91360D8", "Maxtor 91190D7", "Maxtor 91020D6", "Maxtor 90845D5", |
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"Maxtor 90680D4", "Maxtor 90510D3", "Maxtor 90340D2", |
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"Maxtor 91152D8", "Maxtor 91008D7", "Maxtor 90845D6", "Maxtor 90840D6", |
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"Maxtor 90720D5", "Maxtor 90648D5", "Maxtor 90576D4", |
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"Maxtor 90510D4", |
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"Maxtor 90432D3", "Maxtor 90288D2", "Maxtor 90256D2", |
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"Maxtor 91000D8", "Maxtor 90910D8", "Maxtor 90875D7", "Maxtor 90840D7", |
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"Maxtor 90750D6", "Maxtor 90625D5", "Maxtor 90500D4", |
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"Maxtor 91728D8", "Maxtor 91512D7", "Maxtor 91303D6", "Maxtor 91080D5", |
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"Maxtor 90845D4", "Maxtor 90680D4", "Maxtor 90648D3", "Maxtor 90432D2", |
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NULL |
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}; |
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static const char * const bad_ata66_4[] = { |
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"IBM-DTLA-307075", |
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"IBM-DTLA-307060", |
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"IBM-DTLA-307045", |
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"IBM-DTLA-307030", |
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"IBM-DTLA-307020", |
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"IBM-DTLA-307015", |
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"IBM-DTLA-305040", |
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"IBM-DTLA-305030", |
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"IBM-DTLA-305020", |
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"IC35L010AVER07-0", |
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"IC35L020AVER07-0", |
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"IC35L030AVER07-0", |
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"IC35L040AVER07-0", |
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"IC35L060AVER07-0", |
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"WDC AC310200R", |
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NULL |
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}; |
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static const char * const bad_ata66_3[] = { |
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"WDC AC310200R", |
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NULL |
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}; |
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static int hpt_dma_blacklisted(const struct ata_device *dev, char *modestr, |
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const char * const list[]) |
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{ |
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unsigned char model_num[ATA_ID_PROD_LEN + 1]; |
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int i; |
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ata_id_c_string(dev->id, model_num, ATA_ID_PROD, sizeof(model_num)); |
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i = match_string(list, -1, model_num); |
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if (i >= 0) { |
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pr_warn("%s is not supported for %s\n", modestr, list[i]); |
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return 1; |
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} |
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return 0; |
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} |
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/** |
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* hpt366_filter - mode selection filter |
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* @adev: ATA device |
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* @mask: Current mask to manipulate and pass back |
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* |
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* Block UDMA on devices that cause trouble with this controller. |
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*/ |
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static unsigned long hpt366_filter(struct ata_device *adev, unsigned long mask) |
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{ |
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if (adev->class == ATA_DEV_ATA) { |
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if (hpt_dma_blacklisted(adev, "UDMA", bad_ata33)) |
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mask &= ~ATA_MASK_UDMA; |
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if (hpt_dma_blacklisted(adev, "UDMA3", bad_ata66_3)) |
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mask &= ~(0xF8 << ATA_SHIFT_UDMA); |
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if (hpt_dma_blacklisted(adev, "UDMA4", bad_ata66_4)) |
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mask &= ~(0xF0 << ATA_SHIFT_UDMA); |
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} else if (adev->class == ATA_DEV_ATAPI) |
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mask &= ~(ATA_MASK_MWDMA | ATA_MASK_UDMA); |
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return mask; |
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} |
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static int hpt36x_cable_detect(struct ata_port *ap) |
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{ |
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struct pci_dev *pdev = to_pci_dev(ap->host->dev); |
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u8 ata66; |
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/* |
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* Each channel of pata_hpt366 occupies separate PCI function |
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* as the primary channel and bit1 indicates the cable type. |
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*/ |
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pci_read_config_byte(pdev, 0x5A, &ata66); |
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if (ata66 & 2) |
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return ATA_CBL_PATA40; |
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return ATA_CBL_PATA80; |
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} |
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static void hpt366_set_mode(struct ata_port *ap, struct ata_device *adev, |
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u8 mode) |
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{ |
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struct pci_dev *pdev = to_pci_dev(ap->host->dev); |
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u32 addr = 0x40 + 4 * adev->devno; |
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u32 mask, reg, t; |
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/* determine timing mask and find matching clock entry */ |
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if (mode < XFER_MW_DMA_0) |
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mask = 0xc1f8ffff; |
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else if (mode < XFER_UDMA_0) |
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mask = 0x303800ff; |
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else |
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mask = 0x30070000; |
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t = hpt36x_find_mode(ap, mode); |
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/* |
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* Combine new mode bits with old config bits and disable |
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* on-chip PIO FIFO/buffer (and PIO MST mode as well) to avoid |
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* problems handling I/O errors later. |
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*/ |
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pci_read_config_dword(pdev, addr, ®); |
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reg = ((reg & ~mask) | (t & mask)) & ~0xc0000000; |
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pci_write_config_dword(pdev, addr, reg); |
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} |
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/** |
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* hpt366_set_piomode - PIO setup |
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* @ap: ATA interface |
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* @adev: device on the interface |
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* |
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* Perform PIO mode setup. |
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*/ |
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static void hpt366_set_piomode(struct ata_port *ap, struct ata_device *adev) |
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{ |
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hpt366_set_mode(ap, adev, adev->pio_mode); |
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} |
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/** |
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* hpt366_set_dmamode - DMA timing setup |
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* @ap: ATA interface |
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* @adev: Device being configured |
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* |
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* Set up the channel for MWDMA or UDMA modes. Much the same as with |
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* PIO, load the mode number and then set MWDMA or UDMA flag. |
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*/ |
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static void hpt366_set_dmamode(struct ata_port *ap, struct ata_device *adev) |
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{ |
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hpt366_set_mode(ap, adev, adev->dma_mode); |
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} |
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static struct scsi_host_template hpt36x_sht = { |
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ATA_BMDMA_SHT(DRV_NAME), |
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}; |
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/* |
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* Configuration for HPT366/68 |
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*/ |
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static struct ata_port_operations hpt366_port_ops = { |
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.inherits = &ata_bmdma_port_ops, |
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.cable_detect = hpt36x_cable_detect, |
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.mode_filter = hpt366_filter, |
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.set_piomode = hpt366_set_piomode, |
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.set_dmamode = hpt366_set_dmamode, |
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}; |
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/** |
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* hpt36x_init_chipset - common chip setup |
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* @dev: PCI device |
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* |
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* Perform the chip setup work that must be done at both init and |
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* resume time |
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*/ |
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static void hpt36x_init_chipset(struct pci_dev *dev) |
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{ |
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u8 drive_fast; |
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pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, (L1_CACHE_BYTES / 4)); |
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pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x78); |
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pci_write_config_byte(dev, PCI_MIN_GNT, 0x08); |
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pci_write_config_byte(dev, PCI_MAX_LAT, 0x08); |
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pci_read_config_byte(dev, 0x51, &drive_fast); |
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if (drive_fast & 0x80) |
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pci_write_config_byte(dev, 0x51, drive_fast & ~0x80); |
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} |
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/** |
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* hpt36x_init_one - Initialise an HPT366/368 |
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* @dev: PCI device |
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* @id: Entry in match table |
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* |
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* Initialise an HPT36x device. There are some interesting complications |
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* here. Firstly the chip may report 366 and be one of several variants. |
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* Secondly all the timings depend on the clock for the chip which we must |
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* detect and look up |
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* |
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* This is the known chip mappings. It may be missing a couple of later |
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* releases. |
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* |
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* Chip version PCI Rev Notes |
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* HPT366 4 (HPT366) 0 UDMA66 |
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* HPT366 4 (HPT366) 1 UDMA66 |
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* HPT368 4 (HPT366) 2 UDMA66 |
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* HPT37x/30x 4 (HPT366) 3+ Other driver |
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* |
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*/ |
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static int hpt36x_init_one(struct pci_dev *dev, const struct pci_device_id *id) |
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{ |
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static const struct ata_port_info info_hpt366 = { |
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.flags = ATA_FLAG_SLAVE_POSS, |
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.pio_mask = ATA_PIO4, |
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.mwdma_mask = ATA_MWDMA2, |
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.udma_mask = ATA_UDMA4, |
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.port_ops = &hpt366_port_ops |
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}; |
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const struct ata_port_info *ppi[] = { &info_hpt366, NULL }; |
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const void *hpriv = NULL; |
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u32 reg1; |
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int rc; |
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rc = pcim_enable_device(dev); |
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if (rc) |
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return rc; |
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/* May be a later chip in disguise. Check */ |
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/* Newer chips are not in the HPT36x driver. Ignore them */ |
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if (dev->revision > 2) |
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return -ENODEV; |
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hpt36x_init_chipset(dev); |
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pci_read_config_dword(dev, 0x40, ®1); |
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/* PCI clocking determines the ATA timing values to use */ |
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/* info_hpt366 is safe against re-entry so we can scribble on it */ |
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switch ((reg1 & 0xf00) >> 8) { |
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case 9: |
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hpriv = &hpt366_40; |
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break; |
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case 5: |
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hpriv = &hpt366_25; |
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break; |
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default: |
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hpriv = &hpt366_33; |
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break; |
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} |
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/* Now kick off ATA set up */ |
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return ata_pci_bmdma_init_one(dev, ppi, &hpt36x_sht, (void *)hpriv, 0); |
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} |
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#ifdef CONFIG_PM_SLEEP |
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static int hpt36x_reinit_one(struct pci_dev *dev) |
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{ |
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struct ata_host *host = pci_get_drvdata(dev); |
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int rc; |
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rc = ata_pci_device_do_resume(dev); |
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if (rc) |
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return rc; |
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hpt36x_init_chipset(dev); |
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ata_host_resume(host); |
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return 0; |
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} |
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#endif |
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static const struct pci_device_id hpt36x[] = { |
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{ PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT366), }, |
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{ }, |
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}; |
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static struct pci_driver hpt36x_pci_driver = { |
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.name = DRV_NAME, |
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.id_table = hpt36x, |
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.probe = hpt36x_init_one, |
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.remove = ata_pci_remove_one, |
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#ifdef CONFIG_PM_SLEEP |
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.suspend = ata_pci_device_suspend, |
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.resume = hpt36x_reinit_one, |
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#endif |
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}; |
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module_pci_driver(hpt36x_pci_driver); |
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MODULE_AUTHOR("Alan Cox"); |
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MODULE_DESCRIPTION("low-level driver for the Highpoint HPT366/368"); |
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MODULE_LICENSE("GPL"); |
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MODULE_DEVICE_TABLE(pci, hpt36x); |
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MODULE_VERSION(DRV_VERSION);
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