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320 lines
8.7 KiB
320 lines
8.7 KiB
// SPDX-License-Identifier: GPL-2.0-only |
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/* |
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* pata_atiixp.c - ATI PATA for new ATA layer |
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* (C) 2005 Red Hat Inc |
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* (C) 2009-2010 Bartlomiej Zolnierkiewicz |
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* |
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* Based on |
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* |
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* linux/drivers/ide/pci/atiixp.c Version 0.01-bart2 Feb. 26, 2004 |
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* |
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* Copyright (C) 2003 ATI Inc. <[email protected]> |
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* Copyright (C) 2004 Bartlomiej Zolnierkiewicz |
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* |
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*/ |
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#include <linux/kernel.h> |
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#include <linux/module.h> |
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#include <linux/pci.h> |
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#include <linux/blkdev.h> |
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#include <linux/delay.h> |
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#include <scsi/scsi_host.h> |
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#include <linux/libata.h> |
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#include <linux/dmi.h> |
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#define DRV_NAME "pata_atiixp" |
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#define DRV_VERSION "0.4.6" |
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enum { |
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ATIIXP_IDE_PIO_TIMING = 0x40, |
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ATIIXP_IDE_MWDMA_TIMING = 0x44, |
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ATIIXP_IDE_PIO_CONTROL = 0x48, |
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ATIIXP_IDE_PIO_MODE = 0x4a, |
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ATIIXP_IDE_UDMA_CONTROL = 0x54, |
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ATIIXP_IDE_UDMA_MODE = 0x56 |
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}; |
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static const struct dmi_system_id attixp_cable_override_dmi_table[] = { |
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{ |
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/* Board has onboard PATA<->SATA converters */ |
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.ident = "MSI E350DM-E33", |
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.matches = { |
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DMI_MATCH(DMI_BOARD_VENDOR, "MSI"), |
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DMI_MATCH(DMI_BOARD_NAME, "E350DM-E33(MS-7720)"), |
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}, |
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}, |
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{ } |
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}; |
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static int atiixp_cable_detect(struct ata_port *ap) |
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{ |
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struct pci_dev *pdev = to_pci_dev(ap->host->dev); |
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u8 udma; |
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if (dmi_check_system(attixp_cable_override_dmi_table)) |
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return ATA_CBL_PATA40_SHORT; |
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/* Hack from drivers/ide/pci. Really we want to know how to do the |
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raw detection not play follow the bios mode guess */ |
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pci_read_config_byte(pdev, ATIIXP_IDE_UDMA_MODE + ap->port_no, &udma); |
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if ((udma & 0x07) >= 0x04 || (udma & 0x70) >= 0x40) |
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return ATA_CBL_PATA80; |
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return ATA_CBL_PATA40; |
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} |
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static DEFINE_SPINLOCK(atiixp_lock); |
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/** |
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* atiixp_prereset - perform reset handling |
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* @link: ATA link |
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* @deadline: deadline jiffies for the operation |
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* |
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* Reset sequence checking enable bits to see which ports are |
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* active. |
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*/ |
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static int atiixp_prereset(struct ata_link *link, unsigned long deadline) |
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{ |
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static const struct pci_bits atiixp_enable_bits[] = { |
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{ 0x48, 1, 0x01, 0x00 }, |
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{ 0x48, 1, 0x08, 0x00 } |
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}; |
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struct ata_port *ap = link->ap; |
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struct pci_dev *pdev = to_pci_dev(ap->host->dev); |
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if (!pci_test_config_bits(pdev, &atiixp_enable_bits[ap->port_no])) |
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return -ENOENT; |
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return ata_sff_prereset(link, deadline); |
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} |
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/** |
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* atiixp_set_pio_timing - set initial PIO mode data |
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* @ap: ATA interface |
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* @adev: ATA device |
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* @pio: Requested PIO |
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* |
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* Called by both the pio and dma setup functions to set the controller |
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* timings for PIO transfers. We must load both the mode number and |
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* timing values into the controller. |
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*/ |
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static void atiixp_set_pio_timing(struct ata_port *ap, struct ata_device *adev, int pio) |
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{ |
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static u8 pio_timings[5] = { 0x5D, 0x47, 0x34, 0x22, 0x20 }; |
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struct pci_dev *pdev = to_pci_dev(ap->host->dev); |
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int dn = 2 * ap->port_no + adev->devno; |
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int timing_shift = (16 * ap->port_no) + 8 * (adev->devno ^ 1); |
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u32 pio_timing_data; |
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u16 pio_mode_data; |
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pci_read_config_word(pdev, ATIIXP_IDE_PIO_MODE, &pio_mode_data); |
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pio_mode_data &= ~(0x7 << (4 * dn)); |
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pio_mode_data |= pio << (4 * dn); |
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pci_write_config_word(pdev, ATIIXP_IDE_PIO_MODE, pio_mode_data); |
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pci_read_config_dword(pdev, ATIIXP_IDE_PIO_TIMING, &pio_timing_data); |
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pio_timing_data &= ~(0xFF << timing_shift); |
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pio_timing_data |= (pio_timings[pio] << timing_shift); |
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pci_write_config_dword(pdev, ATIIXP_IDE_PIO_TIMING, pio_timing_data); |
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} |
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/** |
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* atiixp_set_piomode - set initial PIO mode data |
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* @ap: ATA interface |
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* @adev: ATA device |
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* |
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* Called to do the PIO mode setup. We use a shared helper for this |
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* as the DMA setup must also adjust the PIO timing information. |
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*/ |
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static void atiixp_set_piomode(struct ata_port *ap, struct ata_device *adev) |
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{ |
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unsigned long flags; |
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spin_lock_irqsave(&atiixp_lock, flags); |
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atiixp_set_pio_timing(ap, adev, adev->pio_mode - XFER_PIO_0); |
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spin_unlock_irqrestore(&atiixp_lock, flags); |
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} |
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/** |
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* atiixp_set_dmamode - set initial DMA mode data |
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* @ap: ATA interface |
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* @adev: ATA device |
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* |
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* Called to do the DMA mode setup. We use timing tables for most |
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* modes but must tune an appropriate PIO mode to match. |
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*/ |
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static void atiixp_set_dmamode(struct ata_port *ap, struct ata_device *adev) |
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{ |
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static u8 mwdma_timings[5] = { 0x77, 0x21, 0x20 }; |
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struct pci_dev *pdev = to_pci_dev(ap->host->dev); |
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int dma = adev->dma_mode; |
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int dn = 2 * ap->port_no + adev->devno; |
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int wanted_pio; |
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unsigned long flags; |
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spin_lock_irqsave(&atiixp_lock, flags); |
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if (adev->dma_mode >= XFER_UDMA_0) { |
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u16 udma_mode_data; |
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dma -= XFER_UDMA_0; |
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pci_read_config_word(pdev, ATIIXP_IDE_UDMA_MODE, &udma_mode_data); |
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udma_mode_data &= ~(0x7 << (4 * dn)); |
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udma_mode_data |= dma << (4 * dn); |
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pci_write_config_word(pdev, ATIIXP_IDE_UDMA_MODE, udma_mode_data); |
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} else { |
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int timing_shift = (16 * ap->port_no) + 8 * (adev->devno ^ 1); |
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u32 mwdma_timing_data; |
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dma -= XFER_MW_DMA_0; |
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pci_read_config_dword(pdev, ATIIXP_IDE_MWDMA_TIMING, |
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&mwdma_timing_data); |
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mwdma_timing_data &= ~(0xFF << timing_shift); |
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mwdma_timing_data |= (mwdma_timings[dma] << timing_shift); |
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pci_write_config_dword(pdev, ATIIXP_IDE_MWDMA_TIMING, |
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mwdma_timing_data); |
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} |
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/* |
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* We must now look at the PIO mode situation. We may need to |
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* adjust the PIO mode to keep the timings acceptable |
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*/ |
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if (adev->dma_mode >= XFER_MW_DMA_2) |
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wanted_pio = 4; |
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else if (adev->dma_mode == XFER_MW_DMA_1) |
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wanted_pio = 3; |
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else if (adev->dma_mode == XFER_MW_DMA_0) |
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wanted_pio = 0; |
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else BUG(); |
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if (adev->pio_mode != wanted_pio) |
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atiixp_set_pio_timing(ap, adev, wanted_pio); |
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spin_unlock_irqrestore(&atiixp_lock, flags); |
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} |
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/** |
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* atiixp_bmdma_start - DMA start callback |
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* @qc: Command in progress |
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* |
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* When DMA begins we need to ensure that the UDMA control |
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* register for the channel is correctly set. |
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* |
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* Note: The host lock held by the libata layer protects |
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* us from two channels both trying to set DMA bits at once |
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*/ |
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static void atiixp_bmdma_start(struct ata_queued_cmd *qc) |
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{ |
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struct ata_port *ap = qc->ap; |
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struct ata_device *adev = qc->dev; |
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struct pci_dev *pdev = to_pci_dev(ap->host->dev); |
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int dn = (2 * ap->port_no) + adev->devno; |
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u16 tmp16; |
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pci_read_config_word(pdev, ATIIXP_IDE_UDMA_CONTROL, &tmp16); |
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if (ata_using_udma(adev)) |
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tmp16 |= (1 << dn); |
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else |
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tmp16 &= ~(1 << dn); |
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pci_write_config_word(pdev, ATIIXP_IDE_UDMA_CONTROL, tmp16); |
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ata_bmdma_start(qc); |
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} |
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/** |
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* atiixp_bmdma_stop - DMA stop callback |
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* @qc: Command in progress |
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* |
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* DMA has completed. Clear the UDMA flag as the next operations will |
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* be PIO ones not UDMA data transfer. |
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* |
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* Note: The host lock held by the libata layer protects |
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* us from two channels both trying to set DMA bits at once |
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*/ |
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static void atiixp_bmdma_stop(struct ata_queued_cmd *qc) |
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{ |
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struct ata_port *ap = qc->ap; |
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struct pci_dev *pdev = to_pci_dev(ap->host->dev); |
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int dn = (2 * ap->port_no) + qc->dev->devno; |
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u16 tmp16; |
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pci_read_config_word(pdev, ATIIXP_IDE_UDMA_CONTROL, &tmp16); |
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tmp16 &= ~(1 << dn); |
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pci_write_config_word(pdev, ATIIXP_IDE_UDMA_CONTROL, tmp16); |
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ata_bmdma_stop(qc); |
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} |
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static struct scsi_host_template atiixp_sht = { |
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ATA_BASE_SHT(DRV_NAME), |
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.sg_tablesize = LIBATA_DUMB_MAX_PRD, |
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.dma_boundary = ATA_DMA_BOUNDARY, |
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}; |
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static struct ata_port_operations atiixp_port_ops = { |
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.inherits = &ata_bmdma_port_ops, |
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.qc_prep = ata_bmdma_dumb_qc_prep, |
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.bmdma_start = atiixp_bmdma_start, |
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.bmdma_stop = atiixp_bmdma_stop, |
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.prereset = atiixp_prereset, |
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.cable_detect = atiixp_cable_detect, |
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.set_piomode = atiixp_set_piomode, |
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.set_dmamode = atiixp_set_dmamode, |
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}; |
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static int atiixp_init_one(struct pci_dev *pdev, const struct pci_device_id *id) |
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{ |
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static const struct ata_port_info info = { |
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.flags = ATA_FLAG_SLAVE_POSS, |
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.pio_mask = ATA_PIO4, |
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.mwdma_mask = ATA_MWDMA12_ONLY, |
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.udma_mask = ATA_UDMA5, |
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.port_ops = &atiixp_port_ops |
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}; |
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const struct ata_port_info *ppi[] = { &info, &info }; |
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/* SB600 doesn't have secondary port wired */ |
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if (pdev->device == PCI_DEVICE_ID_ATI_IXP600_IDE) |
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ppi[1] = &ata_dummy_port_info; |
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return ata_pci_bmdma_init_one(pdev, ppi, &atiixp_sht, NULL, |
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ATA_HOST_PARALLEL_SCAN); |
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} |
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static const struct pci_device_id atiixp[] = { |
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{ PCI_VDEVICE(ATI, PCI_DEVICE_ID_ATI_IXP200_IDE), }, |
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{ PCI_VDEVICE(ATI, PCI_DEVICE_ID_ATI_IXP300_IDE), }, |
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{ PCI_VDEVICE(ATI, PCI_DEVICE_ID_ATI_IXP400_IDE), }, |
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{ PCI_VDEVICE(ATI, PCI_DEVICE_ID_ATI_IXP600_IDE), }, |
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{ PCI_VDEVICE(ATI, PCI_DEVICE_ID_ATI_IXP700_IDE), }, |
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{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_HUDSON2_IDE), }, |
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{ }, |
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}; |
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static struct pci_driver atiixp_pci_driver = { |
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.name = DRV_NAME, |
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.id_table = atiixp, |
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.probe = atiixp_init_one, |
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.remove = ata_pci_remove_one, |
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#ifdef CONFIG_PM_SLEEP |
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.resume = ata_pci_device_resume, |
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.suspend = ata_pci_device_suspend, |
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#endif |
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}; |
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module_pci_driver(atiixp_pci_driver); |
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MODULE_AUTHOR("Alan Cox"); |
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MODULE_DESCRIPTION("low-level driver for ATI IXP200/300/400"); |
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MODULE_LICENSE("GPL"); |
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MODULE_DEVICE_TABLE(pci, atiixp); |
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MODULE_VERSION(DRV_VERSION);
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