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156 lines
3.4 KiB
156 lines
3.4 KiB
// SPDX-License-Identifier: GPL-2.0-only |
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/* |
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* Copyright (C) 2004 Matthew Wilcox <[email protected]> |
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* Copyright (C) 2004 Intel Corp. |
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*/ |
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/* |
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* mmconfig.c - Low-level direct PCI config space access via MMCONFIG |
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*/ |
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#include <linux/pci.h> |
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#include <linux/init.h> |
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#include <linux/rcupdate.h> |
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#include <asm/e820/api.h> |
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#include <asm/pci_x86.h> |
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/* Assume systems with more busses have correct MCFG */ |
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#define mmcfg_virt_addr ((void __iomem *) fix_to_virt(FIX_PCIE_MCFG)) |
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/* The base address of the last MMCONFIG device accessed */ |
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static u32 mmcfg_last_accessed_device; |
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static int mmcfg_last_accessed_cpu; |
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/* |
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* Functions for accessing PCI configuration space with MMCONFIG accesses |
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*/ |
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static u32 get_base_addr(unsigned int seg, int bus, unsigned devfn) |
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{ |
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struct pci_mmcfg_region *cfg = pci_mmconfig_lookup(seg, bus); |
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if (cfg) |
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return cfg->address; |
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return 0; |
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} |
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/* |
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* This is always called under pci_config_lock |
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*/ |
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static void pci_exp_set_dev_base(unsigned int base, int bus, int devfn) |
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{ |
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u32 dev_base = base | PCI_MMCFG_BUS_OFFSET(bus) | (devfn << 12); |
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int cpu = smp_processor_id(); |
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if (dev_base != mmcfg_last_accessed_device || |
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cpu != mmcfg_last_accessed_cpu) { |
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mmcfg_last_accessed_device = dev_base; |
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mmcfg_last_accessed_cpu = cpu; |
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set_fixmap_nocache(FIX_PCIE_MCFG, dev_base); |
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} |
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} |
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static int pci_mmcfg_read(unsigned int seg, unsigned int bus, |
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unsigned int devfn, int reg, int len, u32 *value) |
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{ |
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unsigned long flags; |
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u32 base; |
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if ((bus > 255) || (devfn > 255) || (reg > 4095)) { |
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err: *value = -1; |
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return -EINVAL; |
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} |
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rcu_read_lock(); |
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base = get_base_addr(seg, bus, devfn); |
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if (!base) { |
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rcu_read_unlock(); |
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goto err; |
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} |
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raw_spin_lock_irqsave(&pci_config_lock, flags); |
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pci_exp_set_dev_base(base, bus, devfn); |
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switch (len) { |
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case 1: |
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*value = mmio_config_readb(mmcfg_virt_addr + reg); |
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break; |
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case 2: |
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*value = mmio_config_readw(mmcfg_virt_addr + reg); |
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break; |
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case 4: |
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*value = mmio_config_readl(mmcfg_virt_addr + reg); |
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break; |
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} |
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raw_spin_unlock_irqrestore(&pci_config_lock, flags); |
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rcu_read_unlock(); |
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return 0; |
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} |
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static int pci_mmcfg_write(unsigned int seg, unsigned int bus, |
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unsigned int devfn, int reg, int len, u32 value) |
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{ |
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unsigned long flags; |
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u32 base; |
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if ((bus > 255) || (devfn > 255) || (reg > 4095)) |
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return -EINVAL; |
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rcu_read_lock(); |
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base = get_base_addr(seg, bus, devfn); |
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if (!base) { |
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rcu_read_unlock(); |
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return -EINVAL; |
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} |
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raw_spin_lock_irqsave(&pci_config_lock, flags); |
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pci_exp_set_dev_base(base, bus, devfn); |
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switch (len) { |
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case 1: |
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mmio_config_writeb(mmcfg_virt_addr + reg, value); |
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break; |
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case 2: |
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mmio_config_writew(mmcfg_virt_addr + reg, value); |
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break; |
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case 4: |
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mmio_config_writel(mmcfg_virt_addr + reg, value); |
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break; |
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} |
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raw_spin_unlock_irqrestore(&pci_config_lock, flags); |
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rcu_read_unlock(); |
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return 0; |
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} |
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const struct pci_raw_ops pci_mmcfg = { |
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.read = pci_mmcfg_read, |
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.write = pci_mmcfg_write, |
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}; |
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int __init pci_mmcfg_arch_init(void) |
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{ |
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printk(KERN_INFO "PCI: Using MMCONFIG for extended config space\n"); |
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raw_pci_ext_ops = &pci_mmcfg; |
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return 1; |
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} |
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void __init pci_mmcfg_arch_free(void) |
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{ |
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} |
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int pci_mmcfg_arch_map(struct pci_mmcfg_region *cfg) |
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{ |
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return 0; |
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} |
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void pci_mmcfg_arch_unmap(struct pci_mmcfg_region *cfg) |
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{ |
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unsigned long flags; |
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/* Invalidate the cached mmcfg map entry. */ |
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raw_spin_lock_irqsave(&pci_config_lock, flags); |
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mmcfg_last_accessed_device = 0; |
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raw_spin_unlock_irqrestore(&pci_config_lock, flags); |
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}
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