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826 lines
27 KiB
826 lines
27 KiB
// SPDX-License-Identifier: GPL-2.0 |
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/* |
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* Exceptions for specific devices. Usually work-arounds for fatal design flaws. |
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*/ |
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#include <linux/delay.h> |
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#include <linux/dmi.h> |
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#include <linux/pci.h> |
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#include <linux/vgaarb.h> |
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#include <asm/hpet.h> |
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#include <asm/pci_x86.h> |
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static void pci_fixup_i450nx(struct pci_dev *d) |
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{ |
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/* |
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* i450NX -- Find and scan all secondary buses on all PXB's. |
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*/ |
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int pxb, reg; |
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u8 busno, suba, subb; |
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dev_warn(&d->dev, "Searching for i450NX host bridges\n"); |
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reg = 0xd0; |
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for(pxb = 0; pxb < 2; pxb++) { |
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pci_read_config_byte(d, reg++, &busno); |
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pci_read_config_byte(d, reg++, &suba); |
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pci_read_config_byte(d, reg++, &subb); |
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dev_dbg(&d->dev, "i450NX PXB %d: %02x/%02x/%02x\n", pxb, busno, |
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suba, subb); |
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if (busno) |
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pcibios_scan_root(busno); /* Bus A */ |
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if (suba < subb) |
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pcibios_scan_root(suba+1); /* Bus B */ |
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} |
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pcibios_last_bus = -1; |
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} |
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82451NX, pci_fixup_i450nx); |
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static void pci_fixup_i450gx(struct pci_dev *d) |
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{ |
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/* |
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* i450GX and i450KX -- Find and scan all secondary buses. |
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* (called separately for each PCI bridge found) |
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*/ |
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u8 busno; |
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pci_read_config_byte(d, 0x4a, &busno); |
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dev_info(&d->dev, "i440KX/GX host bridge; secondary bus %02x\n", busno); |
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pcibios_scan_root(busno); |
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pcibios_last_bus = -1; |
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} |
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454GX, pci_fixup_i450gx); |
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static void pci_fixup_umc_ide(struct pci_dev *d) |
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{ |
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/* |
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* UM8886BF IDE controller sets region type bits incorrectly, |
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* therefore they look like memory despite of them being I/O. |
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*/ |
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int i; |
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dev_warn(&d->dev, "Fixing base address flags\n"); |
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for(i = 0; i < 4; i++) |
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d->resource[i].flags |= PCI_BASE_ADDRESS_SPACE_IO; |
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} |
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_UMC, PCI_DEVICE_ID_UMC_UM8886BF, pci_fixup_umc_ide); |
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static void pci_fixup_latency(struct pci_dev *d) |
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{ |
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/* |
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* SiS 5597 and 5598 chipsets require latency timer set to |
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* at most 32 to avoid lockups. |
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*/ |
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dev_dbg(&d->dev, "Setting max latency to 32\n"); |
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pcibios_max_latency = 32; |
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} |
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5597, pci_fixup_latency); |
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5598, pci_fixup_latency); |
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static void pci_fixup_piix4_acpi(struct pci_dev *d) |
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{ |
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/* |
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* PIIX4 ACPI device: hardwired IRQ9 |
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*/ |
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d->irq = 9; |
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} |
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3, pci_fixup_piix4_acpi); |
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/* |
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* Addresses issues with problems in the memory write queue timer in |
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* certain VIA Northbridges. This bugfix is per VIA's specifications, |
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* except for the KL133/KM133: clearing bit 5 on those Northbridges seems |
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* to trigger a bug in its integrated ProSavage video card, which |
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* causes screen corruption. We only clear bits 6 and 7 for that chipset, |
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* until VIA can provide us with definitive information on why screen |
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* corruption occurs, and what exactly those bits do. |
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* |
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* VIA 8363,8622,8361 Northbridges: |
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* - bits 5, 6, 7 at offset 0x55 need to be turned off |
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* VIA 8367 (KT266x) Northbridges: |
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* - bits 5, 6, 7 at offset 0x95 need to be turned off |
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* VIA 8363 rev 0x81/0x84 (KL133/KM133) Northbridges: |
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* - bits 6, 7 at offset 0x55 need to be turned off |
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*/ |
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#define VIA_8363_KL133_REVISION_ID 0x81 |
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#define VIA_8363_KM133_REVISION_ID 0x84 |
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static void pci_fixup_via_northbridge_bug(struct pci_dev *d) |
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{ |
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u8 v; |
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int where = 0x55; |
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int mask = 0x1f; /* clear bits 5, 6, 7 by default */ |
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if (d->device == PCI_DEVICE_ID_VIA_8367_0) { |
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/* fix pci bus latency issues resulted by NB bios error |
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it appears on bug free^Wreduced kt266x's bios forces |
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NB latency to zero */ |
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pci_write_config_byte(d, PCI_LATENCY_TIMER, 0); |
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where = 0x95; /* the memory write queue timer register is |
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different for the KT266x's: 0x95 not 0x55 */ |
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} else if (d->device == PCI_DEVICE_ID_VIA_8363_0 && |
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(d->revision == VIA_8363_KL133_REVISION_ID || |
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d->revision == VIA_8363_KM133_REVISION_ID)) { |
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mask = 0x3f; /* clear only bits 6 and 7; clearing bit 5 |
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causes screen corruption on the KL133/KM133 */ |
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} |
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pci_read_config_byte(d, where, &v); |
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if (v & ~mask) { |
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dev_warn(&d->dev, "Disabling VIA memory write queue (PCI ID %04x, rev %02x): [%02x] %02x & %02x -> %02x\n", \ |
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d->device, d->revision, where, v, mask, v & mask); |
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v &= mask; |
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pci_write_config_byte(d, where, v); |
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} |
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} |
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, pci_fixup_via_northbridge_bug); |
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8622, pci_fixup_via_northbridge_bug); |
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, pci_fixup_via_northbridge_bug); |
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8367_0, pci_fixup_via_northbridge_bug); |
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DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, pci_fixup_via_northbridge_bug); |
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DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8622, pci_fixup_via_northbridge_bug); |
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DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, pci_fixup_via_northbridge_bug); |
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DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8367_0, pci_fixup_via_northbridge_bug); |
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/* |
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* For some reasons Intel decided that certain parts of their |
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* 815, 845 and some other chipsets must look like PCI-to-PCI bridges |
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* while they are obviously not. The 82801 family (AA, AB, BAM/CAM, |
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* BA/CA/DB and E) PCI bridges are actually HUB-to-PCI ones, according |
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* to Intel terminology. These devices do forward all addresses from |
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* system to PCI bus no matter what are their window settings, so they are |
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* "transparent" (or subtractive decoding) from programmers point of view. |
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*/ |
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static void pci_fixup_transparent_bridge(struct pci_dev *dev) |
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{ |
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if ((dev->device & 0xff00) == 0x2400) |
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dev->transparent = 1; |
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} |
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DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_INTEL, PCI_ANY_ID, |
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PCI_CLASS_BRIDGE_PCI, 8, pci_fixup_transparent_bridge); |
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/* |
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* Fixup for C1 Halt Disconnect problem on nForce2 systems. |
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* |
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* From information provided by "Allen Martin" <[email protected]>: |
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* |
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* A hang is caused when the CPU generates a very fast CONNECT/HALT cycle |
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* sequence. Workaround is to set the SYSTEM_IDLE_TIMEOUT to 80 ns. |
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* This allows the state-machine and timer to return to a proper state within |
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* 80 ns of the CONNECT and probe appearing together. Since the CPU will not |
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* issue another HALT within 80 ns of the initial HALT, the failure condition |
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* is avoided. |
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*/ |
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static void pci_fixup_nforce2(struct pci_dev *dev) |
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{ |
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u32 val; |
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/* |
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* Chip Old value New value |
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* C17 0x1F0FFF01 0x1F01FF01 |
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* C18D 0x9F0FFF01 0x9F01FF01 |
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* |
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* Northbridge chip version may be determined by |
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* reading the PCI revision ID (0xC1 or greater is C18D). |
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*/ |
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pci_read_config_dword(dev, 0x6c, &val); |
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/* |
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* Apply fixup if needed, but don't touch disconnect state |
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*/ |
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if ((val & 0x00FF0000) != 0x00010000) { |
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dev_warn(&dev->dev, "nForce2 C1 Halt Disconnect fixup\n"); |
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pci_write_config_dword(dev, 0x6c, (val & 0xFF00FFFF) | 0x00010000); |
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} |
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} |
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE2, pci_fixup_nforce2); |
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DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE2, pci_fixup_nforce2); |
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/* Max PCI Express root ports */ |
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#define MAX_PCIEROOT 6 |
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static int quirk_aspm_offset[MAX_PCIEROOT << 3]; |
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#define GET_INDEX(a, b) ((((a) - PCI_DEVICE_ID_INTEL_MCH_PA) << 3) + ((b) & 7)) |
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static int quirk_pcie_aspm_read(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *value) |
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{ |
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return raw_pci_read(pci_domain_nr(bus), bus->number, |
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devfn, where, size, value); |
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} |
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/* |
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* Replace the original pci bus ops for write with a new one that will filter |
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* the request to insure ASPM cannot be enabled. |
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*/ |
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static int quirk_pcie_aspm_write(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 value) |
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{ |
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u8 offset; |
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offset = quirk_aspm_offset[GET_INDEX(bus->self->device, devfn)]; |
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if ((offset) && (where == offset)) |
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value = value & ~PCI_EXP_LNKCTL_ASPMC; |
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return raw_pci_write(pci_domain_nr(bus), bus->number, |
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devfn, where, size, value); |
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} |
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static struct pci_ops quirk_pcie_aspm_ops = { |
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.read = quirk_pcie_aspm_read, |
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.write = quirk_pcie_aspm_write, |
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}; |
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/* |
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* Prevents PCI Express ASPM (Active State Power Management) being enabled. |
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* |
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* Save the register offset, where the ASPM control bits are located, |
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* for each PCI Express device that is in the device list of |
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* the root port in an array for fast indexing. Replace the bus ops |
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* with the modified one. |
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*/ |
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static void pcie_rootport_aspm_quirk(struct pci_dev *pdev) |
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{ |
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int i; |
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struct pci_bus *pbus; |
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struct pci_dev *dev; |
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if ((pbus = pdev->subordinate) == NULL) |
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return; |
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/* |
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* Check if the DID of pdev matches one of the six root ports. This |
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* check is needed in the case this function is called directly by the |
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* hot-plug driver. |
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*/ |
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if ((pdev->device < PCI_DEVICE_ID_INTEL_MCH_PA) || |
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(pdev->device > PCI_DEVICE_ID_INTEL_MCH_PC1)) |
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return; |
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if (list_empty(&pbus->devices)) { |
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/* |
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* If no device is attached to the root port at power-up or |
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* after hot-remove, the pbus->devices is empty and this code |
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* will set the offsets to zero and the bus ops to parent's bus |
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* ops, which is unmodified. |
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*/ |
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for (i = GET_INDEX(pdev->device, 0); i <= GET_INDEX(pdev->device, 7); ++i) |
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quirk_aspm_offset[i] = 0; |
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pci_bus_set_ops(pbus, pbus->parent->ops); |
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} else { |
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/* |
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* If devices are attached to the root port at power-up or |
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* after hot-add, the code loops through the device list of |
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* each root port to save the register offsets and replace the |
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* bus ops. |
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*/ |
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list_for_each_entry(dev, &pbus->devices, bus_list) |
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/* There are 0 to 8 devices attached to this bus */ |
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quirk_aspm_offset[GET_INDEX(pdev->device, dev->devfn)] = |
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dev->pcie_cap + PCI_EXP_LNKCTL; |
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pci_bus_set_ops(pbus, &quirk_pcie_aspm_ops); |
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dev_info(&pbus->dev, "writes to ASPM control bits will be ignored\n"); |
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} |
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} |
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DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_MCH_PA, pcie_rootport_aspm_quirk); |
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DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_MCH_PA1, pcie_rootport_aspm_quirk); |
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DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_MCH_PB, pcie_rootport_aspm_quirk); |
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DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_MCH_PB1, pcie_rootport_aspm_quirk); |
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DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_MCH_PC, pcie_rootport_aspm_quirk); |
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DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_MCH_PC1, pcie_rootport_aspm_quirk); |
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/* |
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* Fixup to mark boot BIOS video selected by BIOS before it changes |
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* |
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* From information provided by "Jon Smirl" <[email protected]> |
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* |
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* The standard boot ROM sequence for an x86 machine uses the BIOS |
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* to select an initial video card for boot display. This boot video |
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* card will have its BIOS copied to 0xC0000 in system RAM. |
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* IORESOURCE_ROM_SHADOW is used to associate the boot video |
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* card with this copy. On laptops this copy has to be used since |
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* the main ROM may be compressed or combined with another image. |
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* See pci_map_rom() for use of this flag. Before marking the device |
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* with IORESOURCE_ROM_SHADOW check if a vga_default_device is already set |
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* by either arch code or vga-arbitration; if so only apply the fixup to this |
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* already-determined primary video card. |
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*/ |
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static void pci_fixup_video(struct pci_dev *pdev) |
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{ |
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struct pci_dev *bridge; |
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struct pci_bus *bus; |
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u16 config; |
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struct resource *res; |
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/* Is VGA routed to us? */ |
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bus = pdev->bus; |
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while (bus) { |
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bridge = bus->self; |
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/* |
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* From information provided by |
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* "David Miller" <[email protected]> |
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* The bridge control register is valid for PCI header |
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* type BRIDGE, or CARDBUS. Host to PCI controllers use |
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* PCI header type NORMAL. |
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*/ |
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if (bridge && (pci_is_bridge(bridge))) { |
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pci_read_config_word(bridge, PCI_BRIDGE_CONTROL, |
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&config); |
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if (!(config & PCI_BRIDGE_CTL_VGA)) |
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return; |
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} |
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bus = bus->parent; |
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} |
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if (!vga_default_device() || pdev == vga_default_device()) { |
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pci_read_config_word(pdev, PCI_COMMAND, &config); |
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if (config & (PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) { |
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res = &pdev->resource[PCI_ROM_RESOURCE]; |
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pci_disable_rom(pdev); |
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if (res->parent) |
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release_resource(res); |
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res->start = 0xC0000; |
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res->end = res->start + 0x20000 - 1; |
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res->flags = IORESOURCE_MEM | IORESOURCE_ROM_SHADOW | |
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IORESOURCE_PCI_FIXED; |
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dev_info(&pdev->dev, "Video device with shadowed ROM at %pR\n", |
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res); |
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} |
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} |
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} |
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DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_ANY_ID, PCI_ANY_ID, |
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PCI_CLASS_DISPLAY_VGA, 8, pci_fixup_video); |
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static const struct dmi_system_id msi_k8t_dmi_table[] = { |
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{ |
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.ident = "MSI-K8T-Neo2Fir", |
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.matches = { |
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DMI_MATCH(DMI_SYS_VENDOR, "MSI"), |
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DMI_MATCH(DMI_PRODUCT_NAME, "MS-6702E"), |
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}, |
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}, |
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{} |
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}; |
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|
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/* |
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* The AMD-Athlon64 board MSI "K8T Neo2-FIR" disables the onboard sound |
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* card if a PCI-soundcard is added. |
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* |
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* The BIOS only gives options "DISABLED" and "AUTO". This code sets |
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* the corresponding register-value to enable the soundcard. |
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* |
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* The soundcard is only enabled, if the mainboard is identified |
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* via DMI-tables and the soundcard is detected to be off. |
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*/ |
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static void pci_fixup_msi_k8t_onboard_sound(struct pci_dev *dev) |
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{ |
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unsigned char val; |
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if (!dmi_check_system(msi_k8t_dmi_table)) |
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return; /* only applies to MSI K8T Neo2-FIR */ |
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pci_read_config_byte(dev, 0x50, &val); |
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if (val & 0x40) { |
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pci_write_config_byte(dev, 0x50, val & (~0x40)); |
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|
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/* verify the change for status output */ |
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pci_read_config_byte(dev, 0x50, &val); |
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if (val & 0x40) |
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dev_info(&dev->dev, "Detected MSI K8T Neo2-FIR; " |
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"can't enable onboard soundcard!\n"); |
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else |
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dev_info(&dev->dev, "Detected MSI K8T Neo2-FIR; " |
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"enabled onboard soundcard\n"); |
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} |
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} |
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, |
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pci_fixup_msi_k8t_onboard_sound); |
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DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, |
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pci_fixup_msi_k8t_onboard_sound); |
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|
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/* |
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* Some Toshiba laptops need extra code to enable their TI TSB43AB22/A. |
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* |
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* We pretend to bring them out of full D3 state, and restore the proper |
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* IRQ, PCI cache line size, and BARs, otherwise the device won't function |
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* properly. In some cases, the device will generate an interrupt on |
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* the wrong IRQ line, causing any devices sharing the line it's |
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* *supposed* to use to be disabled by the kernel's IRQ debug code. |
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*/ |
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static u16 toshiba_line_size; |
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|
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static const struct dmi_system_id toshiba_ohci1394_dmi_table[] = { |
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{ |
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.ident = "Toshiba PS5 based laptop", |
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.matches = { |
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DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), |
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DMI_MATCH(DMI_PRODUCT_VERSION, "PS5"), |
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}, |
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}, |
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{ |
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.ident = "Toshiba PSM4 based laptop", |
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.matches = { |
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DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), |
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DMI_MATCH(DMI_PRODUCT_VERSION, "PSM4"), |
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}, |
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}, |
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{ |
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.ident = "Toshiba A40 based laptop", |
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.matches = { |
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DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), |
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DMI_MATCH(DMI_PRODUCT_VERSION, "PSA40U"), |
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}, |
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}, |
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{ } |
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}; |
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|
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static void pci_pre_fixup_toshiba_ohci1394(struct pci_dev *dev) |
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{ |
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if (!dmi_check_system(toshiba_ohci1394_dmi_table)) |
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return; /* only applies to certain Toshibas (so far) */ |
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|
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dev->current_state = PCI_D3cold; |
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pci_read_config_word(dev, PCI_CACHE_LINE_SIZE, &toshiba_line_size); |
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} |
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TI, 0x8032, |
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pci_pre_fixup_toshiba_ohci1394); |
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|
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static void pci_post_fixup_toshiba_ohci1394(struct pci_dev *dev) |
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{ |
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if (!dmi_check_system(toshiba_ohci1394_dmi_table)) |
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return; /* only applies to certain Toshibas (so far) */ |
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|
|
/* Restore config space on Toshiba laptops */ |
|
pci_write_config_word(dev, PCI_CACHE_LINE_SIZE, toshiba_line_size); |
|
pci_read_config_byte(dev, PCI_INTERRUPT_LINE, (u8 *)&dev->irq); |
|
pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, |
|
pci_resource_start(dev, 0)); |
|
pci_write_config_dword(dev, PCI_BASE_ADDRESS_1, |
|
pci_resource_start(dev, 1)); |
|
} |
|
DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_TI, 0x8032, |
|
pci_post_fixup_toshiba_ohci1394); |
|
|
|
|
|
/* |
|
* Prevent the BIOS trapping accesses to the Cyrix CS5530A video device |
|
* configuration space. |
|
*/ |
|
static void pci_early_fixup_cyrix_5530(struct pci_dev *dev) |
|
{ |
|
u8 r; |
|
/* clear 'F4 Video Configuration Trap' bit */ |
|
pci_read_config_byte(dev, 0x42, &r); |
|
r &= 0xfd; |
|
pci_write_config_byte(dev, 0x42, r); |
|
} |
|
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_5530_LEGACY, |
|
pci_early_fixup_cyrix_5530); |
|
DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_5530_LEGACY, |
|
pci_early_fixup_cyrix_5530); |
|
|
|
/* |
|
* Siemens Nixdorf AG FSC Multiprocessor Interrupt Controller: |
|
* prevent update of the BAR0, which doesn't look like a normal BAR. |
|
*/ |
|
static void pci_siemens_interrupt_controller(struct pci_dev *dev) |
|
{ |
|
dev->resource[0].flags |= IORESOURCE_PCI_FIXED; |
|
} |
|
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SIEMENS, 0x0015, |
|
pci_siemens_interrupt_controller); |
|
|
|
/* |
|
* SB600: Disable BAR1 on device 14.0 to avoid HPET resources from |
|
* confusing the PCI engine: |
|
*/ |
|
static void sb600_disable_hpet_bar(struct pci_dev *dev) |
|
{ |
|
u8 val; |
|
|
|
/* |
|
* The SB600 and SB700 both share the same device |
|
* ID, but the PM register 0x55 does something different |
|
* for the SB700, so make sure we are dealing with the |
|
* SB600 before touching the bit: |
|
*/ |
|
|
|
pci_read_config_byte(dev, 0x08, &val); |
|
|
|
if (val < 0x2F) { |
|
outb(0x55, 0xCD6); |
|
val = inb(0xCD7); |
|
|
|
/* Set bit 7 in PM register 0x55 */ |
|
outb(0x55, 0xCD6); |
|
outb(val | 0x80, 0xCD7); |
|
} |
|
} |
|
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_ATI, 0x4385, sb600_disable_hpet_bar); |
|
|
|
#ifdef CONFIG_HPET_TIMER |
|
static void sb600_hpet_quirk(struct pci_dev *dev) |
|
{ |
|
struct resource *r = &dev->resource[1]; |
|
|
|
if (r->flags & IORESOURCE_MEM && r->start == hpet_address) { |
|
r->flags |= IORESOURCE_PCI_FIXED; |
|
dev_info(&dev->dev, "reg 0x14 contains HPET; making it immovable\n"); |
|
} |
|
} |
|
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, 0x4385, sb600_hpet_quirk); |
|
#endif |
|
|
|
/* |
|
* Twinhead H12Y needs us to block out a region otherwise we map devices |
|
* there and any access kills the box. |
|
* |
|
* See: https://bugzilla.kernel.org/show_bug.cgi?id=10231 |
|
* |
|
* Match off the LPC and svid/sdid (older kernels lose the bridge subvendor) |
|
*/ |
|
static void twinhead_reserve_killing_zone(struct pci_dev *dev) |
|
{ |
|
if (dev->subsystem_vendor == 0x14FF && dev->subsystem_device == 0xA003) { |
|
pr_info("Reserving memory on Twinhead H12Y\n"); |
|
request_mem_region(0xFFB00000, 0x100000, "twinhead"); |
|
} |
|
} |
|
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x27B9, twinhead_reserve_killing_zone); |
|
|
|
/* |
|
* Device [8086:2fc0] |
|
* Erratum HSE43 |
|
* CONFIG_TDP_NOMINAL CSR Implemented at Incorrect Offset |
|
* https://www.intel.com/content/www/us/en/processors/xeon/xeon-e5-v3-spec-update.html |
|
* |
|
* Devices [8086:6f60,6fa0,6fc0] |
|
* Erratum BDF2 |
|
* PCI BARs in the Home Agent Will Return Non-Zero Values During Enumeration |
|
* https://www.intel.com/content/www/us/en/processors/xeon/xeon-e5-v4-spec-update.html |
|
*/ |
|
static void pci_invalid_bar(struct pci_dev *dev) |
|
{ |
|
dev->non_compliant_bars = 1; |
|
} |
|
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x2fc0, pci_invalid_bar); |
|
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x6f60, pci_invalid_bar); |
|
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x6fa0, pci_invalid_bar); |
|
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x6fc0, pci_invalid_bar); |
|
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0xa1ec, pci_invalid_bar); |
|
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0xa1ed, pci_invalid_bar); |
|
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0xa26c, pci_invalid_bar); |
|
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0xa26d, pci_invalid_bar); |
|
|
|
/* |
|
* Device [1022:7808] |
|
* 23. USB Wake on Connect/Disconnect with Low Speed Devices |
|
* https://support.amd.com/TechDocs/46837.pdf |
|
* Appendix A2 |
|
* https://support.amd.com/TechDocs/42413.pdf |
|
*/ |
|
static void pci_fixup_amd_ehci_pme(struct pci_dev *dev) |
|
{ |
|
dev_info(&dev->dev, "PME# does not work under D3, disabling it\n"); |
|
dev->pme_support &= ~((PCI_PM_CAP_PME_D3hot | PCI_PM_CAP_PME_D3cold) |
|
>> PCI_PM_CAP_PME_SHIFT); |
|
} |
|
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x7808, pci_fixup_amd_ehci_pme); |
|
|
|
/* |
|
* Device [1022:7914] |
|
* When in D0, PME# doesn't get asserted when plugging USB 2.0 device. |
|
*/ |
|
static void pci_fixup_amd_fch_xhci_pme(struct pci_dev *dev) |
|
{ |
|
dev_info(&dev->dev, "PME# does not work under D0, disabling it\n"); |
|
dev->pme_support &= ~(PCI_PM_CAP_PME_D0 >> PCI_PM_CAP_PME_SHIFT); |
|
} |
|
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x7914, pci_fixup_amd_fch_xhci_pme); |
|
|
|
/* |
|
* Apple MacBook Pro: Avoid [mem 0x7fa00000-0x7fbfffff] |
|
* |
|
* Using the [mem 0x7fa00000-0x7fbfffff] region, e.g., by assigning it to |
|
* the 00:1c.0 Root Port, causes a conflict with [io 0x1804], which is used |
|
* for soft poweroff and suspend-to-RAM. |
|
* |
|
* As far as we know, this is related to the address space, not to the Root |
|
* Port itself. Attaching the quirk to the Root Port is a convenience, but |
|
* it could probably also be a standalone DMI quirk. |
|
* |
|
* https://bugzilla.kernel.org/show_bug.cgi?id=103211 |
|
*/ |
|
static void quirk_apple_mbp_poweroff(struct pci_dev *pdev) |
|
{ |
|
struct device *dev = &pdev->dev; |
|
struct resource *res; |
|
|
|
if ((!dmi_match(DMI_PRODUCT_NAME, "MacBookPro11,4") && |
|
!dmi_match(DMI_PRODUCT_NAME, "MacBookPro11,5")) || |
|
pdev->bus->number != 0 || pdev->devfn != PCI_DEVFN(0x1c, 0)) |
|
return; |
|
|
|
res = request_mem_region(0x7fa00000, 0x200000, |
|
"MacBook Pro poweroff workaround"); |
|
if (res) |
|
dev_info(dev, "claimed %s %pR\n", res->name, res); |
|
else |
|
dev_info(dev, "can't work around MacBook Pro poweroff issue\n"); |
|
} |
|
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x8c10, quirk_apple_mbp_poweroff); |
|
|
|
/* |
|
* VMD-enabled root ports will change the source ID for all messages |
|
* to the VMD device. Rather than doing device matching with the source |
|
* ID, the AER driver should traverse the child device tree, reading |
|
* AER registers to find the faulting device. |
|
*/ |
|
static void quirk_no_aersid(struct pci_dev *pdev) |
|
{ |
|
/* VMD Domain */ |
|
if (is_vmd(pdev->bus) && pci_is_root_bus(pdev->bus)) |
|
pdev->bus->bus_flags |= PCI_BUS_FLAGS_NO_AERSID; |
|
} |
|
DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, PCI_ANY_ID, |
|
PCI_CLASS_BRIDGE_PCI, 8, quirk_no_aersid); |
|
|
|
static void quirk_intel_th_dnv(struct pci_dev *dev) |
|
{ |
|
struct resource *r = &dev->resource[4]; |
|
|
|
/* |
|
* Denverton reports 2k of RTIT_BAR (intel_th resource 4), which |
|
* appears to be 4 MB in reality. |
|
*/ |
|
if (r->end == r->start + 0x7ff) { |
|
r->start = 0; |
|
r->end = 0x3fffff; |
|
r->flags |= IORESOURCE_UNSET; |
|
} |
|
} |
|
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x19e1, quirk_intel_th_dnv); |
|
|
|
#ifdef CONFIG_PHYS_ADDR_T_64BIT |
|
|
|
#define AMD_141b_MMIO_BASE(x) (0x80 + (x) * 0x8) |
|
#define AMD_141b_MMIO_BASE_RE_MASK BIT(0) |
|
#define AMD_141b_MMIO_BASE_WE_MASK BIT(1) |
|
#define AMD_141b_MMIO_BASE_MMIOBASE_MASK GENMASK(31,8) |
|
|
|
#define AMD_141b_MMIO_LIMIT(x) (0x84 + (x) * 0x8) |
|
#define AMD_141b_MMIO_LIMIT_MMIOLIMIT_MASK GENMASK(31,8) |
|
|
|
#define AMD_141b_MMIO_HIGH(x) (0x180 + (x) * 0x4) |
|
#define AMD_141b_MMIO_HIGH_MMIOBASE_MASK GENMASK(7,0) |
|
#define AMD_141b_MMIO_HIGH_MMIOLIMIT_SHIFT 16 |
|
#define AMD_141b_MMIO_HIGH_MMIOLIMIT_MASK GENMASK(23,16) |
|
|
|
/* |
|
* The PCI Firmware Spec, rev 3.2, notes that ACPI should optionally allow |
|
* configuring host bridge windows using the _PRS and _SRS methods. |
|
* |
|
* But this is rarely implemented, so we manually enable a large 64bit BAR for |
|
* PCIe device on AMD Family 15h (Models 00h-1fh, 30h-3fh, 60h-7fh) Processors |
|
* here. |
|
*/ |
|
static void pci_amd_enable_64bit_bar(struct pci_dev *dev) |
|
{ |
|
static const char *name = "PCI Bus 0000:00"; |
|
struct resource *res, *conflict; |
|
u32 base, limit, high; |
|
struct pci_dev *other; |
|
unsigned i; |
|
|
|
if (!(pci_probe & PCI_BIG_ROOT_WINDOW)) |
|
return; |
|
|
|
/* Check that we are the only device of that type */ |
|
other = pci_get_device(dev->vendor, dev->device, NULL); |
|
if (other != dev || |
|
(other = pci_get_device(dev->vendor, dev->device, other))) { |
|
/* This is a multi-socket system, don't touch it for now */ |
|
pci_dev_put(other); |
|
return; |
|
} |
|
|
|
for (i = 0; i < 8; i++) { |
|
pci_read_config_dword(dev, AMD_141b_MMIO_BASE(i), &base); |
|
pci_read_config_dword(dev, AMD_141b_MMIO_HIGH(i), &high); |
|
|
|
/* Is this slot free? */ |
|
if (!(base & (AMD_141b_MMIO_BASE_RE_MASK | |
|
AMD_141b_MMIO_BASE_WE_MASK))) |
|
break; |
|
|
|
base >>= 8; |
|
base |= high << 24; |
|
|
|
/* Abort if a slot already configures a 64bit BAR. */ |
|
if (base > 0x10000) |
|
return; |
|
} |
|
if (i == 8) |
|
return; |
|
|
|
res = kzalloc(sizeof(*res), GFP_KERNEL); |
|
if (!res) |
|
return; |
|
|
|
/* |
|
* Allocate a 256GB window directly below the 0xfd00000000 hardware |
|
* limit (see AMD Family 15h Models 30h-3Fh BKDG, sec 2.4.6). |
|
*/ |
|
res->name = name; |
|
res->flags = IORESOURCE_PREFETCH | IORESOURCE_MEM | |
|
IORESOURCE_MEM_64 | IORESOURCE_WINDOW; |
|
res->start = 0xbd00000000ull; |
|
res->end = 0xfd00000000ull - 1; |
|
|
|
conflict = request_resource_conflict(&iomem_resource, res); |
|
if (conflict) { |
|
kfree(res); |
|
if (conflict->name != name) |
|
return; |
|
|
|
/* We are resuming from suspend; just reenable the window */ |
|
res = conflict; |
|
} else { |
|
dev_info(&dev->dev, "adding root bus resource %pR (tainting kernel)\n", |
|
res); |
|
add_taint(TAINT_FIRMWARE_WORKAROUND, LOCKDEP_STILL_OK); |
|
pci_bus_add_resource(dev->bus, res, 0); |
|
} |
|
|
|
base = ((res->start >> 8) & AMD_141b_MMIO_BASE_MMIOBASE_MASK) | |
|
AMD_141b_MMIO_BASE_RE_MASK | AMD_141b_MMIO_BASE_WE_MASK; |
|
limit = ((res->end + 1) >> 8) & AMD_141b_MMIO_LIMIT_MMIOLIMIT_MASK; |
|
high = ((res->start >> 40) & AMD_141b_MMIO_HIGH_MMIOBASE_MASK) | |
|
((((res->end + 1) >> 40) << AMD_141b_MMIO_HIGH_MMIOLIMIT_SHIFT) |
|
& AMD_141b_MMIO_HIGH_MMIOLIMIT_MASK); |
|
|
|
pci_write_config_dword(dev, AMD_141b_MMIO_HIGH(i), high); |
|
pci_write_config_dword(dev, AMD_141b_MMIO_LIMIT(i), limit); |
|
pci_write_config_dword(dev, AMD_141b_MMIO_BASE(i), base); |
|
} |
|
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x1401, pci_amd_enable_64bit_bar); |
|
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x141b, pci_amd_enable_64bit_bar); |
|
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x1571, pci_amd_enable_64bit_bar); |
|
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x15b1, pci_amd_enable_64bit_bar); |
|
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x1601, pci_amd_enable_64bit_bar); |
|
DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, 0x1401, pci_amd_enable_64bit_bar); |
|
DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, 0x141b, pci_amd_enable_64bit_bar); |
|
DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, 0x1571, pci_amd_enable_64bit_bar); |
|
DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, 0x15b1, pci_amd_enable_64bit_bar); |
|
DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, 0x1601, pci_amd_enable_64bit_bar); |
|
|
|
#define RS690_LOWER_TOP_OF_DRAM2 0x30 |
|
#define RS690_LOWER_TOP_OF_DRAM2_VALID 0x1 |
|
#define RS690_UPPER_TOP_OF_DRAM2 0x31 |
|
#define RS690_HTIU_NB_INDEX 0xA8 |
|
#define RS690_HTIU_NB_INDEX_WR_ENABLE 0x100 |
|
#define RS690_HTIU_NB_DATA 0xAC |
|
|
|
/* |
|
* Some BIOS implementations support RAM above 4GB, but do not configure the |
|
* PCI host to respond to bus master accesses for these addresses. These |
|
* implementations set the TOP_OF_DRAM_SLOT1 register correctly, so PCI DMA |
|
* works as expected for addresses below 4GB. |
|
* |
|
* Reference: "AMD RS690 ASIC Family Register Reference Guide" (pg. 2-57) |
|
* https://www.amd.com/system/files/TechDocs/43372_rs690_rrg_3.00o.pdf |
|
*/ |
|
static void rs690_fix_64bit_dma(struct pci_dev *pdev) |
|
{ |
|
u32 val = 0; |
|
phys_addr_t top_of_dram = __pa(high_memory - 1) + 1; |
|
|
|
if (top_of_dram <= (1ULL << 32)) |
|
return; |
|
|
|
pci_write_config_dword(pdev, RS690_HTIU_NB_INDEX, |
|
RS690_LOWER_TOP_OF_DRAM2); |
|
pci_read_config_dword(pdev, RS690_HTIU_NB_DATA, &val); |
|
|
|
if (val) |
|
return; |
|
|
|
pci_info(pdev, "Adjusting top of DRAM to %pa for 64-bit DMA support\n", &top_of_dram); |
|
|
|
pci_write_config_dword(pdev, RS690_HTIU_NB_INDEX, |
|
RS690_UPPER_TOP_OF_DRAM2 | RS690_HTIU_NB_INDEX_WR_ENABLE); |
|
pci_write_config_dword(pdev, RS690_HTIU_NB_DATA, top_of_dram >> 32); |
|
|
|
pci_write_config_dword(pdev, RS690_HTIU_NB_INDEX, |
|
RS690_LOWER_TOP_OF_DRAM2 | RS690_HTIU_NB_INDEX_WR_ENABLE); |
|
pci_write_config_dword(pdev, RS690_HTIU_NB_DATA, |
|
top_of_dram | RS690_LOWER_TOP_OF_DRAM2_VALID); |
|
} |
|
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x7910, rs690_fix_64bit_dma); |
|
|
|
#endif
|
|
|