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609 lines
15 KiB
609 lines
15 KiB
// SPDX-License-Identifier: GPL-2.0 |
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/* |
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* Low-Level PCI Express Support for the SH7786 |
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* |
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* Copyright (C) 2009 - 2011 Paul Mundt |
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*/ |
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#define pr_fmt(fmt) "PCI: " fmt |
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#include <linux/pci.h> |
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#include <linux/init.h> |
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#include <linux/kernel.h> |
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#include <linux/io.h> |
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#include <linux/async.h> |
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#include <linux/delay.h> |
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#include <linux/dma-map-ops.h> |
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#include <linux/slab.h> |
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#include <linux/clk.h> |
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#include <linux/sh_clk.h> |
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#include <linux/sh_intc.h> |
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#include <cpu/sh7786.h> |
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#include "pcie-sh7786.h" |
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#include <linux/sizes.h> |
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struct sh7786_pcie_port { |
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struct pci_channel *hose; |
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struct clk *fclk, phy_clk; |
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unsigned int index; |
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int endpoint; |
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int link; |
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}; |
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static struct sh7786_pcie_port *sh7786_pcie_ports; |
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static unsigned int nr_ports; |
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static unsigned long dma_pfn_offset; |
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size_t memsize; |
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u64 memstart; |
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static struct sh7786_pcie_hwops { |
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int (*core_init)(void); |
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async_func_t port_init_hw; |
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} *sh7786_pcie_hwops; |
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static struct resource sh7786_pci0_resources[] = { |
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{ |
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.name = "PCIe0 MEM 0", |
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.start = 0xfd000000, |
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.end = 0xfd000000 + SZ_8M - 1, |
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.flags = IORESOURCE_MEM, |
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}, { |
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.name = "PCIe0 MEM 1", |
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.start = 0xc0000000, |
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.end = 0xc0000000 + SZ_512M - 1, |
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.flags = IORESOURCE_MEM | IORESOURCE_MEM_32BIT, |
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}, { |
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.name = "PCIe0 MEM 2", |
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.start = 0x10000000, |
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.end = 0x10000000 + SZ_64M - 1, |
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.flags = IORESOURCE_MEM, |
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}, { |
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.name = "PCIe0 IO", |
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.start = 0xfe100000, |
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.end = 0xfe100000 + SZ_1M - 1, |
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.flags = IORESOURCE_IO, |
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}, |
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}; |
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static struct resource sh7786_pci1_resources[] = { |
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{ |
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.name = "PCIe1 MEM 0", |
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.start = 0xfd800000, |
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.end = 0xfd800000 + SZ_8M - 1, |
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.flags = IORESOURCE_MEM, |
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}, { |
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.name = "PCIe1 MEM 1", |
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.start = 0xa0000000, |
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.end = 0xa0000000 + SZ_512M - 1, |
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.flags = IORESOURCE_MEM | IORESOURCE_MEM_32BIT, |
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}, { |
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.name = "PCIe1 MEM 2", |
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.start = 0x30000000, |
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.end = 0x30000000 + SZ_256M - 1, |
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.flags = IORESOURCE_MEM | IORESOURCE_MEM_32BIT, |
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}, { |
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.name = "PCIe1 IO", |
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.start = 0xfe300000, |
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.end = 0xfe300000 + SZ_1M - 1, |
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.flags = IORESOURCE_IO, |
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}, |
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}; |
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static struct resource sh7786_pci2_resources[] = { |
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{ |
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.name = "PCIe2 MEM 0", |
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.start = 0xfc800000, |
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.end = 0xfc800000 + SZ_4M - 1, |
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.flags = IORESOURCE_MEM, |
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}, { |
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.name = "PCIe2 MEM 1", |
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.start = 0x80000000, |
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.end = 0x80000000 + SZ_512M - 1, |
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.flags = IORESOURCE_MEM | IORESOURCE_MEM_32BIT, |
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}, { |
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.name = "PCIe2 MEM 2", |
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.start = 0x20000000, |
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.end = 0x20000000 + SZ_256M - 1, |
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.flags = IORESOURCE_MEM | IORESOURCE_MEM_32BIT, |
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}, { |
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.name = "PCIe2 IO", |
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.start = 0xfcd00000, |
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.end = 0xfcd00000 + SZ_1M - 1, |
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.flags = IORESOURCE_IO, |
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}, |
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}; |
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extern struct pci_ops sh7786_pci_ops; |
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#define DEFINE_CONTROLLER(start, idx) \ |
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{ \ |
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.pci_ops = &sh7786_pci_ops, \ |
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.resources = sh7786_pci##idx##_resources, \ |
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.nr_resources = ARRAY_SIZE(sh7786_pci##idx##_resources), \ |
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.reg_base = start, \ |
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.mem_offset = 0, \ |
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.io_offset = 0, \ |
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} |
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static struct pci_channel sh7786_pci_channels[] = { |
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DEFINE_CONTROLLER(0xfe000000, 0), |
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DEFINE_CONTROLLER(0xfe200000, 1), |
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DEFINE_CONTROLLER(0xfcc00000, 2), |
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}; |
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static struct clk fixed_pciexclkp = { |
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.rate = 100000000, /* 100 MHz reference clock */ |
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}; |
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static void sh7786_pci_fixup(struct pci_dev *dev) |
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{ |
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/* |
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* Prevent enumeration of root complex resources. |
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*/ |
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if (pci_is_root_bus(dev->bus) && dev->devfn == 0) { |
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int i; |
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for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) { |
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dev->resource[i].start = 0; |
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dev->resource[i].end = 0; |
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dev->resource[i].flags = 0; |
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} |
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} |
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} |
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_RENESAS, PCI_DEVICE_ID_RENESAS_SH7786, |
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sh7786_pci_fixup); |
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static int __init phy_wait_for_ack(struct pci_channel *chan) |
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{ |
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unsigned int timeout = 100; |
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while (timeout--) { |
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if (pci_read_reg(chan, SH4A_PCIEPHYADRR) & (1 << BITS_ACK)) |
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return 0; |
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udelay(100); |
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} |
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return -ETIMEDOUT; |
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} |
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static int __init pci_wait_for_irq(struct pci_channel *chan, unsigned int mask) |
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{ |
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unsigned int timeout = 100; |
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while (timeout--) { |
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if ((pci_read_reg(chan, SH4A_PCIEINTR) & mask) == mask) |
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return 0; |
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udelay(100); |
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} |
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return -ETIMEDOUT; |
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} |
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static void __init phy_write_reg(struct pci_channel *chan, unsigned int addr, |
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unsigned int lane, unsigned int data) |
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{ |
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unsigned long phyaddr; |
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phyaddr = (1 << BITS_CMD) + ((lane & 0xf) << BITS_LANE) + |
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((addr & 0xff) << BITS_ADR); |
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/* Set write data */ |
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pci_write_reg(chan, data, SH4A_PCIEPHYDOUTR); |
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pci_write_reg(chan, phyaddr, SH4A_PCIEPHYADRR); |
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phy_wait_for_ack(chan); |
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/* Clear command */ |
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pci_write_reg(chan, 0, SH4A_PCIEPHYDOUTR); |
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pci_write_reg(chan, 0, SH4A_PCIEPHYADRR); |
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phy_wait_for_ack(chan); |
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} |
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static int __init pcie_clk_init(struct sh7786_pcie_port *port) |
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{ |
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struct pci_channel *chan = port->hose; |
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struct clk *clk; |
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char fclk_name[16]; |
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int ret; |
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/* |
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* First register the fixed clock |
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*/ |
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ret = clk_register(&fixed_pciexclkp); |
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if (unlikely(ret != 0)) |
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return ret; |
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/* |
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* Grab the port's function clock, which the PHY clock depends |
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* on. clock lookups don't help us much at this point, since no |
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* dev_id is available this early. Lame. |
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*/ |
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snprintf(fclk_name, sizeof(fclk_name), "pcie%d_fck", port->index); |
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port->fclk = clk_get(NULL, fclk_name); |
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if (IS_ERR(port->fclk)) { |
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ret = PTR_ERR(port->fclk); |
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goto err_fclk; |
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} |
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clk_enable(port->fclk); |
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/* |
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* And now, set up the PHY clock |
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*/ |
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clk = &port->phy_clk; |
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memset(clk, 0, sizeof(struct clk)); |
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clk->parent = &fixed_pciexclkp; |
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clk->enable_reg = (void __iomem *)(chan->reg_base + SH4A_PCIEPHYCTLR); |
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clk->enable_bit = BITS_CKE; |
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ret = sh_clk_mstp_register(clk, 1); |
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if (unlikely(ret < 0)) |
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goto err_phy; |
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return 0; |
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err_phy: |
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clk_disable(port->fclk); |
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clk_put(port->fclk); |
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err_fclk: |
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clk_unregister(&fixed_pciexclkp); |
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return ret; |
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} |
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static int __init phy_init(struct sh7786_pcie_port *port) |
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{ |
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struct pci_channel *chan = port->hose; |
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unsigned int timeout = 100; |
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clk_enable(&port->phy_clk); |
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/* Initialize the phy */ |
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phy_write_reg(chan, 0x60, 0xf, 0x004b008b); |
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phy_write_reg(chan, 0x61, 0xf, 0x00007b41); |
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phy_write_reg(chan, 0x64, 0xf, 0x00ff4f00); |
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phy_write_reg(chan, 0x65, 0xf, 0x09070907); |
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phy_write_reg(chan, 0x66, 0xf, 0x00000010); |
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phy_write_reg(chan, 0x74, 0xf, 0x0007001c); |
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phy_write_reg(chan, 0x79, 0xf, 0x01fc000d); |
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phy_write_reg(chan, 0xb0, 0xf, 0x00000610); |
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/* Deassert Standby */ |
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phy_write_reg(chan, 0x67, 0x1, 0x00000400); |
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/* Disable clock */ |
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clk_disable(&port->phy_clk); |
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while (timeout--) { |
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if (pci_read_reg(chan, SH4A_PCIEPHYSR)) |
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return 0; |
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udelay(100); |
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} |
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return -ETIMEDOUT; |
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} |
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static void __init pcie_reset(struct sh7786_pcie_port *port) |
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{ |
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struct pci_channel *chan = port->hose; |
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pci_write_reg(chan, 1, SH4A_PCIESRSTR); |
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pci_write_reg(chan, 0, SH4A_PCIETCTLR); |
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pci_write_reg(chan, 0, SH4A_PCIESRSTR); |
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pci_write_reg(chan, 0, SH4A_PCIETXVC0SR); |
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} |
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static int __init pcie_init(struct sh7786_pcie_port *port) |
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{ |
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struct pci_channel *chan = port->hose; |
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unsigned int data; |
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phys_addr_t memstart, memend; |
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int ret, i, win; |
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/* Begin initialization */ |
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pcie_reset(port); |
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/* |
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* Initial header for port config space is type 1, set the device |
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* class to match. Hardware takes care of propagating the IDSETR |
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* settings, so there is no need to bother with a quirk. |
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*/ |
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pci_write_reg(chan, PCI_CLASS_BRIDGE_PCI << 16, SH4A_PCIEIDSETR1); |
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/* Initialize default capabilities. */ |
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data = pci_read_reg(chan, SH4A_PCIEEXPCAP0); |
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data &= ~(PCI_EXP_FLAGS_TYPE << 16); |
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if (port->endpoint) |
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data |= PCI_EXP_TYPE_ENDPOINT << 20; |
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else |
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data |= PCI_EXP_TYPE_ROOT_PORT << 20; |
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data |= PCI_CAP_ID_EXP; |
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pci_write_reg(chan, data, SH4A_PCIEEXPCAP0); |
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/* Enable data link layer active state reporting */ |
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pci_write_reg(chan, PCI_EXP_LNKCAP_DLLLARC, SH4A_PCIEEXPCAP3); |
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/* Enable extended sync and ASPM L0s support */ |
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data = pci_read_reg(chan, SH4A_PCIEEXPCAP4); |
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data &= ~PCI_EXP_LNKCTL_ASPMC; |
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data |= PCI_EXP_LNKCTL_ES | 1; |
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pci_write_reg(chan, data, SH4A_PCIEEXPCAP4); |
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/* Write out the physical slot number */ |
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data = pci_read_reg(chan, SH4A_PCIEEXPCAP5); |
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data &= ~PCI_EXP_SLTCAP_PSN; |
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data |= (port->index + 1) << 19; |
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pci_write_reg(chan, data, SH4A_PCIEEXPCAP5); |
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/* Set the completion timer timeout to the maximum 32ms. */ |
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data = pci_read_reg(chan, SH4A_PCIETLCTLR); |
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data &= ~0x3f00; |
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data |= 0x32 << 8; |
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pci_write_reg(chan, data, SH4A_PCIETLCTLR); |
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/* |
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* Set fast training sequences to the maximum 255, |
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* and enable MAC data scrambling. |
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*/ |
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data = pci_read_reg(chan, SH4A_PCIEMACCTLR); |
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data &= ~PCIEMACCTLR_SCR_DIS; |
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data |= (0xff << 16); |
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pci_write_reg(chan, data, SH4A_PCIEMACCTLR); |
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memstart = __pa(memory_start); |
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memend = __pa(memory_end); |
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memsize = roundup_pow_of_two(memend - memstart); |
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/* |
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* The start address must be aligned on its size. So we round |
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* it down, and then recalculate the size so that it covers |
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* the entire memory. |
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*/ |
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memstart = ALIGN_DOWN(memstart, memsize); |
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memsize = roundup_pow_of_two(memend - memstart); |
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/* |
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* If there's more than 512MB of memory, we need to roll over to |
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* LAR1/LAMR1. |
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*/ |
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if (memsize > SZ_512M) { |
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pci_write_reg(chan, memstart + SZ_512M, SH4A_PCIELAR1); |
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pci_write_reg(chan, ((memsize - SZ_512M) - SZ_256) | 1, |
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SH4A_PCIELAMR1); |
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memsize = SZ_512M; |
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} else { |
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/* |
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* Otherwise just zero it out and disable it. |
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*/ |
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pci_write_reg(chan, 0, SH4A_PCIELAR1); |
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pci_write_reg(chan, 0, SH4A_PCIELAMR1); |
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} |
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/* |
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* LAR0/LAMR0 covers up to the first 512MB, which is enough to |
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* cover all of lowmem on most platforms. |
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*/ |
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pci_write_reg(chan, memstart, SH4A_PCIELAR0); |
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pci_write_reg(chan, (memsize - SZ_256) | 1, SH4A_PCIELAMR0); |
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/* Finish initialization */ |
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data = pci_read_reg(chan, SH4A_PCIETCTLR); |
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data |= 0x1; |
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pci_write_reg(chan, data, SH4A_PCIETCTLR); |
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/* Let things settle down a bit.. */ |
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mdelay(100); |
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/* Enable DL_Active Interrupt generation */ |
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data = pci_read_reg(chan, SH4A_PCIEDLINTENR); |
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data |= PCIEDLINTENR_DLL_ACT_ENABLE; |
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pci_write_reg(chan, data, SH4A_PCIEDLINTENR); |
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/* Disable MAC data scrambling. */ |
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data = pci_read_reg(chan, SH4A_PCIEMACCTLR); |
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data |= PCIEMACCTLR_SCR_DIS | (0xff << 16); |
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pci_write_reg(chan, data, SH4A_PCIEMACCTLR); |
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/* |
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* This will timeout if we don't have a link, but we permit the |
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* port to register anyways in order to support hotplug on future |
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* hardware. |
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*/ |
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ret = pci_wait_for_irq(chan, MASK_INT_TX_CTRL); |
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data = pci_read_reg(chan, SH4A_PCIEPCICONF1); |
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data &= ~(PCI_STATUS_DEVSEL_MASK << 16); |
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data |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | |
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(PCI_STATUS_CAP_LIST | PCI_STATUS_DEVSEL_FAST) << 16; |
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pci_write_reg(chan, data, SH4A_PCIEPCICONF1); |
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pci_write_reg(chan, 0x80888000, SH4A_PCIETXVC0DCTLR); |
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pci_write_reg(chan, 0x00222000, SH4A_PCIERXVC0DCTLR); |
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wmb(); |
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if (ret == 0) { |
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data = pci_read_reg(chan, SH4A_PCIEMACSR); |
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printk(KERN_NOTICE "PCI: PCIe#%d x%d link detected\n", |
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port->index, (data >> 20) & 0x3f); |
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} else |
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printk(KERN_NOTICE "PCI: PCIe#%d link down\n", |
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port->index); |
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for (i = win = 0; i < chan->nr_resources; i++) { |
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struct resource *res = chan->resources + i; |
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resource_size_t size; |
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u32 mask; |
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/* |
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* We can't use the 32-bit mode windows in legacy 29-bit |
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* mode, so just skip them entirely. |
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*/ |
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if ((res->flags & IORESOURCE_MEM_32BIT) && __in_29bit_mode()) |
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res->flags |= IORESOURCE_DISABLED; |
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if (res->flags & IORESOURCE_DISABLED) |
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continue; |
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pci_write_reg(chan, 0x00000000, SH4A_PCIEPTCTLR(win)); |
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/* |
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* The PAMR mask is calculated in units of 256kB, which |
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* keeps things pretty simple. |
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*/ |
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size = resource_size(res); |
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mask = (roundup_pow_of_two(size) / SZ_256K) - 1; |
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pci_write_reg(chan, mask << 18, SH4A_PCIEPAMR(win)); |
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pci_write_reg(chan, upper_32_bits(res->start), |
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SH4A_PCIEPARH(win)); |
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pci_write_reg(chan, lower_32_bits(res->start), |
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SH4A_PCIEPARL(win)); |
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mask = MASK_PARE; |
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if (res->flags & IORESOURCE_IO) |
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mask |= MASK_SPC; |
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pci_write_reg(chan, mask, SH4A_PCIEPTCTLR(win)); |
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win++; |
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} |
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return 0; |
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} |
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int pcibios_map_platform_irq(const struct pci_dev *pdev, u8 slot, u8 pin) |
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{ |
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return evt2irq(0xae0); |
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} |
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void pcibios_bus_add_device(struct pci_dev *pdev) |
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{ |
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dma_direct_set_offset(&pdev->dev, __pa(memory_start), |
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__pa(memory_start) - memstart, memsize); |
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} |
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static int __init sh7786_pcie_core_init(void) |
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{ |
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/* Return the number of ports */ |
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return test_mode_pin(MODE_PIN12) ? 3 : 2; |
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} |
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static void __init sh7786_pcie_init_hw(void *data, async_cookie_t cookie) |
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{ |
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struct sh7786_pcie_port *port = data; |
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int ret; |
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/* |
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* Check if we are configured in endpoint or root complex mode, |
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* this is a fixed pin setting that applies to all PCIe ports. |
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*/ |
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port->endpoint = test_mode_pin(MODE_PIN11); |
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/* |
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* Setup clocks, needed both for PHY and PCIe registers. |
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*/ |
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ret = pcie_clk_init(port); |
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if (unlikely(ret < 0)) { |
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pr_err("clock initialization failed for port#%d\n", |
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port->index); |
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return; |
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} |
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ret = phy_init(port); |
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if (unlikely(ret < 0)) { |
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pr_err("phy initialization failed for port#%d\n", |
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port->index); |
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return; |
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} |
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ret = pcie_init(port); |
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if (unlikely(ret < 0)) { |
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pr_err("core initialization failed for port#%d\n", |
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port->index); |
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return; |
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} |
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|
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/* In the interest of preserving device ordering, synchronize */ |
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async_synchronize_cookie(cookie); |
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|
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register_pci_controller(port->hose); |
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} |
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static struct sh7786_pcie_hwops sh7786_65nm_pcie_hwops __initdata = { |
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.core_init = sh7786_pcie_core_init, |
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.port_init_hw = sh7786_pcie_init_hw, |
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}; |
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|
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static int __init sh7786_pcie_init(void) |
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{ |
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struct clk *platclk; |
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u32 mm_sel; |
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int i; |
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|
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printk(KERN_NOTICE "PCI: Starting initialization.\n"); |
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|
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sh7786_pcie_hwops = &sh7786_65nm_pcie_hwops; |
|
|
|
nr_ports = sh7786_pcie_hwops->core_init(); |
|
BUG_ON(nr_ports > ARRAY_SIZE(sh7786_pci_channels)); |
|
|
|
if (unlikely(nr_ports == 0)) |
|
return -ENODEV; |
|
|
|
sh7786_pcie_ports = kcalloc(nr_ports, sizeof(struct sh7786_pcie_port), |
|
GFP_KERNEL); |
|
if (unlikely(!sh7786_pcie_ports)) |
|
return -ENOMEM; |
|
|
|
/* |
|
* Fetch any optional platform clock associated with this block. |
|
* |
|
* This is a rather nasty hack for boards with spec-mocking FPGAs |
|
* that have a secondary set of clocks outside of the on-chip |
|
* ones that need to be accounted for before there is any chance |
|
* of touching the existing MSTP bits or CPG clocks. |
|
*/ |
|
platclk = clk_get(NULL, "pcie_plat_clk"); |
|
if (IS_ERR(platclk)) { |
|
/* Sane hardware should probably get a WARN_ON.. */ |
|
platclk = NULL; |
|
} |
|
|
|
clk_enable(platclk); |
|
|
|
mm_sel = sh7786_mm_sel(); |
|
|
|
/* |
|
* Depending on the MMSELR register value, the PCIe0 MEM 1 |
|
* area may not be available. See Table 13.11 of the SH7786 |
|
* datasheet. |
|
*/ |
|
if (mm_sel != 1 && mm_sel != 2 && mm_sel != 5 && mm_sel != 6) |
|
sh7786_pci0_resources[2].flags |= IORESOURCE_DISABLED; |
|
|
|
printk(KERN_NOTICE "PCI: probing %d ports.\n", nr_ports); |
|
|
|
for (i = 0; i < nr_ports; i++) { |
|
struct sh7786_pcie_port *port = sh7786_pcie_ports + i; |
|
|
|
port->index = i; |
|
port->hose = sh7786_pci_channels + i; |
|
port->hose->io_map_base = port->hose->resources[0].start; |
|
|
|
async_schedule(sh7786_pcie_hwops->port_init_hw, port); |
|
} |
|
|
|
async_synchronize_full(); |
|
|
|
return 0; |
|
} |
|
arch_initcall(sh7786_pcie_init);
|
|
|