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1154 lines
28 KiB
1154 lines
28 KiB
// SPDX-License-Identifier: GPL-2.0 |
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/* BPF JIT compiler for RV64G |
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* |
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* Copyright(c) 2019 Björn Töpel <[email protected]> |
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* |
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*/ |
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|
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#include <linux/bpf.h> |
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#include <linux/filter.h> |
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#include "bpf_jit.h" |
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|
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#define RV_REG_TCC RV_REG_A6 |
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#define RV_REG_TCC_SAVED RV_REG_S6 /* Store A6 in S6 if program do calls */ |
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|
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static const int regmap[] = { |
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[BPF_REG_0] = RV_REG_A5, |
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[BPF_REG_1] = RV_REG_A0, |
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[BPF_REG_2] = RV_REG_A1, |
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[BPF_REG_3] = RV_REG_A2, |
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[BPF_REG_4] = RV_REG_A3, |
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[BPF_REG_5] = RV_REG_A4, |
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[BPF_REG_6] = RV_REG_S1, |
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[BPF_REG_7] = RV_REG_S2, |
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[BPF_REG_8] = RV_REG_S3, |
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[BPF_REG_9] = RV_REG_S4, |
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[BPF_REG_FP] = RV_REG_S5, |
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[BPF_REG_AX] = RV_REG_T0, |
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}; |
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enum { |
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RV_CTX_F_SEEN_TAIL_CALL = 0, |
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RV_CTX_F_SEEN_CALL = RV_REG_RA, |
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RV_CTX_F_SEEN_S1 = RV_REG_S1, |
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RV_CTX_F_SEEN_S2 = RV_REG_S2, |
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RV_CTX_F_SEEN_S3 = RV_REG_S3, |
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RV_CTX_F_SEEN_S4 = RV_REG_S4, |
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RV_CTX_F_SEEN_S5 = RV_REG_S5, |
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RV_CTX_F_SEEN_S6 = RV_REG_S6, |
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}; |
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static u8 bpf_to_rv_reg(int bpf_reg, struct rv_jit_context *ctx) |
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{ |
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u8 reg = regmap[bpf_reg]; |
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|
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switch (reg) { |
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case RV_CTX_F_SEEN_S1: |
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case RV_CTX_F_SEEN_S2: |
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case RV_CTX_F_SEEN_S3: |
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case RV_CTX_F_SEEN_S4: |
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case RV_CTX_F_SEEN_S5: |
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case RV_CTX_F_SEEN_S6: |
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__set_bit(reg, &ctx->flags); |
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} |
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return reg; |
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}; |
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static bool seen_reg(int reg, struct rv_jit_context *ctx) |
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{ |
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switch (reg) { |
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case RV_CTX_F_SEEN_CALL: |
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case RV_CTX_F_SEEN_S1: |
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case RV_CTX_F_SEEN_S2: |
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case RV_CTX_F_SEEN_S3: |
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case RV_CTX_F_SEEN_S4: |
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case RV_CTX_F_SEEN_S5: |
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case RV_CTX_F_SEEN_S6: |
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return test_bit(reg, &ctx->flags); |
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} |
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return false; |
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} |
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static void mark_fp(struct rv_jit_context *ctx) |
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{ |
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__set_bit(RV_CTX_F_SEEN_S5, &ctx->flags); |
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} |
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|
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static void mark_call(struct rv_jit_context *ctx) |
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{ |
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__set_bit(RV_CTX_F_SEEN_CALL, &ctx->flags); |
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} |
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static bool seen_call(struct rv_jit_context *ctx) |
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{ |
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return test_bit(RV_CTX_F_SEEN_CALL, &ctx->flags); |
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} |
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static void mark_tail_call(struct rv_jit_context *ctx) |
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{ |
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__set_bit(RV_CTX_F_SEEN_TAIL_CALL, &ctx->flags); |
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} |
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static bool seen_tail_call(struct rv_jit_context *ctx) |
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{ |
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return test_bit(RV_CTX_F_SEEN_TAIL_CALL, &ctx->flags); |
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} |
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static u8 rv_tail_call_reg(struct rv_jit_context *ctx) |
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{ |
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mark_tail_call(ctx); |
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|
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if (seen_call(ctx)) { |
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__set_bit(RV_CTX_F_SEEN_S6, &ctx->flags); |
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return RV_REG_S6; |
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} |
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return RV_REG_A6; |
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} |
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static bool is_32b_int(s64 val) |
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{ |
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return -(1L << 31) <= val && val < (1L << 31); |
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} |
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static bool in_auipc_jalr_range(s64 val) |
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{ |
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/* |
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* auipc+jalr can reach any signed PC-relative offset in the range |
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* [-2^31 - 2^11, 2^31 - 2^11). |
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*/ |
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return (-(1L << 31) - (1L << 11)) <= val && |
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val < ((1L << 31) - (1L << 11)); |
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} |
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static void emit_imm(u8 rd, s64 val, struct rv_jit_context *ctx) |
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{ |
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/* Note that the immediate from the add is sign-extended, |
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* which means that we need to compensate this by adding 2^12, |
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* when the 12th bit is set. A simpler way of doing this, and |
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* getting rid of the check, is to just add 2**11 before the |
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* shift. The "Loading a 32-Bit constant" example from the |
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* "Computer Organization and Design, RISC-V edition" book by |
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* Patterson/Hennessy highlights this fact. |
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* |
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* This also means that we need to process LSB to MSB. |
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*/ |
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s64 upper = (val + (1 << 11)) >> 12; |
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/* Sign-extend lower 12 bits to 64 bits since immediates for li, addiw, |
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* and addi are signed and RVC checks will perform signed comparisons. |
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*/ |
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s64 lower = ((val & 0xfff) << 52) >> 52; |
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int shift; |
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|
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if (is_32b_int(val)) { |
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if (upper) |
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emit_lui(rd, upper, ctx); |
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|
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if (!upper) { |
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emit_li(rd, lower, ctx); |
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return; |
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} |
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emit_addiw(rd, rd, lower, ctx); |
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return; |
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} |
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shift = __ffs(upper); |
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upper >>= shift; |
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shift += 12; |
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emit_imm(rd, upper, ctx); |
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emit_slli(rd, rd, shift, ctx); |
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if (lower) |
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emit_addi(rd, rd, lower, ctx); |
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} |
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static void __build_epilogue(bool is_tail_call, struct rv_jit_context *ctx) |
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{ |
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int stack_adjust = ctx->stack_size, store_offset = stack_adjust - 8; |
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|
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if (seen_reg(RV_REG_RA, ctx)) { |
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emit_ld(RV_REG_RA, store_offset, RV_REG_SP, ctx); |
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store_offset -= 8; |
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} |
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emit_ld(RV_REG_FP, store_offset, RV_REG_SP, ctx); |
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store_offset -= 8; |
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if (seen_reg(RV_REG_S1, ctx)) { |
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emit_ld(RV_REG_S1, store_offset, RV_REG_SP, ctx); |
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store_offset -= 8; |
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} |
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if (seen_reg(RV_REG_S2, ctx)) { |
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emit_ld(RV_REG_S2, store_offset, RV_REG_SP, ctx); |
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store_offset -= 8; |
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} |
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if (seen_reg(RV_REG_S3, ctx)) { |
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emit_ld(RV_REG_S3, store_offset, RV_REG_SP, ctx); |
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store_offset -= 8; |
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} |
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if (seen_reg(RV_REG_S4, ctx)) { |
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emit_ld(RV_REG_S4, store_offset, RV_REG_SP, ctx); |
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store_offset -= 8; |
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} |
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if (seen_reg(RV_REG_S5, ctx)) { |
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emit_ld(RV_REG_S5, store_offset, RV_REG_SP, ctx); |
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store_offset -= 8; |
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} |
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if (seen_reg(RV_REG_S6, ctx)) { |
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emit_ld(RV_REG_S6, store_offset, RV_REG_SP, ctx); |
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store_offset -= 8; |
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} |
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emit_addi(RV_REG_SP, RV_REG_SP, stack_adjust, ctx); |
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/* Set return value. */ |
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if (!is_tail_call) |
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emit_mv(RV_REG_A0, RV_REG_A5, ctx); |
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emit_jalr(RV_REG_ZERO, is_tail_call ? RV_REG_T3 : RV_REG_RA, |
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is_tail_call ? 4 : 0, /* skip TCC init */ |
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ctx); |
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} |
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static void emit_bcc(u8 cond, u8 rd, u8 rs, int rvoff, |
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struct rv_jit_context *ctx) |
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{ |
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switch (cond) { |
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case BPF_JEQ: |
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emit(rv_beq(rd, rs, rvoff >> 1), ctx); |
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return; |
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case BPF_JGT: |
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emit(rv_bltu(rs, rd, rvoff >> 1), ctx); |
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return; |
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case BPF_JLT: |
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emit(rv_bltu(rd, rs, rvoff >> 1), ctx); |
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return; |
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case BPF_JGE: |
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emit(rv_bgeu(rd, rs, rvoff >> 1), ctx); |
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return; |
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case BPF_JLE: |
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emit(rv_bgeu(rs, rd, rvoff >> 1), ctx); |
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return; |
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case BPF_JNE: |
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emit(rv_bne(rd, rs, rvoff >> 1), ctx); |
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return; |
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case BPF_JSGT: |
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emit(rv_blt(rs, rd, rvoff >> 1), ctx); |
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return; |
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case BPF_JSLT: |
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emit(rv_blt(rd, rs, rvoff >> 1), ctx); |
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return; |
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case BPF_JSGE: |
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emit(rv_bge(rd, rs, rvoff >> 1), ctx); |
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return; |
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case BPF_JSLE: |
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emit(rv_bge(rs, rd, rvoff >> 1), ctx); |
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} |
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} |
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static void emit_branch(u8 cond, u8 rd, u8 rs, int rvoff, |
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struct rv_jit_context *ctx) |
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{ |
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s64 upper, lower; |
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if (is_13b_int(rvoff)) { |
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emit_bcc(cond, rd, rs, rvoff, ctx); |
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return; |
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} |
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/* Adjust for jal */ |
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rvoff -= 4; |
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/* Transform, e.g.: |
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* bne rd,rs,foo |
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* to |
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* beq rd,rs,<.L1> |
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* (auipc foo) |
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* jal(r) foo |
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* .L1 |
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*/ |
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cond = invert_bpf_cond(cond); |
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if (is_21b_int(rvoff)) { |
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emit_bcc(cond, rd, rs, 8, ctx); |
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emit(rv_jal(RV_REG_ZERO, rvoff >> 1), ctx); |
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return; |
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} |
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/* 32b No need for an additional rvoff adjustment, since we |
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* get that from the auipc at PC', where PC = PC' + 4. |
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*/ |
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upper = (rvoff + (1 << 11)) >> 12; |
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lower = rvoff & 0xfff; |
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emit_bcc(cond, rd, rs, 12, ctx); |
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emit(rv_auipc(RV_REG_T1, upper), ctx); |
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emit(rv_jalr(RV_REG_ZERO, RV_REG_T1, lower), ctx); |
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} |
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static void emit_zext_32(u8 reg, struct rv_jit_context *ctx) |
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{ |
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emit_slli(reg, reg, 32, ctx); |
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emit_srli(reg, reg, 32, ctx); |
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} |
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static int emit_bpf_tail_call(int insn, struct rv_jit_context *ctx) |
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{ |
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int tc_ninsn, off, start_insn = ctx->ninsns; |
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u8 tcc = rv_tail_call_reg(ctx); |
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/* a0: &ctx |
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* a1: &array |
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* a2: index |
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* |
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* if (index >= array->map.max_entries) |
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* goto out; |
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*/ |
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tc_ninsn = insn ? ctx->offset[insn] - ctx->offset[insn - 1] : |
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ctx->offset[0]; |
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emit_zext_32(RV_REG_A2, ctx); |
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off = offsetof(struct bpf_array, map.max_entries); |
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if (is_12b_check(off, insn)) |
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return -1; |
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emit(rv_lwu(RV_REG_T1, off, RV_REG_A1), ctx); |
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off = ninsns_rvoff(tc_ninsn - (ctx->ninsns - start_insn)); |
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emit_branch(BPF_JGE, RV_REG_A2, RV_REG_T1, off, ctx); |
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/* if (TCC-- < 0) |
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* goto out; |
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*/ |
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emit_addi(RV_REG_T1, tcc, -1, ctx); |
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off = ninsns_rvoff(tc_ninsn - (ctx->ninsns - start_insn)); |
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emit_branch(BPF_JSLT, tcc, RV_REG_ZERO, off, ctx); |
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/* prog = array->ptrs[index]; |
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* if (!prog) |
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* goto out; |
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*/ |
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emit_slli(RV_REG_T2, RV_REG_A2, 3, ctx); |
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emit_add(RV_REG_T2, RV_REG_T2, RV_REG_A1, ctx); |
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off = offsetof(struct bpf_array, ptrs); |
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if (is_12b_check(off, insn)) |
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return -1; |
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emit_ld(RV_REG_T2, off, RV_REG_T2, ctx); |
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off = ninsns_rvoff(tc_ninsn - (ctx->ninsns - start_insn)); |
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emit_branch(BPF_JEQ, RV_REG_T2, RV_REG_ZERO, off, ctx); |
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|
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/* goto *(prog->bpf_func + 4); */ |
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off = offsetof(struct bpf_prog, bpf_func); |
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if (is_12b_check(off, insn)) |
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return -1; |
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emit_ld(RV_REG_T3, off, RV_REG_T2, ctx); |
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emit_mv(RV_REG_TCC, RV_REG_T1, ctx); |
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__build_epilogue(true, ctx); |
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return 0; |
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} |
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static void init_regs(u8 *rd, u8 *rs, const struct bpf_insn *insn, |
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struct rv_jit_context *ctx) |
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{ |
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u8 code = insn->code; |
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|
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switch (code) { |
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case BPF_JMP | BPF_JA: |
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case BPF_JMP | BPF_CALL: |
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case BPF_JMP | BPF_EXIT: |
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case BPF_JMP | BPF_TAIL_CALL: |
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break; |
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default: |
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*rd = bpf_to_rv_reg(insn->dst_reg, ctx); |
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} |
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|
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if (code & (BPF_ALU | BPF_X) || code & (BPF_ALU64 | BPF_X) || |
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code & (BPF_JMP | BPF_X) || code & (BPF_JMP32 | BPF_X) || |
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code & BPF_LDX || code & BPF_STX) |
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*rs = bpf_to_rv_reg(insn->src_reg, ctx); |
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} |
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static void emit_zext_32_rd_rs(u8 *rd, u8 *rs, struct rv_jit_context *ctx) |
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{ |
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emit_mv(RV_REG_T2, *rd, ctx); |
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emit_zext_32(RV_REG_T2, ctx); |
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emit_mv(RV_REG_T1, *rs, ctx); |
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emit_zext_32(RV_REG_T1, ctx); |
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*rd = RV_REG_T2; |
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*rs = RV_REG_T1; |
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} |
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|
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static void emit_sext_32_rd_rs(u8 *rd, u8 *rs, struct rv_jit_context *ctx) |
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{ |
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emit_addiw(RV_REG_T2, *rd, 0, ctx); |
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emit_addiw(RV_REG_T1, *rs, 0, ctx); |
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*rd = RV_REG_T2; |
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*rs = RV_REG_T1; |
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} |
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|
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static void emit_zext_32_rd_t1(u8 *rd, struct rv_jit_context *ctx) |
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{ |
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emit_mv(RV_REG_T2, *rd, ctx); |
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emit_zext_32(RV_REG_T2, ctx); |
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emit_zext_32(RV_REG_T1, ctx); |
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*rd = RV_REG_T2; |
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} |
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|
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static void emit_sext_32_rd(u8 *rd, struct rv_jit_context *ctx) |
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{ |
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emit_addiw(RV_REG_T2, *rd, 0, ctx); |
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*rd = RV_REG_T2; |
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} |
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|
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static int emit_jump_and_link(u8 rd, s64 rvoff, bool force_jalr, |
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struct rv_jit_context *ctx) |
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{ |
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s64 upper, lower; |
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|
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if (rvoff && is_21b_int(rvoff) && !force_jalr) { |
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emit(rv_jal(rd, rvoff >> 1), ctx); |
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return 0; |
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} else if (in_auipc_jalr_range(rvoff)) { |
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upper = (rvoff + (1 << 11)) >> 12; |
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lower = rvoff & 0xfff; |
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emit(rv_auipc(RV_REG_T1, upper), ctx); |
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emit(rv_jalr(rd, RV_REG_T1, lower), ctx); |
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return 0; |
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} |
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|
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pr_err("bpf-jit: target offset 0x%llx is out of range\n", rvoff); |
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return -ERANGE; |
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} |
|
|
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static bool is_signed_bpf_cond(u8 cond) |
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{ |
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return cond == BPF_JSGT || cond == BPF_JSLT || |
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cond == BPF_JSGE || cond == BPF_JSLE; |
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} |
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|
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static int emit_call(bool fixed, u64 addr, struct rv_jit_context *ctx) |
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{ |
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s64 off = 0; |
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u64 ip; |
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u8 rd; |
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int ret; |
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|
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if (addr && ctx->insns) { |
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ip = (u64)(long)(ctx->insns + ctx->ninsns); |
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off = addr - ip; |
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} |
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|
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ret = emit_jump_and_link(RV_REG_RA, off, !fixed, ctx); |
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if (ret) |
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return ret; |
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rd = bpf_to_rv_reg(BPF_REG_0, ctx); |
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emit_mv(rd, RV_REG_A0, ctx); |
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return 0; |
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} |
|
|
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int bpf_jit_emit_insn(const struct bpf_insn *insn, struct rv_jit_context *ctx, |
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bool extra_pass) |
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{ |
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bool is64 = BPF_CLASS(insn->code) == BPF_ALU64 || |
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BPF_CLASS(insn->code) == BPF_JMP; |
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int s, e, rvoff, ret, i = insn - ctx->prog->insnsi; |
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struct bpf_prog_aux *aux = ctx->prog->aux; |
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u8 rd = -1, rs = -1, code = insn->code; |
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s16 off = insn->off; |
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s32 imm = insn->imm; |
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|
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init_regs(&rd, &rs, insn, ctx); |
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|
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switch (code) { |
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/* dst = src */ |
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case BPF_ALU | BPF_MOV | BPF_X: |
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case BPF_ALU64 | BPF_MOV | BPF_X: |
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if (imm == 1) { |
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/* Special mov32 for zext */ |
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emit_zext_32(rd, ctx); |
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break; |
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} |
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emit_mv(rd, rs, ctx); |
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if (!is64 && !aux->verifier_zext) |
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emit_zext_32(rd, ctx); |
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break; |
|
|
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/* dst = dst OP src */ |
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case BPF_ALU | BPF_ADD | BPF_X: |
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case BPF_ALU64 | BPF_ADD | BPF_X: |
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emit_add(rd, rd, rs, ctx); |
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if (!is64 && !aux->verifier_zext) |
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emit_zext_32(rd, ctx); |
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break; |
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case BPF_ALU | BPF_SUB | BPF_X: |
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case BPF_ALU64 | BPF_SUB | BPF_X: |
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if (is64) |
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emit_sub(rd, rd, rs, ctx); |
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else |
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emit_subw(rd, rd, rs, ctx); |
|
|
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if (!is64 && !aux->verifier_zext) |
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emit_zext_32(rd, ctx); |
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break; |
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case BPF_ALU | BPF_AND | BPF_X: |
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case BPF_ALU64 | BPF_AND | BPF_X: |
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emit_and(rd, rd, rs, ctx); |
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if (!is64 && !aux->verifier_zext) |
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emit_zext_32(rd, ctx); |
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break; |
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case BPF_ALU | BPF_OR | BPF_X: |
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case BPF_ALU64 | BPF_OR | BPF_X: |
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emit_or(rd, rd, rs, ctx); |
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if (!is64 && !aux->verifier_zext) |
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emit_zext_32(rd, ctx); |
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break; |
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case BPF_ALU | BPF_XOR | BPF_X: |
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case BPF_ALU64 | BPF_XOR | BPF_X: |
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emit_xor(rd, rd, rs, ctx); |
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if (!is64 && !aux->verifier_zext) |
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emit_zext_32(rd, ctx); |
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break; |
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case BPF_ALU | BPF_MUL | BPF_X: |
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case BPF_ALU64 | BPF_MUL | BPF_X: |
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emit(is64 ? rv_mul(rd, rd, rs) : rv_mulw(rd, rd, rs), ctx); |
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if (!is64 && !aux->verifier_zext) |
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emit_zext_32(rd, ctx); |
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break; |
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case BPF_ALU | BPF_DIV | BPF_X: |
|
case BPF_ALU64 | BPF_DIV | BPF_X: |
|
emit(is64 ? rv_divu(rd, rd, rs) : rv_divuw(rd, rd, rs), ctx); |
|
if (!is64 && !aux->verifier_zext) |
|
emit_zext_32(rd, ctx); |
|
break; |
|
case BPF_ALU | BPF_MOD | BPF_X: |
|
case BPF_ALU64 | BPF_MOD | BPF_X: |
|
emit(is64 ? rv_remu(rd, rd, rs) : rv_remuw(rd, rd, rs), ctx); |
|
if (!is64 && !aux->verifier_zext) |
|
emit_zext_32(rd, ctx); |
|
break; |
|
case BPF_ALU | BPF_LSH | BPF_X: |
|
case BPF_ALU64 | BPF_LSH | BPF_X: |
|
emit(is64 ? rv_sll(rd, rd, rs) : rv_sllw(rd, rd, rs), ctx); |
|
if (!is64 && !aux->verifier_zext) |
|
emit_zext_32(rd, ctx); |
|
break; |
|
case BPF_ALU | BPF_RSH | BPF_X: |
|
case BPF_ALU64 | BPF_RSH | BPF_X: |
|
emit(is64 ? rv_srl(rd, rd, rs) : rv_srlw(rd, rd, rs), ctx); |
|
if (!is64 && !aux->verifier_zext) |
|
emit_zext_32(rd, ctx); |
|
break; |
|
case BPF_ALU | BPF_ARSH | BPF_X: |
|
case BPF_ALU64 | BPF_ARSH | BPF_X: |
|
emit(is64 ? rv_sra(rd, rd, rs) : rv_sraw(rd, rd, rs), ctx); |
|
if (!is64 && !aux->verifier_zext) |
|
emit_zext_32(rd, ctx); |
|
break; |
|
|
|
/* dst = -dst */ |
|
case BPF_ALU | BPF_NEG: |
|
case BPF_ALU64 | BPF_NEG: |
|
emit_sub(rd, RV_REG_ZERO, rd, ctx); |
|
if (!is64 && !aux->verifier_zext) |
|
emit_zext_32(rd, ctx); |
|
break; |
|
|
|
/* dst = BSWAP##imm(dst) */ |
|
case BPF_ALU | BPF_END | BPF_FROM_LE: |
|
switch (imm) { |
|
case 16: |
|
emit_slli(rd, rd, 48, ctx); |
|
emit_srli(rd, rd, 48, ctx); |
|
break; |
|
case 32: |
|
if (!aux->verifier_zext) |
|
emit_zext_32(rd, ctx); |
|
break; |
|
case 64: |
|
/* Do nothing */ |
|
break; |
|
} |
|
break; |
|
|
|
case BPF_ALU | BPF_END | BPF_FROM_BE: |
|
emit_li(RV_REG_T2, 0, ctx); |
|
|
|
emit_andi(RV_REG_T1, rd, 0xff, ctx); |
|
emit_add(RV_REG_T2, RV_REG_T2, RV_REG_T1, ctx); |
|
emit_slli(RV_REG_T2, RV_REG_T2, 8, ctx); |
|
emit_srli(rd, rd, 8, ctx); |
|
if (imm == 16) |
|
goto out_be; |
|
|
|
emit_andi(RV_REG_T1, rd, 0xff, ctx); |
|
emit_add(RV_REG_T2, RV_REG_T2, RV_REG_T1, ctx); |
|
emit_slli(RV_REG_T2, RV_REG_T2, 8, ctx); |
|
emit_srli(rd, rd, 8, ctx); |
|
|
|
emit_andi(RV_REG_T1, rd, 0xff, ctx); |
|
emit_add(RV_REG_T2, RV_REG_T2, RV_REG_T1, ctx); |
|
emit_slli(RV_REG_T2, RV_REG_T2, 8, ctx); |
|
emit_srli(rd, rd, 8, ctx); |
|
if (imm == 32) |
|
goto out_be; |
|
|
|
emit_andi(RV_REG_T1, rd, 0xff, ctx); |
|
emit_add(RV_REG_T2, RV_REG_T2, RV_REG_T1, ctx); |
|
emit_slli(RV_REG_T2, RV_REG_T2, 8, ctx); |
|
emit_srli(rd, rd, 8, ctx); |
|
|
|
emit_andi(RV_REG_T1, rd, 0xff, ctx); |
|
emit_add(RV_REG_T2, RV_REG_T2, RV_REG_T1, ctx); |
|
emit_slli(RV_REG_T2, RV_REG_T2, 8, ctx); |
|
emit_srli(rd, rd, 8, ctx); |
|
|
|
emit_andi(RV_REG_T1, rd, 0xff, ctx); |
|
emit_add(RV_REG_T2, RV_REG_T2, RV_REG_T1, ctx); |
|
emit_slli(RV_REG_T2, RV_REG_T2, 8, ctx); |
|
emit_srli(rd, rd, 8, ctx); |
|
|
|
emit_andi(RV_REG_T1, rd, 0xff, ctx); |
|
emit_add(RV_REG_T2, RV_REG_T2, RV_REG_T1, ctx); |
|
emit_slli(RV_REG_T2, RV_REG_T2, 8, ctx); |
|
emit_srli(rd, rd, 8, ctx); |
|
out_be: |
|
emit_andi(RV_REG_T1, rd, 0xff, ctx); |
|
emit_add(RV_REG_T2, RV_REG_T2, RV_REG_T1, ctx); |
|
|
|
emit_mv(rd, RV_REG_T2, ctx); |
|
break; |
|
|
|
/* dst = imm */ |
|
case BPF_ALU | BPF_MOV | BPF_K: |
|
case BPF_ALU64 | BPF_MOV | BPF_K: |
|
emit_imm(rd, imm, ctx); |
|
if (!is64 && !aux->verifier_zext) |
|
emit_zext_32(rd, ctx); |
|
break; |
|
|
|
/* dst = dst OP imm */ |
|
case BPF_ALU | BPF_ADD | BPF_K: |
|
case BPF_ALU64 | BPF_ADD | BPF_K: |
|
if (is_12b_int(imm)) { |
|
emit_addi(rd, rd, imm, ctx); |
|
} else { |
|
emit_imm(RV_REG_T1, imm, ctx); |
|
emit_add(rd, rd, RV_REG_T1, ctx); |
|
} |
|
if (!is64 && !aux->verifier_zext) |
|
emit_zext_32(rd, ctx); |
|
break; |
|
case BPF_ALU | BPF_SUB | BPF_K: |
|
case BPF_ALU64 | BPF_SUB | BPF_K: |
|
if (is_12b_int(-imm)) { |
|
emit_addi(rd, rd, -imm, ctx); |
|
} else { |
|
emit_imm(RV_REG_T1, imm, ctx); |
|
emit_sub(rd, rd, RV_REG_T1, ctx); |
|
} |
|
if (!is64 && !aux->verifier_zext) |
|
emit_zext_32(rd, ctx); |
|
break; |
|
case BPF_ALU | BPF_AND | BPF_K: |
|
case BPF_ALU64 | BPF_AND | BPF_K: |
|
if (is_12b_int(imm)) { |
|
emit_andi(rd, rd, imm, ctx); |
|
} else { |
|
emit_imm(RV_REG_T1, imm, ctx); |
|
emit_and(rd, rd, RV_REG_T1, ctx); |
|
} |
|
if (!is64 && !aux->verifier_zext) |
|
emit_zext_32(rd, ctx); |
|
break; |
|
case BPF_ALU | BPF_OR | BPF_K: |
|
case BPF_ALU64 | BPF_OR | BPF_K: |
|
if (is_12b_int(imm)) { |
|
emit(rv_ori(rd, rd, imm), ctx); |
|
} else { |
|
emit_imm(RV_REG_T1, imm, ctx); |
|
emit_or(rd, rd, RV_REG_T1, ctx); |
|
} |
|
if (!is64 && !aux->verifier_zext) |
|
emit_zext_32(rd, ctx); |
|
break; |
|
case BPF_ALU | BPF_XOR | BPF_K: |
|
case BPF_ALU64 | BPF_XOR | BPF_K: |
|
if (is_12b_int(imm)) { |
|
emit(rv_xori(rd, rd, imm), ctx); |
|
} else { |
|
emit_imm(RV_REG_T1, imm, ctx); |
|
emit_xor(rd, rd, RV_REG_T1, ctx); |
|
} |
|
if (!is64 && !aux->verifier_zext) |
|
emit_zext_32(rd, ctx); |
|
break; |
|
case BPF_ALU | BPF_MUL | BPF_K: |
|
case BPF_ALU64 | BPF_MUL | BPF_K: |
|
emit_imm(RV_REG_T1, imm, ctx); |
|
emit(is64 ? rv_mul(rd, rd, RV_REG_T1) : |
|
rv_mulw(rd, rd, RV_REG_T1), ctx); |
|
if (!is64 && !aux->verifier_zext) |
|
emit_zext_32(rd, ctx); |
|
break; |
|
case BPF_ALU | BPF_DIV | BPF_K: |
|
case BPF_ALU64 | BPF_DIV | BPF_K: |
|
emit_imm(RV_REG_T1, imm, ctx); |
|
emit(is64 ? rv_divu(rd, rd, RV_REG_T1) : |
|
rv_divuw(rd, rd, RV_REG_T1), ctx); |
|
if (!is64 && !aux->verifier_zext) |
|
emit_zext_32(rd, ctx); |
|
break; |
|
case BPF_ALU | BPF_MOD | BPF_K: |
|
case BPF_ALU64 | BPF_MOD | BPF_K: |
|
emit_imm(RV_REG_T1, imm, ctx); |
|
emit(is64 ? rv_remu(rd, rd, RV_REG_T1) : |
|
rv_remuw(rd, rd, RV_REG_T1), ctx); |
|
if (!is64 && !aux->verifier_zext) |
|
emit_zext_32(rd, ctx); |
|
break; |
|
case BPF_ALU | BPF_LSH | BPF_K: |
|
case BPF_ALU64 | BPF_LSH | BPF_K: |
|
emit_slli(rd, rd, imm, ctx); |
|
|
|
if (!is64 && !aux->verifier_zext) |
|
emit_zext_32(rd, ctx); |
|
break; |
|
case BPF_ALU | BPF_RSH | BPF_K: |
|
case BPF_ALU64 | BPF_RSH | BPF_K: |
|
if (is64) |
|
emit_srli(rd, rd, imm, ctx); |
|
else |
|
emit(rv_srliw(rd, rd, imm), ctx); |
|
|
|
if (!is64 && !aux->verifier_zext) |
|
emit_zext_32(rd, ctx); |
|
break; |
|
case BPF_ALU | BPF_ARSH | BPF_K: |
|
case BPF_ALU64 | BPF_ARSH | BPF_K: |
|
if (is64) |
|
emit_srai(rd, rd, imm, ctx); |
|
else |
|
emit(rv_sraiw(rd, rd, imm), ctx); |
|
|
|
if (!is64 && !aux->verifier_zext) |
|
emit_zext_32(rd, ctx); |
|
break; |
|
|
|
/* JUMP off */ |
|
case BPF_JMP | BPF_JA: |
|
rvoff = rv_offset(i, off, ctx); |
|
ret = emit_jump_and_link(RV_REG_ZERO, rvoff, false, ctx); |
|
if (ret) |
|
return ret; |
|
break; |
|
|
|
/* IF (dst COND src) JUMP off */ |
|
case BPF_JMP | BPF_JEQ | BPF_X: |
|
case BPF_JMP32 | BPF_JEQ | BPF_X: |
|
case BPF_JMP | BPF_JGT | BPF_X: |
|
case BPF_JMP32 | BPF_JGT | BPF_X: |
|
case BPF_JMP | BPF_JLT | BPF_X: |
|
case BPF_JMP32 | BPF_JLT | BPF_X: |
|
case BPF_JMP | BPF_JGE | BPF_X: |
|
case BPF_JMP32 | BPF_JGE | BPF_X: |
|
case BPF_JMP | BPF_JLE | BPF_X: |
|
case BPF_JMP32 | BPF_JLE | BPF_X: |
|
case BPF_JMP | BPF_JNE | BPF_X: |
|
case BPF_JMP32 | BPF_JNE | BPF_X: |
|
case BPF_JMP | BPF_JSGT | BPF_X: |
|
case BPF_JMP32 | BPF_JSGT | BPF_X: |
|
case BPF_JMP | BPF_JSLT | BPF_X: |
|
case BPF_JMP32 | BPF_JSLT | BPF_X: |
|
case BPF_JMP | BPF_JSGE | BPF_X: |
|
case BPF_JMP32 | BPF_JSGE | BPF_X: |
|
case BPF_JMP | BPF_JSLE | BPF_X: |
|
case BPF_JMP32 | BPF_JSLE | BPF_X: |
|
case BPF_JMP | BPF_JSET | BPF_X: |
|
case BPF_JMP32 | BPF_JSET | BPF_X: |
|
rvoff = rv_offset(i, off, ctx); |
|
if (!is64) { |
|
s = ctx->ninsns; |
|
if (is_signed_bpf_cond(BPF_OP(code))) |
|
emit_sext_32_rd_rs(&rd, &rs, ctx); |
|
else |
|
emit_zext_32_rd_rs(&rd, &rs, ctx); |
|
e = ctx->ninsns; |
|
|
|
/* Adjust for extra insns */ |
|
rvoff -= ninsns_rvoff(e - s); |
|
} |
|
|
|
if (BPF_OP(code) == BPF_JSET) { |
|
/* Adjust for and */ |
|
rvoff -= 4; |
|
emit_and(RV_REG_T1, rd, rs, ctx); |
|
emit_branch(BPF_JNE, RV_REG_T1, RV_REG_ZERO, rvoff, |
|
ctx); |
|
} else { |
|
emit_branch(BPF_OP(code), rd, rs, rvoff, ctx); |
|
} |
|
break; |
|
|
|
/* IF (dst COND imm) JUMP off */ |
|
case BPF_JMP | BPF_JEQ | BPF_K: |
|
case BPF_JMP32 | BPF_JEQ | BPF_K: |
|
case BPF_JMP | BPF_JGT | BPF_K: |
|
case BPF_JMP32 | BPF_JGT | BPF_K: |
|
case BPF_JMP | BPF_JLT | BPF_K: |
|
case BPF_JMP32 | BPF_JLT | BPF_K: |
|
case BPF_JMP | BPF_JGE | BPF_K: |
|
case BPF_JMP32 | BPF_JGE | BPF_K: |
|
case BPF_JMP | BPF_JLE | BPF_K: |
|
case BPF_JMP32 | BPF_JLE | BPF_K: |
|
case BPF_JMP | BPF_JNE | BPF_K: |
|
case BPF_JMP32 | BPF_JNE | BPF_K: |
|
case BPF_JMP | BPF_JSGT | BPF_K: |
|
case BPF_JMP32 | BPF_JSGT | BPF_K: |
|
case BPF_JMP | BPF_JSLT | BPF_K: |
|
case BPF_JMP32 | BPF_JSLT | BPF_K: |
|
case BPF_JMP | BPF_JSGE | BPF_K: |
|
case BPF_JMP32 | BPF_JSGE | BPF_K: |
|
case BPF_JMP | BPF_JSLE | BPF_K: |
|
case BPF_JMP32 | BPF_JSLE | BPF_K: |
|
rvoff = rv_offset(i, off, ctx); |
|
s = ctx->ninsns; |
|
if (imm) { |
|
emit_imm(RV_REG_T1, imm, ctx); |
|
rs = RV_REG_T1; |
|
} else { |
|
/* If imm is 0, simply use zero register. */ |
|
rs = RV_REG_ZERO; |
|
} |
|
if (!is64) { |
|
if (is_signed_bpf_cond(BPF_OP(code))) |
|
emit_sext_32_rd(&rd, ctx); |
|
else |
|
emit_zext_32_rd_t1(&rd, ctx); |
|
} |
|
e = ctx->ninsns; |
|
|
|
/* Adjust for extra insns */ |
|
rvoff -= ninsns_rvoff(e - s); |
|
emit_branch(BPF_OP(code), rd, rs, rvoff, ctx); |
|
break; |
|
|
|
case BPF_JMP | BPF_JSET | BPF_K: |
|
case BPF_JMP32 | BPF_JSET | BPF_K: |
|
rvoff = rv_offset(i, off, ctx); |
|
s = ctx->ninsns; |
|
if (is_12b_int(imm)) { |
|
emit_andi(RV_REG_T1, rd, imm, ctx); |
|
} else { |
|
emit_imm(RV_REG_T1, imm, ctx); |
|
emit_and(RV_REG_T1, rd, RV_REG_T1, ctx); |
|
} |
|
/* For jset32, we should clear the upper 32 bits of t1, but |
|
* sign-extension is sufficient here and saves one instruction, |
|
* as t1 is used only in comparison against zero. |
|
*/ |
|
if (!is64 && imm < 0) |
|
emit_addiw(RV_REG_T1, RV_REG_T1, 0, ctx); |
|
e = ctx->ninsns; |
|
rvoff -= ninsns_rvoff(e - s); |
|
emit_branch(BPF_JNE, RV_REG_T1, RV_REG_ZERO, rvoff, ctx); |
|
break; |
|
|
|
/* function call */ |
|
case BPF_JMP | BPF_CALL: |
|
{ |
|
bool fixed; |
|
u64 addr; |
|
|
|
mark_call(ctx); |
|
ret = bpf_jit_get_func_addr(ctx->prog, insn, extra_pass, &addr, |
|
&fixed); |
|
if (ret < 0) |
|
return ret; |
|
ret = emit_call(fixed, addr, ctx); |
|
if (ret) |
|
return ret; |
|
break; |
|
} |
|
/* tail call */ |
|
case BPF_JMP | BPF_TAIL_CALL: |
|
if (emit_bpf_tail_call(i, ctx)) |
|
return -1; |
|
break; |
|
|
|
/* function return */ |
|
case BPF_JMP | BPF_EXIT: |
|
if (i == ctx->prog->len - 1) |
|
break; |
|
|
|
rvoff = epilogue_offset(ctx); |
|
ret = emit_jump_and_link(RV_REG_ZERO, rvoff, false, ctx); |
|
if (ret) |
|
return ret; |
|
break; |
|
|
|
/* dst = imm64 */ |
|
case BPF_LD | BPF_IMM | BPF_DW: |
|
{ |
|
struct bpf_insn insn1 = insn[1]; |
|
u64 imm64; |
|
|
|
imm64 = (u64)insn1.imm << 32 | (u32)imm; |
|
emit_imm(rd, imm64, ctx); |
|
return 1; |
|
} |
|
|
|
/* LDX: dst = *(size *)(src + off) */ |
|
case BPF_LDX | BPF_MEM | BPF_B: |
|
if (is_12b_int(off)) { |
|
emit(rv_lbu(rd, off, rs), ctx); |
|
break; |
|
} |
|
|
|
emit_imm(RV_REG_T1, off, ctx); |
|
emit_add(RV_REG_T1, RV_REG_T1, rs, ctx); |
|
emit(rv_lbu(rd, 0, RV_REG_T1), ctx); |
|
if (insn_is_zext(&insn[1])) |
|
return 1; |
|
break; |
|
case BPF_LDX | BPF_MEM | BPF_H: |
|
if (is_12b_int(off)) { |
|
emit(rv_lhu(rd, off, rs), ctx); |
|
break; |
|
} |
|
|
|
emit_imm(RV_REG_T1, off, ctx); |
|
emit_add(RV_REG_T1, RV_REG_T1, rs, ctx); |
|
emit(rv_lhu(rd, 0, RV_REG_T1), ctx); |
|
if (insn_is_zext(&insn[1])) |
|
return 1; |
|
break; |
|
case BPF_LDX | BPF_MEM | BPF_W: |
|
if (is_12b_int(off)) { |
|
emit(rv_lwu(rd, off, rs), ctx); |
|
break; |
|
} |
|
|
|
emit_imm(RV_REG_T1, off, ctx); |
|
emit_add(RV_REG_T1, RV_REG_T1, rs, ctx); |
|
emit(rv_lwu(rd, 0, RV_REG_T1), ctx); |
|
if (insn_is_zext(&insn[1])) |
|
return 1; |
|
break; |
|
case BPF_LDX | BPF_MEM | BPF_DW: |
|
if (is_12b_int(off)) { |
|
emit_ld(rd, off, rs, ctx); |
|
break; |
|
} |
|
|
|
emit_imm(RV_REG_T1, off, ctx); |
|
emit_add(RV_REG_T1, RV_REG_T1, rs, ctx); |
|
emit_ld(rd, 0, RV_REG_T1, ctx); |
|
break; |
|
|
|
/* speculation barrier */ |
|
case BPF_ST | BPF_NOSPEC: |
|
break; |
|
|
|
/* ST: *(size *)(dst + off) = imm */ |
|
case BPF_ST | BPF_MEM | BPF_B: |
|
emit_imm(RV_REG_T1, imm, ctx); |
|
if (is_12b_int(off)) { |
|
emit(rv_sb(rd, off, RV_REG_T1), ctx); |
|
break; |
|
} |
|
|
|
emit_imm(RV_REG_T2, off, ctx); |
|
emit_add(RV_REG_T2, RV_REG_T2, rd, ctx); |
|
emit(rv_sb(RV_REG_T2, 0, RV_REG_T1), ctx); |
|
break; |
|
|
|
case BPF_ST | BPF_MEM | BPF_H: |
|
emit_imm(RV_REG_T1, imm, ctx); |
|
if (is_12b_int(off)) { |
|
emit(rv_sh(rd, off, RV_REG_T1), ctx); |
|
break; |
|
} |
|
|
|
emit_imm(RV_REG_T2, off, ctx); |
|
emit_add(RV_REG_T2, RV_REG_T2, rd, ctx); |
|
emit(rv_sh(RV_REG_T2, 0, RV_REG_T1), ctx); |
|
break; |
|
case BPF_ST | BPF_MEM | BPF_W: |
|
emit_imm(RV_REG_T1, imm, ctx); |
|
if (is_12b_int(off)) { |
|
emit_sw(rd, off, RV_REG_T1, ctx); |
|
break; |
|
} |
|
|
|
emit_imm(RV_REG_T2, off, ctx); |
|
emit_add(RV_REG_T2, RV_REG_T2, rd, ctx); |
|
emit_sw(RV_REG_T2, 0, RV_REG_T1, ctx); |
|
break; |
|
case BPF_ST | BPF_MEM | BPF_DW: |
|
emit_imm(RV_REG_T1, imm, ctx); |
|
if (is_12b_int(off)) { |
|
emit_sd(rd, off, RV_REG_T1, ctx); |
|
break; |
|
} |
|
|
|
emit_imm(RV_REG_T2, off, ctx); |
|
emit_add(RV_REG_T2, RV_REG_T2, rd, ctx); |
|
emit_sd(RV_REG_T2, 0, RV_REG_T1, ctx); |
|
break; |
|
|
|
/* STX: *(size *)(dst + off) = src */ |
|
case BPF_STX | BPF_MEM | BPF_B: |
|
if (is_12b_int(off)) { |
|
emit(rv_sb(rd, off, rs), ctx); |
|
break; |
|
} |
|
|
|
emit_imm(RV_REG_T1, off, ctx); |
|
emit_add(RV_REG_T1, RV_REG_T1, rd, ctx); |
|
emit(rv_sb(RV_REG_T1, 0, rs), ctx); |
|
break; |
|
case BPF_STX | BPF_MEM | BPF_H: |
|
if (is_12b_int(off)) { |
|
emit(rv_sh(rd, off, rs), ctx); |
|
break; |
|
} |
|
|
|
emit_imm(RV_REG_T1, off, ctx); |
|
emit_add(RV_REG_T1, RV_REG_T1, rd, ctx); |
|
emit(rv_sh(RV_REG_T1, 0, rs), ctx); |
|
break; |
|
case BPF_STX | BPF_MEM | BPF_W: |
|
if (is_12b_int(off)) { |
|
emit_sw(rd, off, rs, ctx); |
|
break; |
|
} |
|
|
|
emit_imm(RV_REG_T1, off, ctx); |
|
emit_add(RV_REG_T1, RV_REG_T1, rd, ctx); |
|
emit_sw(RV_REG_T1, 0, rs, ctx); |
|
break; |
|
case BPF_STX | BPF_MEM | BPF_DW: |
|
if (is_12b_int(off)) { |
|
emit_sd(rd, off, rs, ctx); |
|
break; |
|
} |
|
|
|
emit_imm(RV_REG_T1, off, ctx); |
|
emit_add(RV_REG_T1, RV_REG_T1, rd, ctx); |
|
emit_sd(RV_REG_T1, 0, rs, ctx); |
|
break; |
|
case BPF_STX | BPF_ATOMIC | BPF_W: |
|
case BPF_STX | BPF_ATOMIC | BPF_DW: |
|
if (insn->imm != BPF_ADD) { |
|
pr_err("bpf-jit: not supported: atomic operation %02x ***\n", |
|
insn->imm); |
|
return -EINVAL; |
|
} |
|
|
|
/* atomic_add: lock *(u32 *)(dst + off) += src |
|
* atomic_add: lock *(u64 *)(dst + off) += src |
|
*/ |
|
|
|
if (off) { |
|
if (is_12b_int(off)) { |
|
emit_addi(RV_REG_T1, rd, off, ctx); |
|
} else { |
|
emit_imm(RV_REG_T1, off, ctx); |
|
emit_add(RV_REG_T1, RV_REG_T1, rd, ctx); |
|
} |
|
|
|
rd = RV_REG_T1; |
|
} |
|
|
|
emit(BPF_SIZE(code) == BPF_W ? |
|
rv_amoadd_w(RV_REG_ZERO, rs, rd, 0, 0) : |
|
rv_amoadd_d(RV_REG_ZERO, rs, rd, 0, 0), ctx); |
|
break; |
|
default: |
|
pr_err("bpf-jit: unknown opcode %02x\n", code); |
|
return -EINVAL; |
|
} |
|
|
|
return 0; |
|
} |
|
|
|
void bpf_jit_build_prologue(struct rv_jit_context *ctx) |
|
{ |
|
int stack_adjust = 0, store_offset, bpf_stack_adjust; |
|
|
|
bpf_stack_adjust = round_up(ctx->prog->aux->stack_depth, 16); |
|
if (bpf_stack_adjust) |
|
mark_fp(ctx); |
|
|
|
if (seen_reg(RV_REG_RA, ctx)) |
|
stack_adjust += 8; |
|
stack_adjust += 8; /* RV_REG_FP */ |
|
if (seen_reg(RV_REG_S1, ctx)) |
|
stack_adjust += 8; |
|
if (seen_reg(RV_REG_S2, ctx)) |
|
stack_adjust += 8; |
|
if (seen_reg(RV_REG_S3, ctx)) |
|
stack_adjust += 8; |
|
if (seen_reg(RV_REG_S4, ctx)) |
|
stack_adjust += 8; |
|
if (seen_reg(RV_REG_S5, ctx)) |
|
stack_adjust += 8; |
|
if (seen_reg(RV_REG_S6, ctx)) |
|
stack_adjust += 8; |
|
|
|
stack_adjust = round_up(stack_adjust, 16); |
|
stack_adjust += bpf_stack_adjust; |
|
|
|
store_offset = stack_adjust - 8; |
|
|
|
/* First instruction is always setting the tail-call-counter |
|
* (TCC) register. This instruction is skipped for tail calls. |
|
* Force using a 4-byte (non-compressed) instruction. |
|
*/ |
|
emit(rv_addi(RV_REG_TCC, RV_REG_ZERO, MAX_TAIL_CALL_CNT), ctx); |
|
|
|
emit_addi(RV_REG_SP, RV_REG_SP, -stack_adjust, ctx); |
|
|
|
if (seen_reg(RV_REG_RA, ctx)) { |
|
emit_sd(RV_REG_SP, store_offset, RV_REG_RA, ctx); |
|
store_offset -= 8; |
|
} |
|
emit_sd(RV_REG_SP, store_offset, RV_REG_FP, ctx); |
|
store_offset -= 8; |
|
if (seen_reg(RV_REG_S1, ctx)) { |
|
emit_sd(RV_REG_SP, store_offset, RV_REG_S1, ctx); |
|
store_offset -= 8; |
|
} |
|
if (seen_reg(RV_REG_S2, ctx)) { |
|
emit_sd(RV_REG_SP, store_offset, RV_REG_S2, ctx); |
|
store_offset -= 8; |
|
} |
|
if (seen_reg(RV_REG_S3, ctx)) { |
|
emit_sd(RV_REG_SP, store_offset, RV_REG_S3, ctx); |
|
store_offset -= 8; |
|
} |
|
if (seen_reg(RV_REG_S4, ctx)) { |
|
emit_sd(RV_REG_SP, store_offset, RV_REG_S4, ctx); |
|
store_offset -= 8; |
|
} |
|
if (seen_reg(RV_REG_S5, ctx)) { |
|
emit_sd(RV_REG_SP, store_offset, RV_REG_S5, ctx); |
|
store_offset -= 8; |
|
} |
|
if (seen_reg(RV_REG_S6, ctx)) { |
|
emit_sd(RV_REG_SP, store_offset, RV_REG_S6, ctx); |
|
store_offset -= 8; |
|
} |
|
|
|
emit_addi(RV_REG_FP, RV_REG_SP, stack_adjust, ctx); |
|
|
|
if (bpf_stack_adjust) |
|
emit_addi(RV_REG_S5, RV_REG_SP, bpf_stack_adjust, ctx); |
|
|
|
/* Program contains calls and tail calls, so RV_REG_TCC need |
|
* to be saved across calls. |
|
*/ |
|
if (seen_tail_call(ctx) && seen_call(ctx)) |
|
emit_mv(RV_REG_TCC_SAVED, RV_REG_TCC, ctx); |
|
|
|
ctx->stack_size = stack_adjust; |
|
} |
|
|
|
void bpf_jit_build_epilogue(struct rv_jit_context *ctx) |
|
{ |
|
__build_epilogue(false, ctx); |
|
}
|
|
|