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113 lines
2.3 KiB
113 lines
2.3 KiB
/* SPDX-License-Identifier: GPL-2.0-only */ |
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/* |
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* Copyright (C) 2013 Regents of the University of California |
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*/ |
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#include <linux/linkage.h> |
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#include <asm/asm.h> |
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/* void *memset(void *, int, size_t) */ |
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ENTRY(__memset) |
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WEAK(memset) |
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move t0, a0 /* Preserve return value */ |
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/* Defer to byte-oriented fill for small sizes */ |
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sltiu a3, a2, 16 |
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bnez a3, 4f |
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/* |
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* Round to nearest XLEN-aligned address |
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* greater than or equal to start address |
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*/ |
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addi a3, t0, SZREG-1 |
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andi a3, a3, ~(SZREG-1) |
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beq a3, t0, 2f /* Skip if already aligned */ |
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/* Handle initial misalignment */ |
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sub a4, a3, t0 |
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1: |
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sb a1, 0(t0) |
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addi t0, t0, 1 |
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bltu t0, a3, 1b |
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sub a2, a2, a4 /* Update count */ |
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2: /* Duff's device with 32 XLEN stores per iteration */ |
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/* Broadcast value into all bytes */ |
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andi a1, a1, 0xff |
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slli a3, a1, 8 |
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or a1, a3, a1 |
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slli a3, a1, 16 |
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or a1, a3, a1 |
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#ifdef CONFIG_64BIT |
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slli a3, a1, 32 |
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or a1, a3, a1 |
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#endif |
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/* Calculate end address */ |
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andi a4, a2, ~(SZREG-1) |
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add a3, t0, a4 |
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andi a4, a4, 31*SZREG /* Calculate remainder */ |
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beqz a4, 3f /* Shortcut if no remainder */ |
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neg a4, a4 |
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addi a4, a4, 32*SZREG /* Calculate initial offset */ |
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/* Adjust start address with offset */ |
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sub t0, t0, a4 |
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/* Jump into loop body */ |
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/* Assumes 32-bit instruction lengths */ |
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la a5, 3f |
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#ifdef CONFIG_64BIT |
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srli a4, a4, 1 |
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#endif |
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add a5, a5, a4 |
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jr a5 |
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3: |
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REG_S a1, 0(t0) |
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REG_S a1, SZREG(t0) |
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REG_S a1, 2*SZREG(t0) |
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REG_S a1, 3*SZREG(t0) |
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REG_S a1, 4*SZREG(t0) |
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REG_S a1, 5*SZREG(t0) |
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REG_S a1, 6*SZREG(t0) |
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REG_S a1, 7*SZREG(t0) |
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REG_S a1, 8*SZREG(t0) |
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REG_S a1, 9*SZREG(t0) |
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REG_S a1, 10*SZREG(t0) |
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REG_S a1, 11*SZREG(t0) |
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REG_S a1, 12*SZREG(t0) |
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REG_S a1, 13*SZREG(t0) |
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REG_S a1, 14*SZREG(t0) |
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REG_S a1, 15*SZREG(t0) |
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REG_S a1, 16*SZREG(t0) |
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REG_S a1, 17*SZREG(t0) |
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REG_S a1, 18*SZREG(t0) |
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REG_S a1, 19*SZREG(t0) |
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REG_S a1, 20*SZREG(t0) |
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REG_S a1, 21*SZREG(t0) |
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REG_S a1, 22*SZREG(t0) |
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REG_S a1, 23*SZREG(t0) |
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REG_S a1, 24*SZREG(t0) |
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REG_S a1, 25*SZREG(t0) |
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REG_S a1, 26*SZREG(t0) |
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REG_S a1, 27*SZREG(t0) |
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REG_S a1, 28*SZREG(t0) |
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REG_S a1, 29*SZREG(t0) |
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REG_S a1, 30*SZREG(t0) |
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REG_S a1, 31*SZREG(t0) |
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addi t0, t0, 32*SZREG |
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bltu t0, a3, 3b |
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andi a2, a2, SZREG-1 /* Update count */ |
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4: |
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/* Handle trailing misalignment */ |
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beqz a2, 6f |
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add a3, t0, a2 |
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5: |
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sb a1, 0(t0) |
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addi t0, t0, 1 |
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bltu t0, a3, 5b |
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6: |
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ret |
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END(__memset)
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