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459 lines
11 KiB
459 lines
11 KiB
// SPDX-License-Identifier: GPL-2.0+ |
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/* |
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* Copyright (C) 2019-20 Sean Anderson <[email protected]> |
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* Copyright (C) 2020 Western Digital Corporation or its affiliates. |
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*/ |
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#include <dt-bindings/clock/k210-clk.h> |
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#include <dt-bindings/pinctrl/k210-fpioa.h> |
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#include <dt-bindings/reset/k210-rst.h> |
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/ { |
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/* |
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* Although the K210 is a 64-bit CPU, the address bus is only 32-bits |
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* wide, and the upper half of all addresses is ignored. |
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*/ |
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#address-cells = <1>; |
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#size-cells = <1>; |
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compatible = "canaan,kendryte-k210"; |
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aliases { |
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serial0 = &uarths0; |
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serial1 = &uart1; |
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serial2 = &uart2; |
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serial3 = &uart3; |
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}; |
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/* |
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* The K210 has an sv39 MMU following the privileged specification v1.9. |
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* Since this is a non-ratified draft specification, the kernel does not |
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* support it and the K210 support enabled only for the !MMU case. |
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* Be consistent with this by setting the CPUs MMU type to "none". |
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*/ |
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cpus { |
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#address-cells = <1>; |
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#size-cells = <0>; |
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timebase-frequency = <7800000>; |
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cpu0: cpu@0 { |
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device_type = "cpu"; |
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compatible = "canaan,k210", "riscv"; |
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reg = <0>; |
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riscv,isa = "rv64imafdc"; |
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mmu-type = "riscv,none"; |
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i-cache-block-size = <64>; |
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i-cache-size = <0x8000>; |
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d-cache-block-size = <64>; |
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d-cache-size = <0x8000>; |
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cpu0_intc: interrupt-controller { |
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#interrupt-cells = <1>; |
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interrupt-controller; |
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compatible = "riscv,cpu-intc"; |
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}; |
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}; |
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cpu1: cpu@1 { |
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device_type = "cpu"; |
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compatible = "canaan,k210", "riscv"; |
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reg = <1>; |
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riscv,isa = "rv64imafdc"; |
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mmu-type = "riscv,none"; |
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i-cache-block-size = <64>; |
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i-cache-size = <0x8000>; |
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d-cache-block-size = <64>; |
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d-cache-size = <0x8000>; |
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cpu1_intc: interrupt-controller { |
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#interrupt-cells = <1>; |
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interrupt-controller; |
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compatible = "riscv,cpu-intc"; |
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}; |
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}; |
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}; |
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sram: memory@80000000 { |
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device_type = "memory"; |
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compatible = "canaan,k210-sram"; |
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reg = <0x80000000 0x400000>, |
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<0x80400000 0x200000>, |
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<0x80600000 0x200000>; |
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reg-names = "sram0", "sram1", "aisram"; |
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clocks = <&sysclk K210_CLK_SRAM0>, |
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<&sysclk K210_CLK_SRAM1>, |
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<&sysclk K210_CLK_AI>; |
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clock-names = "sram0", "sram1", "aisram"; |
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}; |
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clocks { |
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in0: oscillator { |
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compatible = "fixed-clock"; |
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#clock-cells = <0>; |
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clock-frequency = <26000000>; |
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}; |
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}; |
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soc { |
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#address-cells = <1>; |
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#size-cells = <1>; |
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compatible = "simple-bus"; |
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ranges; |
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interrupt-parent = <&plic0>; |
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rom0: nvmem@1000 { |
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reg = <0x1000 0x1000>; |
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read-only; |
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}; |
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clint0: timer@2000000 { |
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compatible = "canaan,k210-clint", "sifive,clint0"; |
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reg = <0x2000000 0xC000>; |
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interrupts-extended = <&cpu0_intc 3 &cpu0_intc 7 |
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&cpu1_intc 3 &cpu1_intc 7>; |
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}; |
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plic0: interrupt-controller@c000000 { |
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#interrupt-cells = <1>; |
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#address-cells = <0>; |
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compatible = "canaan,k210-plic", "sifive,plic-1.0.0"; |
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reg = <0xC000000 0x4000000>; |
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interrupt-controller; |
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interrupts-extended = <&cpu0_intc 11 &cpu1_intc 11>; |
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riscv,ndev = <65>; |
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}; |
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uarths0: serial@38000000 { |
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compatible = "canaan,k210-uarths", "sifive,uart0"; |
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reg = <0x38000000 0x1000>; |
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interrupts = <33>; |
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clocks = <&sysclk K210_CLK_CPU>; |
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}; |
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gpio0: gpio-controller@38001000 { |
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#interrupt-cells = <2>; |
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#gpio-cells = <2>; |
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compatible = "canaan,k210-gpiohs", "sifive,gpio0"; |
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reg = <0x38001000 0x1000>; |
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interrupt-controller; |
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interrupts = <34 35 36 37 38 39 40 41 |
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42 43 44 45 46 47 48 49 |
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50 51 52 53 54 55 56 57 |
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58 59 60 61 62 63 64 65>; |
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gpio-controller; |
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ngpios = <32>; |
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}; |
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dmac0: dma-controller@50000000 { |
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compatible = "snps,axi-dma-1.01a"; |
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reg = <0x50000000 0x1000>; |
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interrupts = <27 28 29 30 31 32>; |
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#dma-cells = <1>; |
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clocks = <&sysclk K210_CLK_DMA>, <&sysclk K210_CLK_DMA>; |
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clock-names = "core-clk", "cfgr-clk"; |
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resets = <&sysrst K210_RST_DMA>; |
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dma-channels = <6>; |
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snps,dma-masters = <2>; |
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snps,priority = <0 1 2 3 4 5>; |
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snps,data-width = <5>; |
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snps,block-size = <0x200000 0x200000 0x200000 |
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0x200000 0x200000 0x200000>; |
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snps,axi-max-burst-len = <256>; |
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}; |
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apb0: bus@50200000 { |
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#address-cells = <1>; |
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#size-cells = <1>; |
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compatible = "simple-pm-bus"; |
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ranges; |
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clocks = <&sysclk K210_CLK_APB0>; |
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gpio1: gpio@50200000 { |
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#address-cells = <1>; |
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#size-cells = <0>; |
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compatible = "snps,dw-apb-gpio"; |
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reg = <0x50200000 0x80>; |
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clocks = <&sysclk K210_CLK_APB0>, |
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<&sysclk K210_CLK_GPIO>; |
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clock-names = "bus", "db"; |
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resets = <&sysrst K210_RST_GPIO>; |
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gpio1_0: gpio-port@0 { |
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#gpio-cells = <2>; |
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#interrupt-cells = <2>; |
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compatible = "snps,dw-apb-gpio-port"; |
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reg = <0>; |
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interrupt-controller; |
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interrupts = <23>; |
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gpio-controller; |
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ngpios = <8>; |
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}; |
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}; |
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uart1: serial@50210000 { |
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compatible = "snps,dw-apb-uart"; |
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reg = <0x50210000 0x100>; |
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interrupts = <11>; |
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clocks = <&sysclk K210_CLK_UART1>, |
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<&sysclk K210_CLK_APB0>; |
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clock-names = "baudclk", "apb_pclk"; |
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resets = <&sysrst K210_RST_UART1>; |
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reg-io-width = <4>; |
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reg-shift = <2>; |
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dcd-override; |
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dsr-override; |
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cts-override; |
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ri-override; |
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}; |
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uart2: serial@50220000 { |
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compatible = "snps,dw-apb-uart"; |
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reg = <0x50220000 0x100>; |
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interrupts = <12>; |
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clocks = <&sysclk K210_CLK_UART2>, |
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<&sysclk K210_CLK_APB0>; |
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clock-names = "baudclk", "apb_pclk"; |
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resets = <&sysrst K210_RST_UART2>; |
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reg-io-width = <4>; |
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reg-shift = <2>; |
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dcd-override; |
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dsr-override; |
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cts-override; |
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ri-override; |
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}; |
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uart3: serial@50230000 { |
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compatible = "snps,dw-apb-uart"; |
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reg = <0x50230000 0x100>; |
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interrupts = <13>; |
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clocks = <&sysclk K210_CLK_UART3>, |
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<&sysclk K210_CLK_APB0>; |
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clock-names = "baudclk", "apb_pclk"; |
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resets = <&sysrst K210_RST_UART3>; |
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reg-io-width = <4>; |
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reg-shift = <2>; |
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dcd-override; |
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dsr-override; |
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cts-override; |
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ri-override; |
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}; |
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spi2: spi@50240000 { |
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compatible = "canaan,k210-spi"; |
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spi-slave; |
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reg = <0x50240000 0x100>; |
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#address-cells = <0>; |
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#size-cells = <0>; |
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interrupts = <3>; |
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clocks = <&sysclk K210_CLK_SPI2>, |
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<&sysclk K210_CLK_APB0>; |
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clock-names = "ssi_clk", "pclk"; |
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resets = <&sysrst K210_RST_SPI2>; |
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spi-max-frequency = <25000000>; |
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}; |
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i2s0: i2s@50250000 { |
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compatible = "snps,designware-i2s"; |
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reg = <0x50250000 0x200>; |
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interrupts = <5>; |
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clocks = <&sysclk K210_CLK_I2S0>; |
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clock-names = "i2sclk"; |
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resets = <&sysrst K210_RST_I2S0>; |
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}; |
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i2s1: i2s@50260000 { |
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compatible = "snps,designware-i2s"; |
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reg = <0x50260000 0x200>; |
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interrupts = <6>; |
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clocks = <&sysclk K210_CLK_I2S1>; |
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clock-names = "i2sclk"; |
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resets = <&sysrst K210_RST_I2S1>; |
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}; |
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i2s2: i2s@50270000 { |
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compatible = "snps,designware-i2s"; |
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reg = <0x50270000 0x200>; |
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interrupts = <7>; |
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clocks = <&sysclk K210_CLK_I2S2>; |
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clock-names = "i2sclk"; |
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resets = <&sysrst K210_RST_I2S2>; |
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}; |
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i2c0: i2c@50280000 { |
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compatible = "snps,designware-i2c"; |
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reg = <0x50280000 0x100>; |
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interrupts = <8>; |
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clocks = <&sysclk K210_CLK_I2C0>, |
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<&sysclk K210_CLK_APB0>; |
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clock-names = "ref", "pclk"; |
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resets = <&sysrst K210_RST_I2C0>; |
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}; |
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i2c1: i2c@50290000 { |
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compatible = "snps,designware-i2c"; |
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reg = <0x50290000 0x100>; |
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interrupts = <9>; |
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clocks = <&sysclk K210_CLK_I2C1>, |
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<&sysclk K210_CLK_APB0>; |
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clock-names = "ref", "pclk"; |
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resets = <&sysrst K210_RST_I2C1>; |
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}; |
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i2c2: i2c@502a0000 { |
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compatible = "snps,designware-i2c"; |
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reg = <0x502A0000 0x100>; |
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interrupts = <10>; |
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clocks = <&sysclk K210_CLK_I2C2>, |
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<&sysclk K210_CLK_APB0>; |
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clock-names = "ref", "pclk"; |
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resets = <&sysrst K210_RST_I2C2>; |
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}; |
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fpioa: pinmux@502b0000 { |
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compatible = "canaan,k210-fpioa"; |
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reg = <0x502B0000 0x100>; |
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clocks = <&sysclk K210_CLK_FPIOA>, |
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<&sysclk K210_CLK_APB0>; |
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clock-names = "ref", "pclk"; |
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resets = <&sysrst K210_RST_FPIOA>; |
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canaan,k210-sysctl-power = <&sysctl 108>; |
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}; |
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timer0: timer@502d0000 { |
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compatible = "snps,dw-apb-timer"; |
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reg = <0x502D0000 0x100>; |
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interrupts = <14 15>; |
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clocks = <&sysclk K210_CLK_TIMER0>, |
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<&sysclk K210_CLK_APB0>; |
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clock-names = "timer", "pclk"; |
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resets = <&sysrst K210_RST_TIMER0>; |
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}; |
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timer1: timer@502e0000 { |
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compatible = "snps,dw-apb-timer"; |
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reg = <0x502E0000 0x100>; |
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interrupts = <16 17>; |
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clocks = <&sysclk K210_CLK_TIMER1>, |
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<&sysclk K210_CLK_APB0>; |
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clock-names = "timer", "pclk"; |
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resets = <&sysrst K210_RST_TIMER1>; |
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}; |
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timer2: timer@502f0000 { |
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compatible = "snps,dw-apb-timer"; |
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reg = <0x502F0000 0x100>; |
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interrupts = <18 19>; |
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clocks = <&sysclk K210_CLK_TIMER2>, |
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<&sysclk K210_CLK_APB0>; |
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clock-names = "timer", "pclk"; |
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resets = <&sysrst K210_RST_TIMER2>; |
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}; |
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}; |
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apb1: bus@50400000 { |
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#address-cells = <1>; |
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#size-cells = <1>; |
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compatible = "simple-pm-bus"; |
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ranges; |
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clocks = <&sysclk K210_CLK_APB1>; |
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wdt0: watchdog@50400000 { |
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compatible = "snps,dw-wdt"; |
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reg = <0x50400000 0x100>; |
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interrupts = <21>; |
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clocks = <&sysclk K210_CLK_WDT0>, |
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<&sysclk K210_CLK_APB1>; |
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clock-names = "tclk", "pclk"; |
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resets = <&sysrst K210_RST_WDT0>; |
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}; |
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wdt1: watchdog@50410000 { |
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compatible = "snps,dw-wdt"; |
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reg = <0x50410000 0x100>; |
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interrupts = <22>; |
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clocks = <&sysclk K210_CLK_WDT1>, |
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<&sysclk K210_CLK_APB1>; |
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clock-names = "tclk", "pclk"; |
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resets = <&sysrst K210_RST_WDT1>; |
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}; |
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sysctl: syscon@50440000 { |
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compatible = "canaan,k210-sysctl", |
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"syscon", "simple-mfd"; |
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reg = <0x50440000 0x100>; |
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clocks = <&sysclk K210_CLK_APB1>; |
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clock-names = "pclk"; |
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sysclk: clock-controller { |
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#clock-cells = <1>; |
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compatible = "canaan,k210-clk"; |
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clocks = <&in0>; |
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}; |
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sysrst: reset-controller { |
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compatible = "canaan,k210-rst"; |
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#reset-cells = <1>; |
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}; |
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reboot: syscon-reboot { |
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compatible = "syscon-reboot"; |
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regmap = <&sysctl>; |
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offset = <48>; |
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mask = <1>; |
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value = <1>; |
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}; |
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}; |
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}; |
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apb2: bus@52000000 { |
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#address-cells = <1>; |
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#size-cells = <1>; |
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compatible = "simple-pm-bus"; |
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ranges; |
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clocks = <&sysclk K210_CLK_APB2>; |
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spi0: spi@52000000 { |
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#address-cells = <1>; |
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#size-cells = <0>; |
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compatible = "canaan,k210-spi"; |
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reg = <0x52000000 0x100>; |
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interrupts = <1>; |
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clocks = <&sysclk K210_CLK_SPI0>, |
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<&sysclk K210_CLK_APB2>; |
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clock-names = "ssi_clk", "pclk"; |
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resets = <&sysrst K210_RST_SPI0>; |
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reset-names = "spi"; |
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spi-max-frequency = <25000000>; |
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num-cs = <4>; |
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reg-io-width = <4>; |
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}; |
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spi1: spi@53000000 { |
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#address-cells = <1>; |
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#size-cells = <0>; |
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compatible = "canaan,k210-spi"; |
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reg = <0x53000000 0x100>; |
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interrupts = <2>; |
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clocks = <&sysclk K210_CLK_SPI1>, |
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<&sysclk K210_CLK_APB2>; |
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clock-names = "ssi_clk", "pclk"; |
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resets = <&sysrst K210_RST_SPI1>; |
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reset-names = "spi"; |
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spi-max-frequency = <25000000>; |
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num-cs = <4>; |
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reg-io-width = <4>; |
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}; |
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spi3: spi@54000000 { |
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#address-cells = <1>; |
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#size-cells = <0>; |
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compatible = "snps,dwc-ssi-1.01a"; |
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reg = <0x54000000 0x200>; |
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interrupts = <4>; |
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clocks = <&sysclk K210_CLK_SPI3>, |
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<&sysclk K210_CLK_APB2>; |
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clock-names = "ssi_clk", "pclk"; |
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resets = <&sysrst K210_RST_SPI3>; |
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reset-names = "spi"; |
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/* Could possibly go up to 200 MHz */ |
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spi-max-frequency = <100000000>; |
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num-cs = <4>; |
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reg-io-width = <4>; |
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}; |
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}; |
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}; |
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};
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