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132 lines
3.5 KiB
132 lines
3.5 KiB
// SPDX-License-Identifier: GPL-2.0-or-later |
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/* |
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* Performance counter support for e500 family processors. |
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* |
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* Copyright 2008-2009 Paul Mackerras, IBM Corporation. |
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* Copyright 2010 Freescale Semiconductor, Inc. |
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*/ |
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#include <linux/string.h> |
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#include <linux/perf_event.h> |
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#include <asm/reg.h> |
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#include <asm/cputable.h> |
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/* |
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* Map of generic hardware event types to hardware events |
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* Zero if unsupported |
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*/ |
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static int e500_generic_events[] = { |
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[PERF_COUNT_HW_CPU_CYCLES] = 1, |
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[PERF_COUNT_HW_INSTRUCTIONS] = 2, |
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[PERF_COUNT_HW_CACHE_MISSES] = 41, /* Data L1 cache reloads */ |
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[PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 12, |
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[PERF_COUNT_HW_BRANCH_MISSES] = 15, |
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[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = 18, |
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[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = 19, |
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}; |
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#define C(x) PERF_COUNT_HW_CACHE_##x |
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/* |
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* Table of generalized cache-related events. |
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* 0 means not supported, -1 means nonsensical, other values |
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* are event codes. |
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*/ |
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static int e500_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = { |
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/* |
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* D-cache misses are not split into read/write/prefetch; |
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* use raw event 41. |
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*/ |
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[C(L1D)] = { /* RESULT_ACCESS RESULT_MISS */ |
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[C(OP_READ)] = { 27, 0 }, |
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[C(OP_WRITE)] = { 28, 0 }, |
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[C(OP_PREFETCH)] = { 29, 0 }, |
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}, |
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[C(L1I)] = { /* RESULT_ACCESS RESULT_MISS */ |
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[C(OP_READ)] = { 2, 60 }, |
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[C(OP_WRITE)] = { -1, -1 }, |
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[C(OP_PREFETCH)] = { 0, 0 }, |
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}, |
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/* |
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* Assuming LL means L2, it's not a good match for this model. |
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* It allocates only on L1 castout or explicit prefetch, and |
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* does not have separate read/write events (but it does have |
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* separate instruction/data events). |
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*/ |
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[C(LL)] = { /* RESULT_ACCESS RESULT_MISS */ |
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[C(OP_READ)] = { 0, 0 }, |
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[C(OP_WRITE)] = { 0, 0 }, |
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[C(OP_PREFETCH)] = { 0, 0 }, |
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}, |
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/* |
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* There are data/instruction MMU misses, but that's a miss on |
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* the chip's internal level-one TLB which is probably not |
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* what the user wants. Instead, unified level-two TLB misses |
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* are reported here. |
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*/ |
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[C(DTLB)] = { /* RESULT_ACCESS RESULT_MISS */ |
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[C(OP_READ)] = { 26, 66 }, |
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[C(OP_WRITE)] = { -1, -1 }, |
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[C(OP_PREFETCH)] = { -1, -1 }, |
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}, |
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[C(BPU)] = { /* RESULT_ACCESS RESULT_MISS */ |
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[C(OP_READ)] = { 12, 15 }, |
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[C(OP_WRITE)] = { -1, -1 }, |
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[C(OP_PREFETCH)] = { -1, -1 }, |
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}, |
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[C(NODE)] = { /* RESULT_ACCESS RESULT_MISS */ |
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[C(OP_READ)] = { -1, -1 }, |
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[C(OP_WRITE)] = { -1, -1 }, |
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[C(OP_PREFETCH)] = { -1, -1 }, |
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}, |
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}; |
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static int num_events = 128; |
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/* Upper half of event id is PMLCb, for threshold events */ |
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static u64 e500_xlate_event(u64 event_id) |
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{ |
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u32 event_low = (u32)event_id; |
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u64 ret; |
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if (event_low >= num_events) |
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return 0; |
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ret = FSL_EMB_EVENT_VALID; |
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if (event_low >= 76 && event_low <= 81) { |
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ret |= FSL_EMB_EVENT_RESTRICTED; |
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ret |= event_id & |
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(FSL_EMB_EVENT_THRESHMUL | FSL_EMB_EVENT_THRESH); |
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} else if (event_id & |
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(FSL_EMB_EVENT_THRESHMUL | FSL_EMB_EVENT_THRESH)) { |
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/* Threshold requested on non-threshold event */ |
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return 0; |
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} |
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return ret; |
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} |
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static struct fsl_emb_pmu e500_pmu = { |
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.name = "e500 family", |
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.n_counter = 4, |
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.n_restricted = 2, |
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.xlate_event = e500_xlate_event, |
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.n_generic = ARRAY_SIZE(e500_generic_events), |
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.generic_events = e500_generic_events, |
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.cache_events = &e500_cache_events, |
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}; |
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static int init_e500_pmu(void) |
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{ |
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if (!cur_cpu_spec->oprofile_cpu_type) |
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return -ENODEV; |
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if (!strcmp(cur_cpu_spec->oprofile_cpu_type, "ppc/e500mc")) |
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num_events = 256; |
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else if (strcmp(cur_cpu_spec->oprofile_cpu_type, "ppc/e500")) |
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return -ENODEV; |
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return register_fsl_emb_pmu(&e500_pmu); |
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} |
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early_initcall(init_e500_pmu);
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