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240 lines
5.4 KiB
240 lines
5.4 KiB
// SPDX-License-Identifier: GPL-2.0 |
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#include <linux/kernel.h> |
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#include <linux/mmzone.h> |
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#include <linux/nodemask.h> |
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#include <linux/spinlock.h> |
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#include <linux/smp.h> |
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#include <linux/atomic.h> |
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#include <asm/sn/types.h> |
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#include <asm/sn/addrs.h> |
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#include <asm/sn/nmi.h> |
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#include <asm/sn/arch.h> |
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#include <asm/sn/agent.h> |
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#if 0 |
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#define NODE_NUM_CPUS(n) CNODE_NUM_CPUS(n) |
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#else |
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#define NODE_NUM_CPUS(n) CPUS_PER_NODE |
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#endif |
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#define SEND_NMI(_nasid, _slice) \ |
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REMOTE_HUB_S((_nasid), (PI_NMI_A + ((_slice) * PI_NMI_OFFSET)), 1) |
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typedef unsigned long machreg_t; |
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static arch_spinlock_t nmi_lock = __ARCH_SPIN_LOCK_UNLOCKED; |
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/* |
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* Let's see what else we need to do here. Set up sp, gp? |
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*/ |
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void nmi_dump(void) |
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{ |
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void cont_nmi_dump(void); |
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cont_nmi_dump(); |
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} |
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void install_cpu_nmi_handler(int slice) |
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{ |
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nmi_t *nmi_addr; |
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nmi_addr = (nmi_t *)NMI_ADDR(get_nasid(), slice); |
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if (nmi_addr->call_addr) |
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return; |
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nmi_addr->magic = NMI_MAGIC; |
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nmi_addr->call_addr = (void *)nmi_dump; |
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nmi_addr->call_addr_c = |
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(void *)(~((unsigned long)(nmi_addr->call_addr))); |
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nmi_addr->call_parm = 0; |
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} |
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/* |
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* Copy the cpu registers which have been saved in the IP27prom format |
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* into the eframe format for the node under consideration. |
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*/ |
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void nmi_cpu_eframe_save(nasid_t nasid, int slice) |
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{ |
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struct reg_struct *nr; |
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int i; |
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/* Get the pointer to the current cpu's register set. */ |
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nr = (struct reg_struct *) |
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(TO_UNCAC(TO_NODE(nasid, IP27_NMI_KREGS_OFFSET)) + |
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slice * IP27_NMI_KREGS_CPU_SIZE); |
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pr_emerg("NMI nasid %d: slice %d\n", nasid, slice); |
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/* |
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* Saved main processor registers |
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*/ |
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for (i = 0; i < 32; ) { |
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if ((i % 4) == 0) |
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pr_emerg("$%2d :", i); |
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pr_cont(" %016lx", nr->gpr[i]); |
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i++; |
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if ((i % 4) == 0) |
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pr_cont("\n"); |
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} |
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pr_emerg("Hi : (value lost)\n"); |
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pr_emerg("Lo : (value lost)\n"); |
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/* |
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* Saved cp0 registers |
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*/ |
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pr_emerg("epc : %016lx %pS\n", nr->epc, (void *)nr->epc); |
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pr_emerg("%s\n", print_tainted()); |
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pr_emerg("ErrEPC: %016lx %pS\n", nr->error_epc, (void *)nr->error_epc); |
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pr_emerg("ra : %016lx %pS\n", nr->gpr[31], (void *)nr->gpr[31]); |
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pr_emerg("Status: %08lx ", nr->sr); |
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if (nr->sr & ST0_KX) |
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pr_cont("KX "); |
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if (nr->sr & ST0_SX) |
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pr_cont("SX "); |
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if (nr->sr & ST0_UX) |
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pr_cont("UX "); |
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switch (nr->sr & ST0_KSU) { |
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case KSU_USER: |
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pr_cont("USER "); |
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break; |
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case KSU_SUPERVISOR: |
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pr_cont("SUPERVISOR "); |
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break; |
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case KSU_KERNEL: |
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pr_cont("KERNEL "); |
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break; |
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default: |
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pr_cont("BAD_MODE "); |
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break; |
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} |
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if (nr->sr & ST0_ERL) |
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pr_cont("ERL "); |
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if (nr->sr & ST0_EXL) |
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pr_cont("EXL "); |
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if (nr->sr & ST0_IE) |
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pr_cont("IE "); |
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pr_cont("\n"); |
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pr_emerg("Cause : %08lx\n", nr->cause); |
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pr_emerg("PrId : %08x\n", read_c0_prid()); |
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pr_emerg("BadVA : %016lx\n", nr->badva); |
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pr_emerg("CErr : %016lx\n", nr->cache_err); |
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pr_emerg("NMI_SR: %016lx\n", nr->nmi_sr); |
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pr_emerg("\n"); |
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} |
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void nmi_dump_hub_irq(nasid_t nasid, int slice) |
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{ |
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u64 mask0, mask1, pend0, pend1; |
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if (slice == 0) { /* Slice A */ |
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mask0 = REMOTE_HUB_L(nasid, PI_INT_MASK0_A); |
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mask1 = REMOTE_HUB_L(nasid, PI_INT_MASK1_A); |
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} else { /* Slice B */ |
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mask0 = REMOTE_HUB_L(nasid, PI_INT_MASK0_B); |
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mask1 = REMOTE_HUB_L(nasid, PI_INT_MASK1_B); |
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} |
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pend0 = REMOTE_HUB_L(nasid, PI_INT_PEND0); |
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pend1 = REMOTE_HUB_L(nasid, PI_INT_PEND1); |
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pr_emerg("PI_INT_MASK0: %16llx PI_INT_MASK1: %16llx\n", mask0, mask1); |
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pr_emerg("PI_INT_PEND0: %16llx PI_INT_PEND1: %16llx\n", pend0, pend1); |
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pr_emerg("\n\n"); |
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} |
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/* |
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* Copy the cpu registers which have been saved in the IP27prom format |
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* into the eframe format for the node under consideration. |
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*/ |
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void nmi_node_eframe_save(nasid_t nasid) |
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{ |
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int slice; |
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if (nasid == INVALID_NASID) |
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return; |
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/* Save the registers into eframe for each cpu */ |
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for (slice = 0; slice < NODE_NUM_CPUS(slice); slice++) { |
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nmi_cpu_eframe_save(nasid, slice); |
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nmi_dump_hub_irq(nasid, slice); |
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} |
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} |
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/* |
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* Save the nmi cpu registers for all cpus in the system. |
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*/ |
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void |
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nmi_eframes_save(void) |
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{ |
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nasid_t nasid; |
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for_each_online_node(nasid) |
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nmi_node_eframe_save(nasid); |
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} |
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void |
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cont_nmi_dump(void) |
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{ |
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#ifndef REAL_NMI_SIGNAL |
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static atomic_t nmied_cpus = ATOMIC_INIT(0); |
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atomic_inc(&nmied_cpus); |
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#endif |
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/* |
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* Only allow 1 cpu to proceed |
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*/ |
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arch_spin_lock(&nmi_lock); |
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#ifdef REAL_NMI_SIGNAL |
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/* |
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* Wait up to 15 seconds for the other cpus to respond to the NMI. |
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* If a cpu has not responded after 10 sec, send it 1 additional NMI. |
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* This is for 2 reasons: |
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* - sometimes a MMSC fail to NMI all cpus. |
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* - on 512p SN0 system, the MMSC will only send NMIs to |
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* half the cpus. Unfortunately, we don't know which cpus may be |
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* NMIed - it depends on how the site chooses to configure. |
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* |
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* Note: it has been measure that it takes the MMSC up to 2.3 secs to |
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* send NMIs to all cpus on a 256p system. |
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*/ |
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for (i=0; i < 1500; i++) { |
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for_each_online_node(node) |
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if (NODEPDA(node)->dump_count == 0) |
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break; |
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if (node == MAX_NUMNODES) |
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break; |
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if (i == 1000) { |
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for_each_online_node(node) |
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if (NODEPDA(node)->dump_count == 0) { |
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cpu = cpumask_first(cpumask_of_node(node)); |
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for (n=0; n < CNODE_NUM_CPUS(node); cpu++, n++) { |
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CPUMASK_SETB(nmied_cpus, cpu); |
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/* |
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* cputonasid, cputoslice |
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* needs kernel cpuid |
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*/ |
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SEND_NMI((cputonasid(cpu)), (cputoslice(cpu))); |
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} |
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} |
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} |
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udelay(10000); |
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} |
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#else |
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while (atomic_read(&nmied_cpus) != num_online_cpus()); |
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#endif |
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/* |
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* Save the nmi cpu registers for all cpu in the eframe format. |
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*/ |
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nmi_eframes_save(); |
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LOCAL_HUB_S(NI_PORT_RESET, NPR_PORTRESET | NPR_LOCALRESET); |
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}
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