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131 lines
2.5 KiB
131 lines
2.5 KiB
// SPDX-License-Identifier: GPL-2.0-only |
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/* |
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* Pistachio platform setup |
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* |
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* Copyright (C) 2014 Google, Inc. |
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* Copyright (C) 2016 Imagination Technologies |
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*/ |
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#include <linux/init.h> |
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#include <linux/io.h> |
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#include <linux/kernel.h> |
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#include <linux/of_address.h> |
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#include <linux/of_fdt.h> |
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#include <asm/cacheflush.h> |
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#include <asm/dma-coherence.h> |
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#include <asm/fw/fw.h> |
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#include <asm/mips-boards/generic.h> |
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#include <asm/mips-cps.h> |
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#include <asm/prom.h> |
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#include <asm/smp-ops.h> |
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#include <asm/traps.h> |
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/* |
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* Core revision register decoding |
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* Bits 23 to 20: Major rev |
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* Bits 15 to 8: Minor rev |
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* Bits 7 to 0: Maintenance rev |
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*/ |
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#define PISTACHIO_CORE_REV_REG 0xB81483D0 |
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#define PISTACHIO_CORE_REV_A1 0x00100006 |
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#define PISTACHIO_CORE_REV_B0 0x00100106 |
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const char *get_system_type(void) |
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{ |
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u32 core_rev; |
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const char *sys_type; |
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core_rev = __raw_readl((const void *)PISTACHIO_CORE_REV_REG); |
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switch (core_rev) { |
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case PISTACHIO_CORE_REV_B0: |
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sys_type = "IMG Pistachio SoC (B0)"; |
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break; |
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case PISTACHIO_CORE_REV_A1: |
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sys_type = "IMG Pistachio SoC (A1)"; |
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break; |
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default: |
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sys_type = "IMG Pistachio SoC"; |
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break; |
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} |
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return sys_type; |
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} |
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void __init *plat_get_fdt(void) |
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{ |
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if (fw_arg0 != -2) |
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panic("Device-tree not present"); |
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return (void *)fw_arg1; |
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} |
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void __init plat_mem_setup(void) |
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{ |
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__dt_setup_arch(plat_get_fdt()); |
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} |
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#define DEFAULT_CPC_BASE_ADDR 0x1bde0000 |
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#define DEFAULT_CDMM_BASE_ADDR 0x1bdd0000 |
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phys_addr_t mips_cpc_default_phys_base(void) |
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{ |
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return DEFAULT_CPC_BASE_ADDR; |
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} |
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phys_addr_t mips_cdmm_phys_base(void) |
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{ |
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return DEFAULT_CDMM_BASE_ADDR; |
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} |
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static void __init mips_nmi_setup(void) |
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{ |
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void *base; |
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extern char except_vec_nmi[]; |
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base = cpu_has_veic ? |
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(void *)(CAC_BASE + 0xa80) : |
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(void *)(CAC_BASE + 0x380); |
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memcpy(base, except_vec_nmi, 0x80); |
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flush_icache_range((unsigned long)base, |
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(unsigned long)base + 0x80); |
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} |
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static void __init mips_ejtag_setup(void) |
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{ |
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void *base; |
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extern char except_vec_ejtag_debug[]; |
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base = cpu_has_veic ? |
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(void *)(CAC_BASE + 0xa00) : |
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(void *)(CAC_BASE + 0x300); |
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memcpy(base, except_vec_ejtag_debug, 0x80); |
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flush_icache_range((unsigned long)base, |
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(unsigned long)base + 0x80); |
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} |
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void __init prom_init(void) |
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{ |
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board_nmi_handler_setup = mips_nmi_setup; |
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board_ejtag_handler_setup = mips_ejtag_setup; |
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mips_cm_probe(); |
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mips_cpc_probe(); |
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register_cps_smp_ops(); |
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pr_info("SoC Type: %s\n", get_system_type()); |
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} |
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void __init prom_free_prom_memory(void) |
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{ |
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} |
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void __init device_tree_init(void) |
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{ |
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if (!initial_boot_params) |
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return; |
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unflatten_and_copy_device_tree(); |
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}
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