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368 lines
9.1 KiB
368 lines
9.1 KiB
/* |
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* Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights |
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* reserved. |
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* |
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* This software is available to you under a choice of one of two |
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* licenses. You may choose to be licensed under the terms of the GNU |
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* General Public License (GPL) Version 2, available from the file |
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* COPYING in the main directory of this source tree, or the NetLogic |
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* license below: |
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* |
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* Redistribution and use in source and binary forms, with or without |
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* modification, are permitted provided that the following conditions |
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* are met: |
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* |
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* 1. Redistributions of source code must retain the above copyright |
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* notice, this list of conditions and the following disclaimer. |
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* 2. Redistributions in binary form must reproduce the above copyright |
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* notice, this list of conditions and the following disclaimer in |
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* the documentation and/or other materials provided with the |
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* distribution. |
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* |
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* THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR |
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED |
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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* ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE |
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR |
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* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, |
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* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE |
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* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN |
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* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
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*/ |
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#include <linux/types.h> |
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#include <linux/pci.h> |
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#include <linux/kernel.h> |
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#include <linux/init.h> |
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#include <linux/msi.h> |
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#include <linux/mm.h> |
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#include <linux/irq.h> |
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#include <linux/irqdesc.h> |
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#include <linux/console.h> |
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#include <linux/pci_regs.h> |
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#include <asm/io.h> |
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#include <asm/netlogic/interrupt.h> |
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#include <asm/netlogic/haldefs.h> |
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#include <asm/netlogic/common.h> |
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#include <asm/netlogic/xlr/msidef.h> |
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#include <asm/netlogic/xlr/iomap.h> |
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#include <asm/netlogic/xlr/pic.h> |
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#include <asm/netlogic/xlr/xlr.h> |
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static void *pci_config_base; |
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#define pci_cfg_addr(bus, devfn, off) (((bus) << 16) | ((devfn) << 8) | (off)) |
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/* PCI ops */ |
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static inline u32 pci_cfg_read_32bit(struct pci_bus *bus, unsigned int devfn, |
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int where) |
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{ |
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u32 data; |
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u32 *cfgaddr; |
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cfgaddr = (u32 *)(pci_config_base + |
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pci_cfg_addr(bus->number, devfn, where & ~3)); |
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data = *cfgaddr; |
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return cpu_to_le32(data); |
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} |
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static inline void pci_cfg_write_32bit(struct pci_bus *bus, unsigned int devfn, |
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int where, u32 data) |
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{ |
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u32 *cfgaddr; |
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cfgaddr = (u32 *)(pci_config_base + |
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pci_cfg_addr(bus->number, devfn, where & ~3)); |
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*cfgaddr = cpu_to_le32(data); |
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} |
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static int nlm_pcibios_read(struct pci_bus *bus, unsigned int devfn, |
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int where, int size, u32 *val) |
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{ |
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u32 data; |
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if ((size == 2) && (where & 1)) |
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return PCIBIOS_BAD_REGISTER_NUMBER; |
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else if ((size == 4) && (where & 3)) |
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return PCIBIOS_BAD_REGISTER_NUMBER; |
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data = pci_cfg_read_32bit(bus, devfn, where); |
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if (size == 1) |
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*val = (data >> ((where & 3) << 3)) & 0xff; |
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else if (size == 2) |
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*val = (data >> ((where & 3) << 3)) & 0xffff; |
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else |
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*val = data; |
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return PCIBIOS_SUCCESSFUL; |
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} |
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static int nlm_pcibios_write(struct pci_bus *bus, unsigned int devfn, |
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int where, int size, u32 val) |
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{ |
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u32 data; |
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if ((size == 2) && (where & 1)) |
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return PCIBIOS_BAD_REGISTER_NUMBER; |
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else if ((size == 4) && (where & 3)) |
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return PCIBIOS_BAD_REGISTER_NUMBER; |
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data = pci_cfg_read_32bit(bus, devfn, where); |
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if (size == 1) |
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data = (data & ~(0xff << ((where & 3) << 3))) | |
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(val << ((where & 3) << 3)); |
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else if (size == 2) |
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data = (data & ~(0xffff << ((where & 3) << 3))) | |
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(val << ((where & 3) << 3)); |
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else |
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data = val; |
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pci_cfg_write_32bit(bus, devfn, where, data); |
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return PCIBIOS_SUCCESSFUL; |
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} |
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struct pci_ops nlm_pci_ops = { |
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.read = nlm_pcibios_read, |
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.write = nlm_pcibios_write |
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}; |
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static struct resource nlm_pci_mem_resource = { |
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.name = "XLR PCI MEM", |
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.start = 0xd0000000UL, /* 256MB PCI mem @ 0xd000_0000 */ |
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.end = 0xdfffffffUL, |
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.flags = IORESOURCE_MEM, |
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}; |
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static struct resource nlm_pci_io_resource = { |
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.name = "XLR IO MEM", |
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.start = 0x10000000UL, /* 16MB PCI IO @ 0x1000_0000 */ |
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.end = 0x100fffffUL, |
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.flags = IORESOURCE_IO, |
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}; |
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struct pci_controller nlm_pci_controller = { |
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.index = 0, |
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.pci_ops = &nlm_pci_ops, |
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.mem_resource = &nlm_pci_mem_resource, |
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.mem_offset = 0x00000000UL, |
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.io_resource = &nlm_pci_io_resource, |
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.io_offset = 0x00000000UL, |
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}; |
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/* |
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* The top level PCIe links on the XLS PCIe controller appear as |
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* bridges. Given a device, this function finds which link it is |
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* on. |
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*/ |
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static struct pci_dev *xls_get_pcie_link(const struct pci_dev *dev) |
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{ |
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struct pci_bus *bus, *p; |
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/* Find the bridge on bus 0 */ |
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bus = dev->bus; |
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for (p = bus->parent; p && p->number != 0; p = p->parent) |
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bus = p; |
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return p ? bus->self : NULL; |
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} |
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static int nlm_pci_link_to_irq(int link) |
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{ |
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switch (link) { |
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case 0: |
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return PIC_PCIE_LINK0_IRQ; |
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case 1: |
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return PIC_PCIE_LINK1_IRQ; |
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case 2: |
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if (nlm_chip_is_xls_b()) |
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return PIC_PCIE_XLSB0_LINK2_IRQ; |
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else |
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return PIC_PCIE_LINK2_IRQ; |
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case 3: |
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if (nlm_chip_is_xls_b()) |
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return PIC_PCIE_XLSB0_LINK3_IRQ; |
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else |
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return PIC_PCIE_LINK3_IRQ; |
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} |
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WARN(1, "Unexpected link %d\n", link); |
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return 0; |
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} |
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static int get_irq_vector(const struct pci_dev *dev) |
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{ |
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struct pci_dev *lnk; |
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int link; |
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if (!nlm_chip_is_xls()) |
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return PIC_PCIX_IRQ; /* for XLR just one IRQ */ |
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lnk = xls_get_pcie_link(dev); |
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if (lnk == NULL) |
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return 0; |
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link = PCI_SLOT(lnk->devfn); |
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return nlm_pci_link_to_irq(link); |
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} |
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#ifdef CONFIG_PCI_MSI |
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void arch_teardown_msi_irq(unsigned int irq) |
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{ |
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} |
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int arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc) |
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{ |
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struct msi_msg msg; |
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struct pci_dev *lnk; |
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int irq, ret; |
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u16 val; |
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/* MSI not supported on XLR */ |
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if (!nlm_chip_is_xls()) |
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return 1; |
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/* |
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* Enable MSI on the XLS PCIe controller bridge which was disabled |
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* at enumeration, the bridge MSI capability is at 0x50 |
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*/ |
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lnk = xls_get_pcie_link(dev); |
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if (lnk == NULL) |
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return 1; |
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pci_read_config_word(lnk, 0x50 + PCI_MSI_FLAGS, &val); |
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if ((val & PCI_MSI_FLAGS_ENABLE) == 0) { |
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val |= PCI_MSI_FLAGS_ENABLE; |
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pci_write_config_word(lnk, 0x50 + PCI_MSI_FLAGS, val); |
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} |
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irq = get_irq_vector(dev); |
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if (irq <= 0) |
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return 1; |
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msg.address_hi = MSI_ADDR_BASE_HI; |
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msg.address_lo = MSI_ADDR_BASE_LO | |
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MSI_ADDR_DEST_MODE_PHYSICAL | |
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MSI_ADDR_REDIRECTION_CPU; |
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msg.data = MSI_DATA_TRIGGER_EDGE | |
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MSI_DATA_LEVEL_ASSERT | |
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MSI_DATA_DELIVERY_FIXED; |
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ret = irq_set_msi_desc(irq, desc); |
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if (ret < 0) |
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return ret; |
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pci_write_msi_msg(irq, &msg); |
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return 0; |
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} |
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#endif |
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/* Extra ACK needed for XLR on chip PCI controller */ |
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static void xlr_pci_ack(struct irq_data *d) |
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{ |
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uint64_t pcibase = nlm_mmio_base(NETLOGIC_IO_PCIX_OFFSET); |
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nlm_read_reg(pcibase, (0x140 >> 2)); |
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} |
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/* Extra ACK needed for XLS on chip PCIe controller */ |
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static void xls_pcie_ack(struct irq_data *d) |
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{ |
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uint64_t pciebase_le = nlm_mmio_base(NETLOGIC_IO_PCIE_1_OFFSET); |
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switch (d->irq) { |
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case PIC_PCIE_LINK0_IRQ: |
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nlm_write_reg(pciebase_le, (0x90 >> 2), 0xffffffff); |
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break; |
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case PIC_PCIE_LINK1_IRQ: |
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nlm_write_reg(pciebase_le, (0x94 >> 2), 0xffffffff); |
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break; |
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case PIC_PCIE_LINK2_IRQ: |
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nlm_write_reg(pciebase_le, (0x190 >> 2), 0xffffffff); |
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break; |
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case PIC_PCIE_LINK3_IRQ: |
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nlm_write_reg(pciebase_le, (0x194 >> 2), 0xffffffff); |
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break; |
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} |
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} |
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/* For XLS B silicon, the 3,4 PCI interrupts are different */ |
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static void xls_pcie_ack_b(struct irq_data *d) |
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{ |
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uint64_t pciebase_le = nlm_mmio_base(NETLOGIC_IO_PCIE_1_OFFSET); |
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switch (d->irq) { |
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case PIC_PCIE_LINK0_IRQ: |
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nlm_write_reg(pciebase_le, (0x90 >> 2), 0xffffffff); |
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break; |
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case PIC_PCIE_LINK1_IRQ: |
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nlm_write_reg(pciebase_le, (0x94 >> 2), 0xffffffff); |
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break; |
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case PIC_PCIE_XLSB0_LINK2_IRQ: |
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nlm_write_reg(pciebase_le, (0x190 >> 2), 0xffffffff); |
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break; |
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case PIC_PCIE_XLSB0_LINK3_IRQ: |
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nlm_write_reg(pciebase_le, (0x194 >> 2), 0xffffffff); |
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break; |
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} |
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} |
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int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) |
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{ |
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return get_irq_vector(dev); |
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} |
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/* Do platform specific device initialization at pci_enable_device() time */ |
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int pcibios_plat_dev_init(struct pci_dev *dev) |
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{ |
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return 0; |
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} |
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static int __init pcibios_init(void) |
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{ |
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void (*extra_ack)(struct irq_data *); |
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int link, irq; |
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/* PSB assigns PCI resources */ |
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pci_set_flags(PCI_PROBE_ONLY); |
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pci_config_base = ioremap(DEFAULT_PCI_CONFIG_BASE, 16 << 20); |
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/* Extend IO port for memory mapped io */ |
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ioport_resource.start = 0; |
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ioport_resource.end = ~0; |
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set_io_port_base(CKSEG1); |
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nlm_pci_controller.io_map_base = CKSEG1; |
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pr_info("Registering XLR/XLS PCIX/PCIE Controller.\n"); |
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register_pci_controller(&nlm_pci_controller); |
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/* |
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* For PCI interrupts, we need to ack the PCI controller too, overload |
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* irq handler data to do this |
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*/ |
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if (!nlm_chip_is_xls()) { |
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/* XLR PCI controller ACK */ |
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nlm_set_pic_extra_ack(0, PIC_PCIX_IRQ, xlr_pci_ack); |
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} else { |
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if (nlm_chip_is_xls_b()) |
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extra_ack = xls_pcie_ack_b; |
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else |
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extra_ack = xls_pcie_ack; |
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for (link = 0; link < 4; link++) { |
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irq = nlm_pci_link_to_irq(link); |
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nlm_set_pic_extra_ack(0, irq, extra_ack); |
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} |
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} |
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return 0; |
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} |
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arch_initcall(pcibios_init);
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