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536 lines
14 KiB
536 lines
14 KiB
// SPDX-License-Identifier: GPL-2.0 |
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/* |
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* Alchemy PCI host mode support. |
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* |
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* Copyright 2001-2003, 2007-2008 MontaVista Software Inc. |
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* Author: MontaVista Software, Inc. <[email protected]> |
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* |
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* Support for all devices (greater than 16) added by David Gathright. |
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*/ |
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#include <linux/clk.h> |
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#include <linux/export.h> |
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#include <linux/types.h> |
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#include <linux/pci.h> |
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#include <linux/platform_device.h> |
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#include <linux/kernel.h> |
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#include <linux/init.h> |
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#include <linux/syscore_ops.h> |
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#include <linux/vmalloc.h> |
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#include <linux/dma-map-ops.h> /* for dma_default_coherent */ |
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#include <asm/mach-au1x00/au1000.h> |
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#include <asm/tlbmisc.h> |
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#ifdef CONFIG_PCI_DEBUG |
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#define DBG(x...) printk(KERN_DEBUG x) |
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#else |
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#define DBG(x...) do {} while (0) |
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#endif |
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#define PCI_ACCESS_READ 0 |
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#define PCI_ACCESS_WRITE 1 |
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struct alchemy_pci_context { |
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struct pci_controller alchemy_pci_ctrl; /* leave as first member! */ |
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void __iomem *regs; /* ctrl base */ |
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/* tools for wired entry for config space access */ |
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unsigned long last_elo0; |
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unsigned long last_elo1; |
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int wired_entry; |
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struct vm_struct *pci_cfg_vm; |
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unsigned long pm[12]; |
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int (*board_map_irq)(const struct pci_dev *d, u8 slot, u8 pin); |
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int (*board_pci_idsel)(unsigned int devsel, int assert); |
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}; |
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/* for syscore_ops. There's only one PCI controller on Alchemy chips, so this |
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* should suffice for now. |
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*/ |
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static struct alchemy_pci_context *__alchemy_pci_ctx; |
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/* IO/MEM resources for PCI. Keep the memres in sync with fixup_bigphys_addr |
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* in arch/mips/alchemy/common/setup.c |
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*/ |
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static struct resource alchemy_pci_def_memres = { |
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.start = ALCHEMY_PCI_MEMWIN_START, |
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.end = ALCHEMY_PCI_MEMWIN_END, |
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.name = "PCI memory space", |
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.flags = IORESOURCE_MEM |
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}; |
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static struct resource alchemy_pci_def_iores = { |
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.start = ALCHEMY_PCI_IOWIN_START, |
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.end = ALCHEMY_PCI_IOWIN_END, |
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.name = "PCI IO space", |
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.flags = IORESOURCE_IO |
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}; |
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static void mod_wired_entry(int entry, unsigned long entrylo0, |
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unsigned long entrylo1, unsigned long entryhi, |
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unsigned long pagemask) |
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{ |
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unsigned long old_pagemask; |
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unsigned long old_ctx; |
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/* Save old context and create impossible VPN2 value */ |
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old_ctx = read_c0_entryhi() & MIPS_ENTRYHI_ASID; |
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old_pagemask = read_c0_pagemask(); |
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write_c0_index(entry); |
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write_c0_pagemask(pagemask); |
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write_c0_entryhi(entryhi); |
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write_c0_entrylo0(entrylo0); |
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write_c0_entrylo1(entrylo1); |
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tlb_write_indexed(); |
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write_c0_entryhi(old_ctx); |
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write_c0_pagemask(old_pagemask); |
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} |
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static void alchemy_pci_wired_entry(struct alchemy_pci_context *ctx) |
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{ |
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ctx->wired_entry = read_c0_wired(); |
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add_wired_entry(0, 0, (unsigned long)ctx->pci_cfg_vm->addr, PM_4K); |
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ctx->last_elo0 = ctx->last_elo1 = ~0; |
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} |
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static int config_access(unsigned char access_type, struct pci_bus *bus, |
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unsigned int dev_fn, unsigned char where, u32 *data) |
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{ |
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struct alchemy_pci_context *ctx = bus->sysdata; |
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unsigned int device = PCI_SLOT(dev_fn); |
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unsigned int function = PCI_FUNC(dev_fn); |
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unsigned long offset, status, cfg_base, flags, entryLo0, entryLo1, r; |
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int error = PCIBIOS_SUCCESSFUL; |
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if (device > 19) { |
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*data = 0xffffffff; |
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return -1; |
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} |
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local_irq_save(flags); |
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r = __raw_readl(ctx->regs + PCI_REG_STATCMD) & 0x0000ffff; |
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r |= PCI_STATCMD_STATUS(0x2000); |
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__raw_writel(r, ctx->regs + PCI_REG_STATCMD); |
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wmb(); |
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/* Allow board vendors to implement their own off-chip IDSEL. |
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* If it doesn't succeed, may as well bail out at this point. |
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*/ |
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if (ctx->board_pci_idsel(device, 1) == 0) { |
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*data = 0xffffffff; |
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local_irq_restore(flags); |
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return -1; |
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} |
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/* Setup the config window */ |
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if (bus->number == 0) |
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cfg_base = (1 << device) << 11; |
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else |
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cfg_base = 0x80000000 | (bus->number << 16) | (device << 11); |
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/* Setup the lower bits of the 36-bit address */ |
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offset = (function << 8) | (where & ~0x3); |
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/* Pick up any address that falls below the page mask */ |
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offset |= cfg_base & ~PAGE_MASK; |
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/* Page boundary */ |
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cfg_base = cfg_base & PAGE_MASK; |
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/* To improve performance, if the current device is the same as |
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* the last device accessed, we don't touch the TLB. |
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*/ |
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entryLo0 = (6 << 26) | (cfg_base >> 6) | (2 << 3) | 7; |
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entryLo1 = (6 << 26) | (cfg_base >> 6) | (0x1000 >> 6) | (2 << 3) | 7; |
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if ((entryLo0 != ctx->last_elo0) || (entryLo1 != ctx->last_elo1)) { |
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mod_wired_entry(ctx->wired_entry, entryLo0, entryLo1, |
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(unsigned long)ctx->pci_cfg_vm->addr, PM_4K); |
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ctx->last_elo0 = entryLo0; |
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ctx->last_elo1 = entryLo1; |
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} |
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if (access_type == PCI_ACCESS_WRITE) |
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__raw_writel(*data, ctx->pci_cfg_vm->addr + offset); |
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else |
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*data = __raw_readl(ctx->pci_cfg_vm->addr + offset); |
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wmb(); |
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DBG("alchemy-pci: cfg access %d bus %u dev %u at %x dat %x conf %lx\n", |
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access_type, bus->number, device, where, *data, offset); |
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/* check for errors, master abort */ |
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status = __raw_readl(ctx->regs + PCI_REG_STATCMD); |
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if (status & (1 << 29)) { |
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*data = 0xffffffff; |
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error = -1; |
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DBG("alchemy-pci: master abort on cfg access %d bus %d dev %d\n", |
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access_type, bus->number, device); |
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} else if ((status >> 28) & 0xf) { |
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DBG("alchemy-pci: PCI ERR detected: dev %d, status %lx\n", |
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device, (status >> 28) & 0xf); |
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/* clear errors */ |
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__raw_writel(status & 0xf000ffff, ctx->regs + PCI_REG_STATCMD); |
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*data = 0xffffffff; |
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error = -1; |
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} |
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/* Take away the IDSEL. */ |
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(void)ctx->board_pci_idsel(device, 0); |
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local_irq_restore(flags); |
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return error; |
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} |
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static int read_config_byte(struct pci_bus *bus, unsigned int devfn, |
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int where, u8 *val) |
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{ |
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u32 data; |
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int ret = config_access(PCI_ACCESS_READ, bus, devfn, where, &data); |
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if (where & 1) |
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data >>= 8; |
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if (where & 2) |
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data >>= 16; |
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*val = data & 0xff; |
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return ret; |
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} |
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static int read_config_word(struct pci_bus *bus, unsigned int devfn, |
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int where, u16 *val) |
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{ |
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u32 data; |
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int ret = config_access(PCI_ACCESS_READ, bus, devfn, where, &data); |
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if (where & 2) |
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data >>= 16; |
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*val = data & 0xffff; |
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return ret; |
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} |
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static int read_config_dword(struct pci_bus *bus, unsigned int devfn, |
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int where, u32 *val) |
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{ |
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return config_access(PCI_ACCESS_READ, bus, devfn, where, val); |
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} |
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static int write_config_byte(struct pci_bus *bus, unsigned int devfn, |
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int where, u8 val) |
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{ |
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u32 data = 0; |
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if (config_access(PCI_ACCESS_READ, bus, devfn, where, &data)) |
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return -1; |
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data = (data & ~(0xff << ((where & 3) << 3))) | |
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(val << ((where & 3) << 3)); |
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if (config_access(PCI_ACCESS_WRITE, bus, devfn, where, &data)) |
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return -1; |
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return PCIBIOS_SUCCESSFUL; |
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} |
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static int write_config_word(struct pci_bus *bus, unsigned int devfn, |
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int where, u16 val) |
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{ |
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u32 data = 0; |
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if (config_access(PCI_ACCESS_READ, bus, devfn, where, &data)) |
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return -1; |
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data = (data & ~(0xffff << ((where & 3) << 3))) | |
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(val << ((where & 3) << 3)); |
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if (config_access(PCI_ACCESS_WRITE, bus, devfn, where, &data)) |
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return -1; |
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return PCIBIOS_SUCCESSFUL; |
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} |
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static int write_config_dword(struct pci_bus *bus, unsigned int devfn, |
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int where, u32 val) |
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{ |
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return config_access(PCI_ACCESS_WRITE, bus, devfn, where, &val); |
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} |
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static int alchemy_pci_read(struct pci_bus *bus, unsigned int devfn, |
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int where, int size, u32 *val) |
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{ |
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switch (size) { |
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case 1: { |
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u8 _val; |
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int rc = read_config_byte(bus, devfn, where, &_val); |
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*val = _val; |
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return rc; |
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} |
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case 2: { |
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u16 _val; |
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int rc = read_config_word(bus, devfn, where, &_val); |
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*val = _val; |
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return rc; |
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} |
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default: |
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return read_config_dword(bus, devfn, where, val); |
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} |
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} |
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static int alchemy_pci_write(struct pci_bus *bus, unsigned int devfn, |
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int where, int size, u32 val) |
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{ |
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switch (size) { |
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case 1: |
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return write_config_byte(bus, devfn, where, (u8) val); |
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case 2: |
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return write_config_word(bus, devfn, where, (u16) val); |
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default: |
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return write_config_dword(bus, devfn, where, val); |
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} |
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} |
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static struct pci_ops alchemy_pci_ops = { |
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.read = alchemy_pci_read, |
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.write = alchemy_pci_write, |
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}; |
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static int alchemy_pci_def_idsel(unsigned int devsel, int assert) |
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{ |
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return 1; /* success */ |
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} |
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/* save PCI controller register contents. */ |
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static int alchemy_pci_suspend(void) |
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{ |
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struct alchemy_pci_context *ctx = __alchemy_pci_ctx; |
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if (!ctx) |
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return 0; |
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ctx->pm[0] = __raw_readl(ctx->regs + PCI_REG_CMEM); |
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ctx->pm[1] = __raw_readl(ctx->regs + PCI_REG_CONFIG) & 0x0009ffff; |
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ctx->pm[2] = __raw_readl(ctx->regs + PCI_REG_B2BMASK_CCH); |
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ctx->pm[3] = __raw_readl(ctx->regs + PCI_REG_B2BBASE0_VID); |
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ctx->pm[4] = __raw_readl(ctx->regs + PCI_REG_B2BBASE1_SID); |
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ctx->pm[5] = __raw_readl(ctx->regs + PCI_REG_MWMASK_DEV); |
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ctx->pm[6] = __raw_readl(ctx->regs + PCI_REG_MWBASE_REV_CCL); |
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ctx->pm[7] = __raw_readl(ctx->regs + PCI_REG_ID); |
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ctx->pm[8] = __raw_readl(ctx->regs + PCI_REG_CLASSREV); |
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ctx->pm[9] = __raw_readl(ctx->regs + PCI_REG_PARAM); |
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ctx->pm[10] = __raw_readl(ctx->regs + PCI_REG_MBAR); |
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ctx->pm[11] = __raw_readl(ctx->regs + PCI_REG_TIMEOUT); |
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return 0; |
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} |
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static void alchemy_pci_resume(void) |
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{ |
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struct alchemy_pci_context *ctx = __alchemy_pci_ctx; |
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if (!ctx) |
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return; |
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__raw_writel(ctx->pm[0], ctx->regs + PCI_REG_CMEM); |
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__raw_writel(ctx->pm[2], ctx->regs + PCI_REG_B2BMASK_CCH); |
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__raw_writel(ctx->pm[3], ctx->regs + PCI_REG_B2BBASE0_VID); |
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__raw_writel(ctx->pm[4], ctx->regs + PCI_REG_B2BBASE1_SID); |
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__raw_writel(ctx->pm[5], ctx->regs + PCI_REG_MWMASK_DEV); |
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__raw_writel(ctx->pm[6], ctx->regs + PCI_REG_MWBASE_REV_CCL); |
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__raw_writel(ctx->pm[7], ctx->regs + PCI_REG_ID); |
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__raw_writel(ctx->pm[8], ctx->regs + PCI_REG_CLASSREV); |
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__raw_writel(ctx->pm[9], ctx->regs + PCI_REG_PARAM); |
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__raw_writel(ctx->pm[10], ctx->regs + PCI_REG_MBAR); |
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__raw_writel(ctx->pm[11], ctx->regs + PCI_REG_TIMEOUT); |
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wmb(); |
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__raw_writel(ctx->pm[1], ctx->regs + PCI_REG_CONFIG); |
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wmb(); |
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/* YAMON on all db1xxx boards wipes the TLB and writes zero to C0_wired |
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* on resume, making it necessary to recreate it as soon as possible. |
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*/ |
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ctx->wired_entry = 8191; /* impossibly high value */ |
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alchemy_pci_wired_entry(ctx); /* install it */ |
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} |
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static struct syscore_ops alchemy_pci_pmops = { |
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.suspend = alchemy_pci_suspend, |
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.resume = alchemy_pci_resume, |
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}; |
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static int alchemy_pci_probe(struct platform_device *pdev) |
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{ |
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struct alchemy_pci_platdata *pd = pdev->dev.platform_data; |
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struct alchemy_pci_context *ctx; |
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void __iomem *virt_io; |
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unsigned long val; |
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struct resource *r; |
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struct clk *c; |
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int ret; |
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/* need at least PCI IRQ mapping table */ |
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if (!pd) { |
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dev_err(&pdev->dev, "need platform data for PCI setup\n"); |
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ret = -ENODEV; |
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goto out; |
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} |
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ctx = kzalloc(sizeof(*ctx), GFP_KERNEL); |
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if (!ctx) { |
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dev_err(&pdev->dev, "no memory for pcictl context\n"); |
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ret = -ENOMEM; |
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goto out; |
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} |
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r = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
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if (!r) { |
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dev_err(&pdev->dev, "no pcictl ctrl regs resource\n"); |
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ret = -ENODEV; |
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goto out1; |
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} |
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if (!request_mem_region(r->start, resource_size(r), pdev->name)) { |
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dev_err(&pdev->dev, "cannot claim pci regs\n"); |
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ret = -ENODEV; |
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goto out1; |
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} |
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c = clk_get(&pdev->dev, "pci_clko"); |
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if (IS_ERR(c)) { |
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dev_err(&pdev->dev, "unable to find PCI clock\n"); |
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ret = PTR_ERR(c); |
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goto out2; |
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} |
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ret = clk_prepare_enable(c); |
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if (ret) { |
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dev_err(&pdev->dev, "cannot enable PCI clock\n"); |
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goto out6; |
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} |
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ctx->regs = ioremap(r->start, resource_size(r)); |
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if (!ctx->regs) { |
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dev_err(&pdev->dev, "cannot map pci regs\n"); |
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ret = -ENODEV; |
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goto out5; |
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} |
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/* map parts of the PCI IO area */ |
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/* REVISIT: if this changes with a newer variant (doubt it) make this |
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* a platform resource. |
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*/ |
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virt_io = ioremap(AU1500_PCI_IO_PHYS_ADDR, 0x00100000); |
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if (!virt_io) { |
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dev_err(&pdev->dev, "cannot remap pci io space\n"); |
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ret = -ENODEV; |
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goto out3; |
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} |
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ctx->alchemy_pci_ctrl.io_map_base = (unsigned long)virt_io; |
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/* Au1500 revisions older than AD have borked coherent PCI */ |
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if (alchemy_get_cputype() == ALCHEMY_CPU_AU1500 && |
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read_c0_prid() < 0x01030202 && !dma_default_coherent) { |
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val = __raw_readl(ctx->regs + PCI_REG_CONFIG); |
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val |= PCI_CONFIG_NC; |
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__raw_writel(val, ctx->regs + PCI_REG_CONFIG); |
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wmb(); |
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dev_info(&pdev->dev, "non-coherent PCI on Au1500 AA/AB/AC\n"); |
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} |
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if (pd->board_map_irq) |
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ctx->board_map_irq = pd->board_map_irq; |
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if (pd->board_pci_idsel) |
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ctx->board_pci_idsel = pd->board_pci_idsel; |
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else |
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ctx->board_pci_idsel = alchemy_pci_def_idsel; |
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/* fill in relevant pci_controller members */ |
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ctx->alchemy_pci_ctrl.pci_ops = &alchemy_pci_ops; |
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ctx->alchemy_pci_ctrl.mem_resource = &alchemy_pci_def_memres; |
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ctx->alchemy_pci_ctrl.io_resource = &alchemy_pci_def_iores; |
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/* we can't ioremap the entire pci config space because it's too large, |
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* nor can we dynamically ioremap it because some drivers use the |
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* PCI config routines from within atomic contex and that becomes a |
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* problem in get_vm_area(). Instead we use one wired TLB entry to |
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* handle all config accesses for all busses. |
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*/ |
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ctx->pci_cfg_vm = get_vm_area(0x2000, VM_IOREMAP); |
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if (!ctx->pci_cfg_vm) { |
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dev_err(&pdev->dev, "unable to get vm area\n"); |
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ret = -ENOMEM; |
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goto out4; |
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} |
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ctx->wired_entry = 8191; /* impossibly high value */ |
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alchemy_pci_wired_entry(ctx); /* install it */ |
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set_io_port_base((unsigned long)ctx->alchemy_pci_ctrl.io_map_base); |
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/* board may want to modify bits in the config register, do it now */ |
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val = __raw_readl(ctx->regs + PCI_REG_CONFIG); |
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val &= ~pd->pci_cfg_clr; |
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val |= pd->pci_cfg_set; |
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val &= ~PCI_CONFIG_PD; /* clear disable bit */ |
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__raw_writel(val, ctx->regs + PCI_REG_CONFIG); |
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wmb(); |
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__alchemy_pci_ctx = ctx; |
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platform_set_drvdata(pdev, ctx); |
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register_syscore_ops(&alchemy_pci_pmops); |
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register_pci_controller(&ctx->alchemy_pci_ctrl); |
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dev_info(&pdev->dev, "PCI controller at %ld MHz\n", |
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clk_get_rate(c) / 1000000); |
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return 0; |
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out4: |
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iounmap(virt_io); |
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out3: |
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iounmap(ctx->regs); |
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out5: |
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clk_disable_unprepare(c); |
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out6: |
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clk_put(c); |
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out2: |
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release_mem_region(r->start, resource_size(r)); |
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out1: |
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kfree(ctx); |
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out: |
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return ret; |
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} |
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static struct platform_driver alchemy_pcictl_driver = { |
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.probe = alchemy_pci_probe, |
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.driver = { |
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.name = "alchemy-pci", |
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}, |
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}; |
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static int __init alchemy_pci_init(void) |
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{ |
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/* Au1500/Au1550 have PCI */ |
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switch (alchemy_get_cputype()) { |
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case ALCHEMY_CPU_AU1500: |
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case ALCHEMY_CPU_AU1550: |
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return platform_driver_register(&alchemy_pcictl_driver); |
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} |
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return 0; |
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} |
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arch_initcall(alchemy_pci_init); |
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int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) |
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{ |
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struct alchemy_pci_context *ctx = dev->sysdata; |
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if (ctx && ctx->board_map_irq) |
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return ctx->board_map_irq(dev, slot, pin); |
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return -1; |
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} |
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int pcibios_plat_dev_init(struct pci_dev *dev) |
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{ |
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return 0; |
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}
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