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284 lines
6.6 KiB
284 lines
6.6 KiB
// SPDX-License-Identifier: GPL-2.0 |
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/* |
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* r2300.c: R2000 and R3000 specific mmu/cache code. |
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* |
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* Copyright (C) 1996 David S. Miller ([email protected]) |
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* |
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* with a lot of changes to make this thing work for R3000s |
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* Tx39XX R4k style caches added. HK |
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* Copyright (C) 1998, 1999, 2000 Harald Koerfgen |
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* Copyright (C) 1998 Gleb Raiko & Vladimir Roganov |
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* Copyright (C) 2002 Ralf Baechle |
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* Copyright (C) 2002 Maciej W. Rozycki |
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*/ |
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#include <linux/kernel.h> |
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#include <linux/sched.h> |
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#include <linux/smp.h> |
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#include <linux/mm.h> |
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#include <asm/page.h> |
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#include <asm/mmu_context.h> |
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#include <asm/tlbmisc.h> |
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#include <asm/isadep.h> |
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#include <asm/io.h> |
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#include <asm/bootinfo.h> |
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#include <asm/cpu.h> |
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#undef DEBUG_TLB |
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extern void build_tlb_refill_handler(void); |
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/* CP0 hazard avoidance. */ |
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#define BARRIER \ |
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__asm__ __volatile__( \ |
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".set push\n\t" \ |
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".set noreorder\n\t" \ |
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"nop\n\t" \ |
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".set pop\n\t") |
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int r3k_have_wired_reg; /* Should be in cpu_data? */ |
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/* TLB operations. */ |
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static void local_flush_tlb_from(int entry) |
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{ |
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unsigned long old_ctx; |
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old_ctx = read_c0_entryhi() & cpu_asid_mask(¤t_cpu_data); |
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write_c0_entrylo0(0); |
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while (entry < current_cpu_data.tlbsize) { |
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write_c0_index(entry << 8); |
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write_c0_entryhi((entry | 0x80000) << 12); |
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entry++; /* BARRIER */ |
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tlb_write_indexed(); |
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} |
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write_c0_entryhi(old_ctx); |
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} |
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void local_flush_tlb_all(void) |
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{ |
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unsigned long flags; |
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#ifdef DEBUG_TLB |
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printk("[tlball]"); |
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#endif |
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local_irq_save(flags); |
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local_flush_tlb_from(r3k_have_wired_reg ? read_c0_wired() : 8); |
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local_irq_restore(flags); |
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} |
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void local_flush_tlb_range(struct vm_area_struct *vma, unsigned long start, |
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unsigned long end) |
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{ |
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unsigned long asid_mask = cpu_asid_mask(¤t_cpu_data); |
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struct mm_struct *mm = vma->vm_mm; |
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int cpu = smp_processor_id(); |
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if (cpu_context(cpu, mm) != 0) { |
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unsigned long size, flags; |
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#ifdef DEBUG_TLB |
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printk("[tlbrange<%lu,0x%08lx,0x%08lx>]", |
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cpu_context(cpu, mm) & asid_mask, start, end); |
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#endif |
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local_irq_save(flags); |
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size = (end - start + (PAGE_SIZE - 1)) >> PAGE_SHIFT; |
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if (size <= current_cpu_data.tlbsize) { |
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int oldpid = read_c0_entryhi() & asid_mask; |
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int newpid = cpu_context(cpu, mm) & asid_mask; |
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start &= PAGE_MASK; |
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end += PAGE_SIZE - 1; |
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end &= PAGE_MASK; |
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while (start < end) { |
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int idx; |
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write_c0_entryhi(start | newpid); |
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start += PAGE_SIZE; /* BARRIER */ |
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tlb_probe(); |
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idx = read_c0_index(); |
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write_c0_entrylo0(0); |
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write_c0_entryhi(KSEG0); |
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if (idx < 0) /* BARRIER */ |
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continue; |
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tlb_write_indexed(); |
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} |
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write_c0_entryhi(oldpid); |
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} else { |
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drop_mmu_context(mm); |
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} |
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local_irq_restore(flags); |
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} |
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} |
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void local_flush_tlb_kernel_range(unsigned long start, unsigned long end) |
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{ |
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unsigned long size, flags; |
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#ifdef DEBUG_TLB |
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printk("[tlbrange<%lu,0x%08lx,0x%08lx>]", start, end); |
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#endif |
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local_irq_save(flags); |
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size = (end - start + (PAGE_SIZE - 1)) >> PAGE_SHIFT; |
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if (size <= current_cpu_data.tlbsize) { |
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int pid = read_c0_entryhi(); |
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start &= PAGE_MASK; |
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end += PAGE_SIZE - 1; |
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end &= PAGE_MASK; |
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while (start < end) { |
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int idx; |
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write_c0_entryhi(start); |
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start += PAGE_SIZE; /* BARRIER */ |
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tlb_probe(); |
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idx = read_c0_index(); |
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write_c0_entrylo0(0); |
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write_c0_entryhi(KSEG0); |
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if (idx < 0) /* BARRIER */ |
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continue; |
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tlb_write_indexed(); |
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} |
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write_c0_entryhi(pid); |
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} else { |
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local_flush_tlb_all(); |
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} |
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local_irq_restore(flags); |
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} |
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void local_flush_tlb_page(struct vm_area_struct *vma, unsigned long page) |
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{ |
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unsigned long asid_mask = cpu_asid_mask(¤t_cpu_data); |
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int cpu = smp_processor_id(); |
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if (cpu_context(cpu, vma->vm_mm) != 0) { |
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unsigned long flags; |
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int oldpid, newpid, idx; |
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#ifdef DEBUG_TLB |
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printk("[tlbpage<%lu,0x%08lx>]", cpu_context(cpu, vma->vm_mm), page); |
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#endif |
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newpid = cpu_context(cpu, vma->vm_mm) & asid_mask; |
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page &= PAGE_MASK; |
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local_irq_save(flags); |
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oldpid = read_c0_entryhi() & asid_mask; |
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write_c0_entryhi(page | newpid); |
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BARRIER; |
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tlb_probe(); |
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idx = read_c0_index(); |
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write_c0_entrylo0(0); |
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write_c0_entryhi(KSEG0); |
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if (idx < 0) /* BARRIER */ |
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goto finish; |
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tlb_write_indexed(); |
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finish: |
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write_c0_entryhi(oldpid); |
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local_irq_restore(flags); |
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} |
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} |
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void __update_tlb(struct vm_area_struct *vma, unsigned long address, pte_t pte) |
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{ |
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unsigned long asid_mask = cpu_asid_mask(¤t_cpu_data); |
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unsigned long flags; |
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int idx, pid; |
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/* |
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* Handle debugger faulting in for debugee. |
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*/ |
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if (current->active_mm != vma->vm_mm) |
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return; |
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pid = read_c0_entryhi() & asid_mask; |
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#ifdef DEBUG_TLB |
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if ((pid != (cpu_context(cpu, vma->vm_mm) & asid_mask)) || (cpu_context(cpu, vma->vm_mm) == 0)) { |
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printk("update_mmu_cache: Wheee, bogus tlbpid mmpid=%lu tlbpid=%d\n", |
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(cpu_context(cpu, vma->vm_mm)), pid); |
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} |
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#endif |
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local_irq_save(flags); |
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address &= PAGE_MASK; |
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write_c0_entryhi(address | pid); |
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BARRIER; |
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tlb_probe(); |
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idx = read_c0_index(); |
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write_c0_entrylo0(pte_val(pte)); |
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write_c0_entryhi(address | pid); |
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if (idx < 0) { /* BARRIER */ |
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tlb_write_random(); |
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} else { |
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tlb_write_indexed(); |
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} |
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write_c0_entryhi(pid); |
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local_irq_restore(flags); |
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} |
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void add_wired_entry(unsigned long entrylo0, unsigned long entrylo1, |
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unsigned long entryhi, unsigned long pagemask) |
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{ |
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unsigned long asid_mask = cpu_asid_mask(¤t_cpu_data); |
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unsigned long flags; |
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unsigned long old_ctx; |
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static unsigned long wired = 0; |
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if (r3k_have_wired_reg) { /* TX39XX */ |
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unsigned long old_pagemask; |
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unsigned long w; |
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#ifdef DEBUG_TLB |
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printk("[tlbwired<entry lo0 %8x, hi %8x\n, pagemask %8x>]\n", |
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entrylo0, entryhi, pagemask); |
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#endif |
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local_irq_save(flags); |
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/* Save old context and create impossible VPN2 value */ |
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old_ctx = read_c0_entryhi() & asid_mask; |
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old_pagemask = read_c0_pagemask(); |
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w = read_c0_wired(); |
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write_c0_wired(w + 1); |
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write_c0_index(w << 8); |
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write_c0_pagemask(pagemask); |
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write_c0_entryhi(entryhi); |
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write_c0_entrylo0(entrylo0); |
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BARRIER; |
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tlb_write_indexed(); |
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write_c0_entryhi(old_ctx); |
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write_c0_pagemask(old_pagemask); |
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local_flush_tlb_all(); |
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local_irq_restore(flags); |
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} else if (wired < 8) { |
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#ifdef DEBUG_TLB |
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printk("[tlbwired<entry lo0 %8x, hi %8x\n>]\n", |
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entrylo0, entryhi); |
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#endif |
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local_irq_save(flags); |
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old_ctx = read_c0_entryhi() & asid_mask; |
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write_c0_entrylo0(entrylo0); |
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write_c0_entryhi(entryhi); |
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write_c0_index(wired); |
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wired++; /* BARRIER */ |
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tlb_write_indexed(); |
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write_c0_entryhi(old_ctx); |
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local_flush_tlb_all(); |
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local_irq_restore(flags); |
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} |
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} |
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void tlb_init(void) |
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{ |
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switch (current_cpu_type()) { |
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case CPU_TX3922: |
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case CPU_TX3927: |
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r3k_have_wired_reg = 1; |
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write_c0_wired(0); /* Set to 8 on reset... */ |
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break; |
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} |
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local_flush_tlb_from(0); |
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build_tlb_refill_handler(); |
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}
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