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138 lines
3.7 KiB
138 lines
3.7 KiB
// SPDX-License-Identifier: GPL-2.0-or-later |
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/* |
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* Copyright (C) 2000,2001,2004 Broadcom Corporation |
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*/ |
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#include <linux/clockchips.h> |
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#include <linux/interrupt.h> |
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#include <linux/percpu.h> |
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#include <linux/smp.h> |
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#include <linux/irq.h> |
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#include <asm/addrspace.h> |
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#include <asm/io.h> |
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#include <asm/time.h> |
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#include <asm/sibyte/bcm1480_regs.h> |
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#include <asm/sibyte/sb1250_regs.h> |
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#include <asm/sibyte/bcm1480_int.h> |
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#include <asm/sibyte/bcm1480_scd.h> |
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#include <asm/sibyte/sb1250.h> |
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#define IMR_IP2_VAL K_BCM1480_INT_MAP_I0 |
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#define IMR_IP3_VAL K_BCM1480_INT_MAP_I1 |
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#define IMR_IP4_VAL K_BCM1480_INT_MAP_I2 |
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/* |
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* The general purpose timer ticks at 1MHz independent if |
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* the rest of the system |
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*/ |
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static int sibyte_set_periodic(struct clock_event_device *evt) |
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{ |
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unsigned int cpu = smp_processor_id(); |
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void __iomem *cfg, *init; |
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cfg = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG)); |
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init = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_INIT)); |
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__raw_writeq(0, cfg); |
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__raw_writeq((V_SCD_TIMER_FREQ / HZ) - 1, init); |
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__raw_writeq(M_SCD_TIMER_ENABLE | M_SCD_TIMER_MODE_CONTINUOUS, cfg); |
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return 0; |
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} |
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static int sibyte_shutdown(struct clock_event_device *evt) |
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{ |
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unsigned int cpu = smp_processor_id(); |
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void __iomem *cfg; |
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cfg = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG)); |
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/* Stop the timer until we actually program a shot */ |
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__raw_writeq(0, cfg); |
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return 0; |
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} |
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static int sibyte_next_event(unsigned long delta, struct clock_event_device *cd) |
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{ |
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unsigned int cpu = smp_processor_id(); |
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void __iomem *cfg, *init; |
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cfg = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG)); |
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init = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_INIT)); |
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__raw_writeq(0, cfg); |
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__raw_writeq(delta - 1, init); |
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__raw_writeq(M_SCD_TIMER_ENABLE, cfg); |
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return 0; |
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} |
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static irqreturn_t sibyte_counter_handler(int irq, void *dev_id) |
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{ |
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unsigned int cpu = smp_processor_id(); |
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struct clock_event_device *cd = dev_id; |
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void __iomem *cfg; |
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unsigned long tmode; |
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if (clockevent_state_periodic(cd)) |
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tmode = M_SCD_TIMER_ENABLE | M_SCD_TIMER_MODE_CONTINUOUS; |
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else |
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tmode = 0; |
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/* ACK interrupt */ |
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cfg = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG)); |
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____raw_writeq(tmode, cfg); |
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cd->event_handler(cd); |
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return IRQ_HANDLED; |
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} |
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static DEFINE_PER_CPU(struct clock_event_device, sibyte_hpt_clockevent); |
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static DEFINE_PER_CPU(char [18], sibyte_hpt_name); |
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void sb1480_clockevent_init(void) |
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{ |
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unsigned int cpu = smp_processor_id(); |
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unsigned int irq = K_BCM1480_INT_TIMER_0 + cpu; |
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struct clock_event_device *cd = &per_cpu(sibyte_hpt_clockevent, cpu); |
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unsigned char *name = per_cpu(sibyte_hpt_name, cpu); |
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unsigned long flags = IRQF_PERCPU | IRQF_TIMER; |
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BUG_ON(cpu > 3); /* Only have 4 general purpose timers */ |
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sprintf(name, "bcm1480-counter-%d", cpu); |
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cd->name = name; |
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cd->features = CLOCK_EVT_FEAT_PERIODIC | |
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CLOCK_EVT_FEAT_ONESHOT; |
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clockevent_set_clock(cd, V_SCD_TIMER_FREQ); |
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cd->max_delta_ns = clockevent_delta2ns(0x7fffff, cd); |
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cd->max_delta_ticks = 0x7fffff; |
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cd->min_delta_ns = clockevent_delta2ns(2, cd); |
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cd->min_delta_ticks = 2; |
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cd->rating = 200; |
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cd->irq = irq; |
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cd->cpumask = cpumask_of(cpu); |
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cd->set_next_event = sibyte_next_event; |
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cd->set_state_shutdown = sibyte_shutdown; |
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cd->set_state_periodic = sibyte_set_periodic; |
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cd->set_state_oneshot = sibyte_shutdown; |
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clockevents_register_device(cd); |
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bcm1480_mask_irq(cpu, irq); |
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/* |
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* Map the timer interrupt to IP[4] of this cpu |
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*/ |
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__raw_writeq(IMR_IP4_VAL, |
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IOADDR(A_BCM1480_IMR_REGISTER(cpu, |
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R_BCM1480_IMR_INTERRUPT_MAP_BASE_H) + (irq << 3))); |
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bcm1480_unmask_irq(cpu, irq); |
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irq_set_affinity(irq, cpumask_of(cpu)); |
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if (request_irq(irq, sibyte_counter_handler, flags, name, cd)) |
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pr_err("Failed to request irq %d (%s)\n", irq, name); |
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}
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