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196 lines
4.9 KiB
196 lines
4.9 KiB
// SPDX-License-Identifier: GPL-2.0-or-later |
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/* |
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* Bus error event handling code for DECstation/DECsystem 3100 |
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* and 2100 (KN01) systems equipped with parity error detection |
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* logic. |
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* |
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* Copyright (c) 2005 Maciej W. Rozycki |
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*/ |
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#include <linux/init.h> |
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#include <linux/interrupt.h> |
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#include <linux/kernel.h> |
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#include <linux/spinlock.h> |
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#include <linux/types.h> |
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#include <asm/inst.h> |
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#include <asm/irq_regs.h> |
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#include <asm/mipsregs.h> |
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#include <asm/page.h> |
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#include <asm/ptrace.h> |
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#include <asm/traps.h> |
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#include <linux/uaccess.h> |
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#include <asm/dec/kn01.h> |
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/* CP0 hazard avoidance. */ |
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#define BARRIER \ |
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__asm__ __volatile__( \ |
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".set push\n\t" \ |
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".set noreorder\n\t" \ |
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"nop\n\t" \ |
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".set pop\n\t") |
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/* |
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* Bits 7:0 of the Control Register are write-only -- the |
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* corresponding bits of the Status Register have a different |
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* meaning. Hence we use a cache. It speeds up things a bit |
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* as well. |
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* |
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* There is no default value -- it has to be initialized. |
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*/ |
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u16 cached_kn01_csr; |
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static DEFINE_RAW_SPINLOCK(kn01_lock); |
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static inline void dec_kn01_be_ack(void) |
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{ |
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volatile u16 *csr = (void *)CKSEG1ADDR(KN01_SLOT_BASE + KN01_CSR); |
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unsigned long flags; |
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raw_spin_lock_irqsave(&kn01_lock, flags); |
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*csr = cached_kn01_csr | KN01_CSR_MEMERR; /* Clear bus IRQ. */ |
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iob(); |
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raw_spin_unlock_irqrestore(&kn01_lock, flags); |
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} |
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static int dec_kn01_be_backend(struct pt_regs *regs, int is_fixup, int invoker) |
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{ |
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volatile u32 *kn01_erraddr = (void *)CKSEG1ADDR(KN01_SLOT_BASE + |
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KN01_ERRADDR); |
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static const char excstr[] = "exception"; |
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static const char intstr[] = "interrupt"; |
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static const char cpustr[] = "CPU"; |
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static const char mreadstr[] = "memory read"; |
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static const char readstr[] = "read"; |
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static const char writestr[] = "write"; |
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static const char timestr[] = "timeout"; |
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static const char paritystr[] = "parity error"; |
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int data = regs->cp0_cause & 4; |
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unsigned int __user *pc = (unsigned int __user *)regs->cp0_epc + |
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((regs->cp0_cause & CAUSEF_BD) != 0); |
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union mips_instruction insn; |
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unsigned long entrylo, offset; |
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long asid, entryhi, vaddr; |
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const char *kind, *agent, *cycle, *event; |
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unsigned long address; |
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u32 erraddr = *kn01_erraddr; |
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int action = MIPS_BE_FATAL; |
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/* Ack ASAP, so that any subsequent errors get caught. */ |
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dec_kn01_be_ack(); |
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kind = invoker ? intstr : excstr; |
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agent = cpustr; |
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if (invoker) |
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address = erraddr; |
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else { |
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/* Bloody hardware doesn't record the address for reads... */ |
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if (data) { |
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/* This never faults. */ |
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__get_user(insn.word, pc); |
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vaddr = regs->regs[insn.i_format.rs] + |
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insn.i_format.simmediate; |
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} else |
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vaddr = (long)pc; |
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if (KSEGX(vaddr) == CKSEG0 || KSEGX(vaddr) == CKSEG1) |
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address = CPHYSADDR(vaddr); |
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else { |
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/* Peek at what physical address the CPU used. */ |
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asid = read_c0_entryhi(); |
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entryhi = asid & (PAGE_SIZE - 1); |
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entryhi |= vaddr & ~(PAGE_SIZE - 1); |
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write_c0_entryhi(entryhi); |
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BARRIER; |
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tlb_probe(); |
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/* No need to check for presence. */ |
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tlb_read(); |
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entrylo = read_c0_entrylo0(); |
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write_c0_entryhi(asid); |
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offset = vaddr & (PAGE_SIZE - 1); |
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address = (entrylo & ~(PAGE_SIZE - 1)) | offset; |
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} |
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} |
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/* Treat low 256MB as memory, high -- as I/O. */ |
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if (address < 0x10000000) { |
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cycle = mreadstr; |
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event = paritystr; |
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} else { |
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cycle = invoker ? writestr : readstr; |
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event = timestr; |
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} |
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if (is_fixup) |
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action = MIPS_BE_FIXUP; |
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if (action != MIPS_BE_FIXUP) |
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printk(KERN_ALERT "Bus error %s: %s %s %s at %#010lx\n", |
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kind, agent, cycle, event, address); |
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return action; |
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} |
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int dec_kn01_be_handler(struct pt_regs *regs, int is_fixup) |
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{ |
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return dec_kn01_be_backend(regs, is_fixup, 0); |
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} |
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irqreturn_t dec_kn01_be_interrupt(int irq, void *dev_id) |
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{ |
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volatile u16 *csr = (void *)CKSEG1ADDR(KN01_SLOT_BASE + KN01_CSR); |
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struct pt_regs *regs = get_irq_regs(); |
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int action; |
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if (!(*csr & KN01_CSR_MEMERR)) |
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return IRQ_NONE; /* Must have been video. */ |
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action = dec_kn01_be_backend(regs, 0, 1); |
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if (action == MIPS_BE_DISCARD) |
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return IRQ_HANDLED; |
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/* |
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* FIXME: Find the affected processes and kill them, otherwise |
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* we must die. |
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* |
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* The interrupt is asynchronously delivered thus EPC and RA |
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* may be irrelevant, but are printed for a reference. |
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*/ |
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printk(KERN_ALERT "Fatal bus interrupt, epc == %08lx, ra == %08lx\n", |
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regs->cp0_epc, regs->regs[31]); |
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die("Unrecoverable bus error", regs); |
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} |
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void __init dec_kn01_be_init(void) |
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{ |
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volatile u16 *csr = (void *)CKSEG1ADDR(KN01_SLOT_BASE + KN01_CSR); |
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unsigned long flags; |
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raw_spin_lock_irqsave(&kn01_lock, flags); |
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/* Preset write-only bits of the Control Register cache. */ |
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cached_kn01_csr = *csr; |
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cached_kn01_csr &= KN01_CSR_STATUS | KN01_CSR_PARDIS | KN01_CSR_TXDIS; |
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cached_kn01_csr |= KN01_CSR_LEDS; |
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/* Enable parity error detection. */ |
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cached_kn01_csr &= ~KN01_CSR_PARDIS; |
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*csr = cached_kn01_csr; |
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iob(); |
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raw_spin_unlock_irqrestore(&kn01_lock, flags); |
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/* Clear any leftover errors from the firmware. */ |
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dec_kn01_be_ack(); |
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}
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