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185 lines
5.8 KiB
185 lines
5.8 KiB
/* |
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* intc.c -- interrupt controller or ColdFire 5272 SoC |
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* |
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* (C) Copyright 2009, Greg Ungerer <[email protected]> |
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* |
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* This file is subject to the terms and conditions of the GNU General Public |
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* License. See the file COPYING in the main directory of this archive |
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* for more details. |
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*/ |
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#include <linux/types.h> |
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#include <linux/init.h> |
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#include <linux/kernel.h> |
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#include <linux/interrupt.h> |
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#include <linux/kernel_stat.h> |
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#include <linux/irq.h> |
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#include <linux/io.h> |
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#include <asm/coldfire.h> |
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#include <asm/mcfsim.h> |
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#include <asm/traps.h> |
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/* |
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* The 5272 ColdFire interrupt controller is nothing like any other |
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* ColdFire interrupt controller - it truly is completely different. |
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* Given its age it is unlikely to be used on any other ColdFire CPU. |
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*/ |
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/* |
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* The masking and priproty setting of interrupts on the 5272 is done |
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* via a set of 4 "Interrupt Controller Registers" (ICR). There is a |
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* loose mapping of vector number to register and internal bits, but |
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* a table is the easiest and quickest way to map them. |
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* |
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* Note that the external interrupts are edge triggered (unlike the |
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* internal interrupt sources which are level triggered). Which means |
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* they also need acknowledging via acknowledge bits. |
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*/ |
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struct irqmap { |
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unsigned int icr; |
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unsigned char index; |
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unsigned char ack; |
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}; |
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static struct irqmap intc_irqmap[MCFINT_VECMAX - MCFINT_VECBASE] = { |
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/*MCF_IRQ_SPURIOUS*/ { .icr = 0, .index = 0, .ack = 0, }, |
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/*MCF_IRQ_EINT1*/ { .icr = MCFSIM_ICR1, .index = 28, .ack = 1, }, |
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/*MCF_IRQ_EINT2*/ { .icr = MCFSIM_ICR1, .index = 24, .ack = 1, }, |
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/*MCF_IRQ_EINT3*/ { .icr = MCFSIM_ICR1, .index = 20, .ack = 1, }, |
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/*MCF_IRQ_EINT4*/ { .icr = MCFSIM_ICR1, .index = 16, .ack = 1, }, |
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/*MCF_IRQ_TIMER1*/ { .icr = MCFSIM_ICR1, .index = 12, .ack = 0, }, |
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/*MCF_IRQ_TIMER2*/ { .icr = MCFSIM_ICR1, .index = 8, .ack = 0, }, |
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/*MCF_IRQ_TIMER3*/ { .icr = MCFSIM_ICR1, .index = 4, .ack = 0, }, |
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/*MCF_IRQ_TIMER4*/ { .icr = MCFSIM_ICR1, .index = 0, .ack = 0, }, |
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/*MCF_IRQ_UART1*/ { .icr = MCFSIM_ICR2, .index = 28, .ack = 0, }, |
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/*MCF_IRQ_UART2*/ { .icr = MCFSIM_ICR2, .index = 24, .ack = 0, }, |
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/*MCF_IRQ_PLIP*/ { .icr = MCFSIM_ICR2, .index = 20, .ack = 0, }, |
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/*MCF_IRQ_PLIA*/ { .icr = MCFSIM_ICR2, .index = 16, .ack = 0, }, |
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/*MCF_IRQ_USB0*/ { .icr = MCFSIM_ICR2, .index = 12, .ack = 0, }, |
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/*MCF_IRQ_USB1*/ { .icr = MCFSIM_ICR2, .index = 8, .ack = 0, }, |
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/*MCF_IRQ_USB2*/ { .icr = MCFSIM_ICR2, .index = 4, .ack = 0, }, |
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/*MCF_IRQ_USB3*/ { .icr = MCFSIM_ICR2, .index = 0, .ack = 0, }, |
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/*MCF_IRQ_USB4*/ { .icr = MCFSIM_ICR3, .index = 28, .ack = 0, }, |
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/*MCF_IRQ_USB5*/ { .icr = MCFSIM_ICR3, .index = 24, .ack = 0, }, |
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/*MCF_IRQ_USB6*/ { .icr = MCFSIM_ICR3, .index = 20, .ack = 0, }, |
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/*MCF_IRQ_USB7*/ { .icr = MCFSIM_ICR3, .index = 16, .ack = 0, }, |
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/*MCF_IRQ_DMA*/ { .icr = MCFSIM_ICR3, .index = 12, .ack = 0, }, |
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/*MCF_IRQ_ERX*/ { .icr = MCFSIM_ICR3, .index = 8, .ack = 0, }, |
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/*MCF_IRQ_ETX*/ { .icr = MCFSIM_ICR3, .index = 4, .ack = 0, }, |
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/*MCF_IRQ_ENTC*/ { .icr = MCFSIM_ICR3, .index = 0, .ack = 0, }, |
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/*MCF_IRQ_QSPI*/ { .icr = MCFSIM_ICR4, .index = 28, .ack = 0, }, |
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/*MCF_IRQ_EINT5*/ { .icr = MCFSIM_ICR4, .index = 24, .ack = 1, }, |
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/*MCF_IRQ_EINT6*/ { .icr = MCFSIM_ICR4, .index = 20, .ack = 1, }, |
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/*MCF_IRQ_SWTO*/ { .icr = MCFSIM_ICR4, .index = 16, .ack = 0, }, |
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}; |
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/* |
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* The act of masking the interrupt also has a side effect of 'ack'ing |
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* an interrupt on this irq (for the external irqs). So this mask function |
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* is also an ack_mask function. |
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*/ |
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static void intc_irq_mask(struct irq_data *d) |
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{ |
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unsigned int irq = d->irq; |
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if ((irq >= MCFINT_VECBASE) && (irq <= MCFINT_VECMAX)) { |
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u32 v; |
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irq -= MCFINT_VECBASE; |
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v = 0x8 << intc_irqmap[irq].index; |
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writel(v, intc_irqmap[irq].icr); |
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} |
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} |
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static void intc_irq_unmask(struct irq_data *d) |
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{ |
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unsigned int irq = d->irq; |
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if ((irq >= MCFINT_VECBASE) && (irq <= MCFINT_VECMAX)) { |
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u32 v; |
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irq -= MCFINT_VECBASE; |
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v = 0xd << intc_irqmap[irq].index; |
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writel(v, intc_irqmap[irq].icr); |
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} |
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} |
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static void intc_irq_ack(struct irq_data *d) |
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{ |
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unsigned int irq = d->irq; |
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/* Only external interrupts are acked */ |
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if ((irq >= MCFINT_VECBASE) && (irq <= MCFINT_VECMAX)) { |
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irq -= MCFINT_VECBASE; |
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if (intc_irqmap[irq].ack) { |
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u32 v; |
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v = readl(intc_irqmap[irq].icr); |
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v &= (0x7 << intc_irqmap[irq].index); |
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v |= (0x8 << intc_irqmap[irq].index); |
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writel(v, intc_irqmap[irq].icr); |
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} |
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} |
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} |
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static int intc_irq_set_type(struct irq_data *d, unsigned int type) |
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{ |
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unsigned int irq = d->irq; |
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if ((irq >= MCFINT_VECBASE) && (irq <= MCFINT_VECMAX)) { |
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irq -= MCFINT_VECBASE; |
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if (intc_irqmap[irq].ack) { |
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u32 v; |
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v = readl(MCFSIM_PITR); |
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if (type == IRQ_TYPE_EDGE_FALLING) |
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v &= ~(0x1 << (32 - irq)); |
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else |
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v |= (0x1 << (32 - irq)); |
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writel(v, MCFSIM_PITR); |
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} |
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} |
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return 0; |
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} |
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/* |
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* Simple flow handler to deal with the external edge triggered interrupts. |
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* We need to be careful with the masking/acking due to the side effects |
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* of masking an interrupt. |
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*/ |
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static void intc_external_irq(struct irq_desc *desc) |
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{ |
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irq_desc_get_chip(desc)->irq_ack(&desc->irq_data); |
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handle_simple_irq(desc); |
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} |
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static struct irq_chip intc_irq_chip = { |
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.name = "CF-INTC", |
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.irq_mask = intc_irq_mask, |
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.irq_unmask = intc_irq_unmask, |
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.irq_mask_ack = intc_irq_mask, |
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.irq_ack = intc_irq_ack, |
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.irq_set_type = intc_irq_set_type, |
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}; |
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void __init init_IRQ(void) |
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{ |
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int irq, edge; |
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/* Mask all interrupt sources */ |
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writel(0x88888888, MCFSIM_ICR1); |
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writel(0x88888888, MCFSIM_ICR2); |
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writel(0x88888888, MCFSIM_ICR3); |
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writel(0x88888888, MCFSIM_ICR4); |
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for (irq = 0; (irq < NR_IRQS); irq++) { |
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irq_set_chip(irq, &intc_irq_chip); |
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edge = 0; |
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if ((irq >= MCFINT_VECBASE) && (irq <= MCFINT_VECMAX)) |
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edge = intc_irqmap[irq - MCFINT_VECBASE].ack; |
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if (edge) { |
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irq_set_irq_type(irq, IRQ_TYPE_EDGE_RISING); |
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irq_set_handler(irq, intc_external_irq); |
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} else { |
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irq_set_irq_type(irq, IRQ_TYPE_LEVEL_HIGH); |
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irq_set_handler(irq, handle_level_irq); |
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} |
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} |
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} |
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